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Commit | Line | Data |
---|---|---|
80a8b54b SH |
1 | /include/ "skeleton.dtsi" |
2 | ||
6953af77 SH |
3 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
4 | ||
80a8b54b SH |
5 | / { |
6 | compatible = "marvell,dove"; | |
7 | model = "Marvell Armada 88AP510 SoC"; | |
8 | ||
9139acd1 SH |
9 | aliases { |
10 | gpio0 = &gpio0; | |
11 | gpio1 = &gpio1; | |
12 | gpio2 = &gpio2; | |
13 | }; | |
14 | ||
2d299834 SH |
15 | cpus { |
16 | #address-cells = <1>; | |
17 | #size-cells = <0>; | |
18 | ||
19 | cpu0: cpu@0 { | |
20 | compatible = "marvell,pj4a", "marvell,sheeva-v7"; | |
21 | device_type = "cpu"; | |
22 | next-level-cache = <&l2>; | |
23 | reg = <0>; | |
24 | }; | |
25 | }; | |
26 | ||
27 | l2: l2-cache { | |
28 | compatible = "marvell,tauros2-cache"; | |
29 | marvell,tauros2-cache-features = <0>; | |
30 | }; | |
31 | ||
960ee4e7 SH |
32 | mbus { |
33 | compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; | |
34 | #address-cells = <2>; | |
35 | #size-cells = <1>; | |
36 | controller = <&mbusc>; | |
37 | pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ | |
38 | pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ | |
39 | ||
40 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */ | |
41 | MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */ | |
42 | MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */ | |
43 | MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ | |
44 | MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ | |
45 | }; | |
46 | ||
138ee960 | 47 | soc@f1000000 { |
80a8b54b | 48 | compatible = "simple-bus"; |
80a8b54b SH |
49 | #address-cells = <1>; |
50 | #size-cells = <1>; | |
138ee960 SH |
51 | interrupt-parent = <&intc>; |
52 | ||
53 | ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */ | |
54 | 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */ | |
55 | 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */ | |
56 | 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */ | |
57 | 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */ | |
58 | 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */ | |
59 | 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ | |
60 | 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ | |
80a8b54b | 61 | |
960ee4e7 SH |
62 | mbusc: mbus-ctrl@20000 { |
63 | compatible = "marvell,mbus-controller"; | |
64 | reg = <0x20000 0x80>, <0x800100 0x8>; | |
65 | }; | |
66 | ||
953b710c SH |
67 | timer: timer@20300 { |
68 | compatible = "marvell,orion-timer"; | |
69 | reg = <0x20300 0x20>; | |
70 | interrupt-parent = <&bridge_intc>; | |
71 | interrupts = <1>, <2>; | |
72 | clocks = <&core_clk 0>; | |
73 | }; | |
74 | ||
75 | intc: main-interrupt-ctrl@20200 { | |
138ee960 SH |
76 | compatible = "marvell,orion-intc"; |
77 | interrupt-controller; | |
78 | #interrupt-cells = <1>; | |
953b710c SH |
79 | reg = <0x20200 0x10>, <0x20210 0x10>; |
80 | }; | |
81 | ||
82 | bridge_intc: bridge-interrupt-ctrl@20110 { | |
83 | compatible = "marvell,orion-bridge-intc"; | |
84 | interrupt-controller; | |
85 | #interrupt-cells = <1>; | |
86 | reg = <0x20110 0x8>; | |
87 | interrupts = <0>; | |
88 | marvell,#interrupts = <5>; | |
138ee960 SH |
89 | }; |
90 | ||
5b03df9a SH |
91 | core_clk: core-clocks@d0214 { |
92 | compatible = "marvell,dove-core-clock"; | |
93 | reg = <0xd0214 0x4>; | |
94 | #clock-cells = <1>; | |
95 | }; | |
96 | ||
2d299834 | 97 | gate_clk: clock-gating-ctrl@d0038 { |
5b03df9a SH |
98 | compatible = "marvell,dove-gating-clock"; |
99 | reg = <0xd0038 0x4>; | |
100 | clocks = <&core_clk 0>; | |
101 | #clock-cells = <1>; | |
102 | }; | |
103 | ||
2d299834 | 104 | thermal: thermal-diode@d001c { |
c3117ede AL |
105 | compatible = "marvell,dove-thermal"; |
106 | reg = <0xd001c 0x0c>, <0xd005c 0x08>; | |
107 | }; | |
108 | ||
80a8b54b SH |
109 | uart0: serial@12000 { |
110 | compatible = "ns16550a"; | |
111 | reg = <0x12000 0x100>; | |
112 | reg-shift = <2>; | |
113 | interrupts = <7>; | |
8be7a962 | 114 | clocks = <&core_clk 0>; |
80a8b54b SH |
115 | status = "disabled"; |
116 | }; | |
117 | ||
118 | uart1: serial@12100 { | |
119 | compatible = "ns16550a"; | |
120 | reg = <0x12100 0x100>; | |
121 | reg-shift = <2>; | |
122 | interrupts = <8>; | |
8be7a962 | 123 | clocks = <&core_clk 0>; |
2d299834 SH |
124 | pinctrl-0 = <&pmx_uart1>; |
125 | pinctrl-names = "default"; | |
80a8b54b SH |
126 | status = "disabled"; |
127 | }; | |
128 | ||
129 | uart2: serial@12200 { | |
130 | compatible = "ns16550a"; | |
131 | reg = <0x12000 0x100>; | |
132 | reg-shift = <2>; | |
133 | interrupts = <9>; | |
8be7a962 | 134 | clocks = <&core_clk 0>; |
80a8b54b SH |
135 | status = "disabled"; |
136 | }; | |
137 | ||
138 | uart3: serial@12300 { | |
139 | compatible = "ns16550a"; | |
140 | reg = <0x12100 0x100>; | |
141 | reg-shift = <2>; | |
142 | interrupts = <10>; | |
8be7a962 | 143 | clocks = <&core_clk 0>; |
80a8b54b SH |
144 | status = "disabled"; |
145 | }; | |
146 | ||
2d299834 | 147 | gpio0: gpio-ctrl@d0400 { |
80a8b54b SH |
148 | compatible = "marvell,orion-gpio"; |
149 | #gpio-cells = <2>; | |
150 | gpio-controller; | |
151 | reg = <0xd0400 0x20>; | |
9139acd1 SH |
152 | ngpios = <32>; |
153 | interrupt-controller; | |
fd2704e8 | 154 | #interrupt-cells = <2>; |
80a8b54b SH |
155 | interrupts = <12>, <13>, <14>, <60>; |
156 | }; | |
157 | ||
2d299834 | 158 | gpio1: gpio-ctrl@d0420 { |
80a8b54b SH |
159 | compatible = "marvell,orion-gpio"; |
160 | #gpio-cells = <2>; | |
161 | gpio-controller; | |
162 | reg = <0xd0420 0x20>; | |
9139acd1 SH |
163 | ngpios = <32>; |
164 | interrupt-controller; | |
fd2704e8 | 165 | #interrupt-cells = <2>; |
80a8b54b SH |
166 | interrupts = <61>; |
167 | }; | |
168 | ||
2d299834 | 169 | gpio2: gpio-ctrl@e8400 { |
80a8b54b SH |
170 | compatible = "marvell,orion-gpio"; |
171 | #gpio-cells = <2>; | |
172 | gpio-controller; | |
173 | reg = <0xe8400 0x0c>; | |
9139acd1 SH |
174 | ngpios = <8>; |
175 | }; | |
176 | ||
2d299834 | 177 | pinctrl: pin-ctrl@d0200 { |
9139acd1 SH |
178 | compatible = "marvell,dove-pinctrl"; |
179 | reg = <0xd0200 0x10>; | |
db7d77e6 | 180 | clocks = <&gate_clk 22>; |
2d299834 SH |
181 | |
182 | pmx_gpio_0: pmx-gpio-0 { | |
183 | marvell,pins = "mpp0"; | |
184 | marvell,function = "gpio"; | |
185 | }; | |
186 | ||
187 | pmx_gpio_1: pmx-gpio-1 { | |
188 | marvell,pins = "mpp1"; | |
189 | marvell,function = "gpio"; | |
190 | }; | |
191 | ||
192 | pmx_gpio_2: pmx-gpio-2 { | |
193 | marvell,pins = "mpp2"; | |
194 | marvell,function = "gpio"; | |
195 | }; | |
196 | ||
197 | pmx_gpio_3: pmx-gpio-3 { | |
198 | marvell,pins = "mpp3"; | |
199 | marvell,function = "gpio"; | |
200 | }; | |
201 | ||
202 | pmx_gpio_4: pmx-gpio-4 { | |
203 | marvell,pins = "mpp4"; | |
204 | marvell,function = "gpio"; | |
205 | }; | |
206 | ||
207 | pmx_gpio_5: pmx-gpio-5 { | |
208 | marvell,pins = "mpp5"; | |
209 | marvell,function = "gpio"; | |
210 | }; | |
211 | ||
212 | pmx_gpio_6: pmx-gpio-6 { | |
213 | marvell,pins = "mpp6"; | |
214 | marvell,function = "gpio"; | |
215 | }; | |
216 | ||
217 | pmx_gpio_7: pmx-gpio-7 { | |
218 | marvell,pins = "mpp7"; | |
219 | marvell,function = "gpio"; | |
220 | }; | |
221 | ||
222 | pmx_gpio_8: pmx-gpio-8 { | |
223 | marvell,pins = "mpp8"; | |
224 | marvell,function = "gpio"; | |
225 | }; | |
226 | ||
227 | pmx_gpio_9: pmx-gpio-9 { | |
228 | marvell,pins = "mpp9"; | |
229 | marvell,function = "gpio"; | |
230 | }; | |
231 | ||
232 | pmx_gpio_10: pmx-gpio-10 { | |
233 | marvell,pins = "mpp10"; | |
234 | marvell,function = "gpio"; | |
235 | }; | |
236 | ||
237 | pmx_gpio_11: pmx-gpio-11 { | |
238 | marvell,pins = "mpp11"; | |
239 | marvell,function = "gpio"; | |
240 | }; | |
241 | ||
242 | pmx_gpio_12: pmx-gpio-12 { | |
243 | marvell,pins = "mpp12"; | |
244 | marvell,function = "gpio"; | |
245 | }; | |
246 | ||
247 | pmx_gpio_13: pmx-gpio-13 { | |
248 | marvell,pins = "mpp13"; | |
249 | marvell,function = "gpio"; | |
250 | }; | |
251 | ||
252 | pmx_gpio_14: pmx-gpio-14 { | |
253 | marvell,pins = "mpp14"; | |
254 | marvell,function = "gpio"; | |
255 | }; | |
256 | ||
257 | pmx_gpio_15: pmx-gpio-15 { | |
258 | marvell,pins = "mpp15"; | |
259 | marvell,function = "gpio"; | |
260 | }; | |
261 | ||
262 | pmx_gpio_16: pmx-gpio-16 { | |
263 | marvell,pins = "mpp16"; | |
264 | marvell,function = "gpio"; | |
265 | }; | |
266 | ||
267 | pmx_gpio_17: pmx-gpio-17 { | |
268 | marvell,pins = "mpp17"; | |
269 | marvell,function = "gpio"; | |
270 | }; | |
271 | ||
272 | pmx_gpio_18: pmx-gpio-18 { | |
273 | marvell,pins = "mpp18"; | |
274 | marvell,function = "gpio"; | |
275 | }; | |
276 | ||
277 | pmx_gpio_19: pmx-gpio-19 { | |
278 | marvell,pins = "mpp19"; | |
279 | marvell,function = "gpio"; | |
280 | }; | |
281 | ||
282 | pmx_gpio_20: pmx-gpio-20 { | |
283 | marvell,pins = "mpp20"; | |
284 | marvell,function = "gpio"; | |
285 | }; | |
286 | ||
287 | pmx_gpio_21: pmx-gpio-21 { | |
288 | marvell,pins = "mpp21"; | |
289 | marvell,function = "gpio"; | |
290 | }; | |
291 | ||
292 | pmx_camera: pmx-camera { | |
293 | marvell,pins = "mpp_camera"; | |
294 | marvell,function = "camera"; | |
295 | }; | |
296 | ||
297 | pmx_camera_gpio: pmx-camera-gpio { | |
298 | marvell,pins = "mpp_camera"; | |
299 | marvell,function = "gpio"; | |
300 | }; | |
301 | ||
302 | pmx_sdio0: pmx-sdio0 { | |
303 | marvell,pins = "mpp_sdio0"; | |
304 | marvell,function = "sdio0"; | |
305 | }; | |
306 | ||
307 | pmx_sdio0_gpio: pmx-sdio0-gpio { | |
308 | marvell,pins = "mpp_sdio0"; | |
309 | marvell,function = "gpio"; | |
310 | }; | |
311 | ||
312 | pmx_sdio1: pmx-sdio1 { | |
313 | marvell,pins = "mpp_sdio1"; | |
314 | marvell,function = "sdio1"; | |
315 | }; | |
316 | ||
317 | pmx_sdio1_gpio: pmx-sdio1-gpio { | |
318 | marvell,pins = "mpp_sdio1"; | |
319 | marvell,function = "gpio"; | |
320 | }; | |
321 | ||
322 | pmx_audio1_gpio: pmx-audio1-gpio { | |
323 | marvell,pins = "mpp_audio1"; | |
324 | marvell,function = "gpio"; | |
325 | }; | |
326 | ||
327 | pmx_spi0: pmx-spi0 { | |
328 | marvell,pins = "mpp_spi0"; | |
329 | marvell,function = "spi0"; | |
330 | }; | |
331 | ||
332 | pmx_spi0_gpio: pmx-spi0-gpio { | |
333 | marvell,pins = "mpp_spi0"; | |
334 | marvell,function = "gpio"; | |
335 | }; | |
336 | ||
337 | pmx_uart1: pmx-uart1 { | |
338 | marvell,pins = "mpp_uart1"; | |
339 | marvell,function = "uart1"; | |
340 | }; | |
341 | ||
342 | pmx_uart1_gpio: pmx-uart1-gpio { | |
343 | marvell,pins = "mpp_uart1"; | |
344 | marvell,function = "gpio"; | |
345 | }; | |
346 | ||
347 | pmx_nand: pmx-nand { | |
348 | marvell,pins = "mpp_nand"; | |
349 | marvell,function = "nand"; | |
350 | }; | |
351 | ||
352 | pmx_nand_gpo: pmx-nand-gpo { | |
353 | marvell,pins = "mpp_nand"; | |
354 | marvell,function = "gpo"; | |
355 | }; | |
80a8b54b SH |
356 | }; |
357 | ||
2d299834 | 358 | spi0: spi-ctrl@10600 { |
80a8b54b SH |
359 | compatible = "marvell,orion-spi"; |
360 | #address-cells = <1>; | |
361 | #size-cells = <0>; | |
362 | cell-index = <0>; | |
363 | interrupts = <6>; | |
364 | reg = <0x10600 0x28>; | |
5b03df9a | 365 | clocks = <&core_clk 0>; |
2d299834 SH |
366 | pinctrl-0 = <&pmx_spi0>; |
367 | pinctrl-names = "default"; | |
80a8b54b SH |
368 | status = "disabled"; |
369 | }; | |
370 | ||
2d299834 | 371 | spi1: spi-ctrl@14600 { |
80a8b54b SH |
372 | compatible = "marvell,orion-spi"; |
373 | #address-cells = <1>; | |
374 | #size-cells = <0>; | |
375 | cell-index = <1>; | |
376 | interrupts = <5>; | |
377 | reg = <0x14600 0x28>; | |
5b03df9a | 378 | clocks = <&core_clk 0>; |
80a8b54b SH |
379 | status = "disabled"; |
380 | }; | |
381 | ||
2d299834 | 382 | i2c0: i2c-ctrl@11000 { |
80a8b54b SH |
383 | compatible = "marvell,mv64xxx-i2c"; |
384 | reg = <0x11000 0x20>; | |
385 | #address-cells = <1>; | |
386 | #size-cells = <0>; | |
387 | interrupts = <11>; | |
388 | clock-frequency = <400000>; | |
389 | timeout-ms = <1000>; | |
5b03df9a | 390 | clocks = <&core_clk 0>; |
80a8b54b SH |
391 | status = "disabled"; |
392 | }; | |
393 | ||
a1abcd7c SH |
394 | ehci0: usb-host@50000 { |
395 | compatible = "marvell,orion-ehci"; | |
396 | reg = <0x50000 0x1000>; | |
397 | interrupts = <24>; | |
398 | clocks = <&gate_clk 0>; | |
399 | status = "okay"; | |
400 | }; | |
401 | ||
402 | ehci1: usb-host@51000 { | |
403 | compatible = "marvell,orion-ehci"; | |
404 | reg = <0x51000 0x1000>; | |
405 | interrupts = <25>; | |
406 | clocks = <&gate_clk 1>; | |
407 | status = "okay"; | |
408 | }; | |
409 | ||
2d299834 | 410 | sdio0: sdio-host@92000 { |
80a8b54b SH |
411 | compatible = "marvell,dove-sdhci"; |
412 | reg = <0x92000 0x100>; | |
413 | interrupts = <35>, <37>; | |
5b03df9a | 414 | clocks = <&gate_clk 8>; |
2d299834 SH |
415 | pinctrl-0 = <&pmx_sdio0>; |
416 | pinctrl-names = "default"; | |
80a8b54b SH |
417 | status = "disabled"; |
418 | }; | |
419 | ||
2d299834 | 420 | sdio1: sdio-host@90000 { |
80a8b54b SH |
421 | compatible = "marvell,dove-sdhci"; |
422 | reg = <0x90000 0x100>; | |
423 | interrupts = <36>, <38>; | |
5b03df9a | 424 | clocks = <&gate_clk 9>; |
2d299834 SH |
425 | pinctrl-0 = <&pmx_sdio1>; |
426 | pinctrl-names = "default"; | |
80a8b54b SH |
427 | status = "disabled"; |
428 | }; | |
429 | ||
2d299834 | 430 | sata0: sata-host@a0000 { |
80a8b54b SH |
431 | compatible = "marvell,orion-sata"; |
432 | reg = <0xa0000 0x2400>; | |
433 | interrupts = <62>; | |
5b03df9a | 434 | clocks = <&gate_clk 3>; |
80a8b54b SH |
435 | nr-ports = <1>; |
436 | status = "disabled"; | |
437 | }; | |
a458926e | 438 | |
2d299834 | 439 | rtc: real-time-clock@d8500 { |
85c0c13d JFM |
440 | compatible = "marvell,orion-rtc"; |
441 | reg = <0xd8500 0x20>; | |
442 | }; | |
443 | ||
2d299834 | 444 | crypto: crypto-engine@30000 { |
a458926e SH |
445 | compatible = "marvell,orion-crypto"; |
446 | reg = <0x30000 0x10000>, | |
447 | <0xc8000000 0x800>; | |
448 | reg-names = "regs", "sram"; | |
449 | interrupts = <31>; | |
5b03df9a | 450 | clocks = <&gate_clk 15>; |
a458926e SH |
451 | status = "okay"; |
452 | }; | |
49f175b9 SH |
453 | |
454 | xor0: dma-engine@60800 { | |
455 | compatible = "marvell,orion-xor"; | |
456 | reg = <0x60800 0x100 | |
457 | 0x60a00 0x100>; | |
458 | clocks = <&gate_clk 23>; | |
a458926e | 459 | status = "okay"; |
49f175b9 SH |
460 | |
461 | channel0 { | |
462 | interrupts = <39>; | |
463 | dmacap,memcpy; | |
464 | dmacap,xor; | |
465 | }; | |
466 | ||
467 | channel1 { | |
468 | interrupts = <40>; | |
469 | dmacap,memset; | |
470 | dmacap,memcpy; | |
471 | dmacap,xor; | |
472 | }; | |
473 | }; | |
474 | ||
475 | xor1: dma-engine@60900 { | |
476 | compatible = "marvell,orion-xor"; | |
477 | reg = <0x60900 0x100 | |
478 | 0x60b00 0x100>; | |
479 | clocks = <&gate_clk 24>; | |
480 | status = "okay"; | |
481 | ||
482 | channel0 { | |
483 | interrupts = <42>; | |
484 | dmacap,memcpy; | |
485 | dmacap,xor; | |
486 | }; | |
487 | ||
488 | channel1 { | |
489 | interrupts = <43>; | |
490 | dmacap,memset; | |
491 | dmacap,memcpy; | |
492 | dmacap,xor; | |
493 | }; | |
a458926e | 494 | }; |
4c3f6b86 SH |
495 | |
496 | mdio: mdio-bus@72004 { | |
497 | compatible = "marvell,orion-mdio"; | |
498 | #address-cells = <1>; | |
499 | #size-cells = <0>; | |
500 | reg = <0x72004 0x84>; | |
501 | interrupts = <30>; | |
502 | clocks = <&gate_clk 2>; | |
503 | status = "disabled"; | |
504 | ||
505 | ethphy: ethernet-phy { | |
506 | device-type = "ethernet-phy"; | |
507 | /* set phy address in board file */ | |
508 | }; | |
509 | }; | |
510 | ||
511 | eth: ethernet-controller@72000 { | |
512 | compatible = "marvell,orion-eth"; | |
513 | #address-cells = <1>; | |
514 | #size-cells = <0>; | |
515 | reg = <0x72000 0x4000>; | |
516 | clocks = <&gate_clk 2>; | |
517 | marvell,tx-checksum-limit = <1600>; | |
518 | status = "disabled"; | |
519 | ||
520 | ethernet-port@0 { | |
521 | device_type = "network"; | |
522 | compatible = "marvell,orion-eth-port"; | |
523 | reg = <0>; | |
524 | interrupts = <29>; | |
525 | /* overwrite MAC address in bootloader */ | |
526 | local-mac-address = [00 00 00 00 00 00]; | |
527 | phy-handle = <ðphy>; | |
528 | }; | |
529 | }; | |
80a8b54b SH |
530 | }; |
531 | }; |