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Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
c46ab061 TL |
2 | |
3 | #include "dm814x-clocks.dtsi" | |
4 | ||
5d7e23a7 TL |
5 | /* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */ |
6 | &adpll_hdvic_ck { | |
7 | status = "disabled"; | |
8 | }; | |
9 | ||
10 | &adpll_l3_ck { | |
11 | status = "disabled"; | |
12 | }; | |
13 | ||
14 | &adpll_dss_ck { | |
15 | status = "disabled"; | |
16 | }; | |
17 | ||
18 | /* Compared to dm814x, dra62x has interconnect clocks on isp PLL */ | |
19 | &sysclk4_ck { | |
20 | clocks = <&adpll_isp_ck 1>; | |
21 | }; | |
22 | ||
23 | &sysclk5_ck { | |
24 | clocks = <&adpll_isp_ck 1>; | |
25 | }; | |
26 | ||
27 | &sysclk6_ck { | |
28 | clocks = <&adpll_isp_ck 1>; | |
29 | }; | |
30 | ||
c46ab061 TL |
31 | /* |
32 | * Compared to dm814x, dra62x has different shifts and more mux options. | |
33 | * Please add the extra options for ysclk_14 and 16 if really needed. | |
34 | */ | |
35 | &timer1_fck { | |
36 | clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck | |
37 | &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; | |
38 | ti,bit-shift = <4>; | |
39 | }; | |
40 | ||
41 | &timer2_fck { | |
42 | clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck | |
43 | &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; | |
44 | ti,bit-shift = <8>; | |
45 | }; |