]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - arch/arm/boot/dts/dra7-evm.dts
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: dra72-evm: Add MMC nodes
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / dra7-evm.dts
CommitLineData
6e58b8f1
S		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
38b248db 10#include "dra74x.dtsi"
c7cc9ba1 11#include <dt-bindings/gpio/gpio.h>
6e58b8f1
S		 12
13/ {
38b248db
RN		 14 model = "TI DRA742";
15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
6e58b8f1
S		 16
17 memory {
18 device_type = "memory";
19 reg = <0x80000000 0x60000000>; /* 1536 MB */
20 };
6cf02dbb
B		 21
22 mmc2_3v3: fixedregulator-mmc2 {
23 compatible = "regulator-fixed";
24 regulator-name = "mmc2_3v3";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 };
c7cc9ba1
LV		 28
29 vtt_fixed: fixedregulator-vtt {
30 compatible = "regulator-fixed";
31 regulator-name = "vtt_fixed";
32 regulator-min-microvolt = <1350000>;
33 regulator-max-microvolt = <1350000>;
34 regulator-always-on;
35 regulator-boot-on;
36 enable-active-high;
37 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
38 };
6e58b8f1
S		 39};
40
41&dra7_pmx_core {
c7cc9ba1
LV		 42 pinctrl-names = "default";
43 pinctrl-0 = <&vtt_pin>;
44
45 vtt_pin: pinmux_vtt_pin {
46 pinctrl-single,pins = <
47 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
48 >;
49 };
50
6e58b8f1
S		 51 i2c1_pins: pinmux_i2c1_pins {
52 pinctrl-single,pins = <
53 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
54 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
55 >;
56 };
57
58 i2c2_pins: pinmux_i2c2_pins {
59 pinctrl-single,pins = <
60 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
61 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
62 >;
63 };
64
65 i2c3_pins: pinmux_i2c3_pins {
66 pinctrl-single,pins = <
544d63d0
RQ		 67 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
68 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
6e58b8f1
S		 69 >;
70 };
71
72 mcspi1_pins: pinmux_mcspi1_pins {
73 pinctrl-single,pins = <
68e4d9e5
NM		 74 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
75 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
76 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
77 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
68e4d9e5
NM		 78 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
79 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
6e58b8f1
S		 80 >;
81 };
82
83 mcspi2_pins: pinmux_mcspi2_pins {
84 pinctrl-single,pins = <
85 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
86 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
87 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
88 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
89 >;
90 };
91
92 uart1_pins: pinmux_uart1_pins {
93 pinctrl-single,pins = <
94 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
95 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
96 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
97 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
98 >;
99 };
100
101 uart2_pins: pinmux_uart2_pins {
102 pinctrl-single,pins = <
103 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
104 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
105 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
106 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
107 >;
108 };
109
110 uart3_pins: pinmux_uart3_pins {
111 pinctrl-single,pins = <
112 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
113 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
114 >;
115 };
dc2dd5b8
SP		 116
117 qspi1_pins: pinmux_qspi1_pins {
118 pinctrl-single,pins = <
119 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
120 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
121 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
122 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
123 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
124 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
125 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
126 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
127 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
128 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
129 >;
130 };
4b4437cb
RQ		 131
132 usb1_pins: pinmux_usb1_pins {
133 pinctrl-single,pins = <
134 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
135 >;
136 };
137
138 usb2_pins: pinmux_usb2_pins {
139 pinctrl-single,pins = <
140 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
141 >;
142 };
ff66a3c8
MS		 143
144 nand_flash_x16: nand_flash_x16 {
145 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
146 * So NAND flash requires following switch settings:
147 * SW5.9 (GPMC_WPN) = LOW
148 * SW5.1 (NAND_BOOTn) = HIGH */
149 pinctrl-single,pins = <
150 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
151 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
152 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
153 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
154 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
155 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
156 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
157 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
158 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
159 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
160 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
161 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
162 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
163 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
164 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
165 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
166 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
167 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
168 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
169 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
170 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
171 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
172 >;
173 };
8d039290
M		 174
175 cpsw_default: cpsw_default {
176 pinctrl-single,pins = <
177 /* Slave 1 */
178 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
179 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
180 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
181 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
182 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
183 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
184 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
185 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
186 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
187 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
188 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
189 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
190
191 /* Slave 2 */
192 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
193 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
194 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
195 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
196 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
197 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
198 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
199 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
200 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
201 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
202 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
203 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
204 >;
205
206 };
207
208 cpsw_sleep: cpsw_sleep {
209 pinctrl-single,pins = <
210 /* Slave 1 */
211 0x250 (MUX_MODE15)
212 0x254 (MUX_MODE15)
213 0x258 (MUX_MODE15)
214 0x25c (MUX_MODE15)
215 0x260 (MUX_MODE15)
216 0x264 (MUX_MODE15)
217 0x268 (MUX_MODE15)
218 0x26c (MUX_MODE15)
219 0x270 (MUX_MODE15)
220 0x274 (MUX_MODE15)
221 0x278 (MUX_MODE15)
222 0x27c (MUX_MODE15)
223
224 /* Slave 2 */
225 0x198 (MUX_MODE15)
226 0x19c (MUX_MODE15)
227 0x1a0 (MUX_MODE15)
228 0x1a4 (MUX_MODE15)
229 0x1a8 (MUX_MODE15)
230 0x1ac (MUX_MODE15)
231 0x1b0 (MUX_MODE15)
232 0x1b4 (MUX_MODE15)
233 0x1b8 (MUX_MODE15)
234 0x1bc (MUX_MODE15)
235 0x1c0 (MUX_MODE15)
236 0x1c4 (MUX_MODE15)
237 >;
238 };
239
240 davinci_mdio_default: davinci_mdio_default {
241 pinctrl-single,pins = <
242 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
243 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
244 >;
245 };
246
247 davinci_mdio_sleep: davinci_mdio_sleep {
248 pinctrl-single,pins = <
249 0x23c (MUX_MODE15)
250 0x240 (MUX_MODE15)
251 >;
252 };
253
6e58b8f1
S		 254};
255
256&i2c1 {
257 status = "okay";
258 pinctrl-names = "default";
259 pinctrl-0 = <&i2c1_pins>;
260 clock-frequency = <400000>;
c56a831c
K		 261
262 tps659038: tps659038@58 {
263 compatible = "ti,tps659038";
264 reg = <0x58>;
265
266 tps659038_pmic {
267 compatible = "ti,tps659038-pmic";
268
269 regulators {
270 smps123_reg: smps123 {
271 /* VDD_MPU */
272 regulator-name = "smps123";
273 regulator-min-microvolt = < 850000>;
274 regulator-max-microvolt = <1250000>;
275 regulator-always-on;
276 regulator-boot-on;
277 };
278
279 smps45_reg: smps45 {
280 /* VDD_DSPEVE */
281 regulator-name = "smps45";
282 regulator-min-microvolt = < 850000>;
283 regulator-max-microvolt = <1150000>;
284 regulator-boot-on;
285 };
286
287 smps6_reg: smps6 {
288 /* VDD_GPU - over VDD_SMPS6 */
289 regulator-name = "smps6";
290 regulator-min-microvolt = <850000>;
291 regulator-max-microvolt = <12500000>;
292 regulator-boot-on;
293 };
294
295 smps7_reg: smps7 {
296 /* CORE_VDD */
297 regulator-name = "smps7";
298 regulator-min-microvolt = <850000>;
299 regulator-max-microvolt = <1030000>;
300 regulator-always-on;
301 regulator-boot-on;
302 };
303
304 smps8_reg: smps8 {
305 /* VDD_IVAHD */
306 regulator-name = "smps8";
307 regulator-min-microvolt = < 850000>;
308 regulator-max-microvolt = <1250000>;
309 regulator-boot-on;
310 };
311
312 smps9_reg: smps9 {
313 /* VDDS1V8 */
314 regulator-name = "smps9";
315 regulator-min-microvolt = <1800000>;
316 regulator-max-microvolt = <1800000>;
317 regulator-always-on;
318 regulator-boot-on;
319 };
320
321 ldo1_reg: ldo1 {
322 /* LDO1_OUT --> SDIO */
323 regulator-name = "ldo1";
324 regulator-min-microvolt = <1800000>;
325 regulator-max-microvolt = <3300000>;
326 regulator-boot-on;
327 };
328
329 ldo2_reg: ldo2 {
330 /* VDD_RTCIO */
331 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
332 regulator-name = "ldo2";
333 regulator-min-microvolt = <3300000>;
334 regulator-max-microvolt = <3300000>;
335 regulator-boot-on;
336 };
337
338 ldo3_reg: ldo3 {
339 /* VDDA_1V8_PHY */
340 regulator-name = "ldo3";
341 regulator-min-microvolt = <1800000>;
342 regulator-max-microvolt = <1800000>;
e120fb45 343 regulator-always-on;
c56a831c
K		 344 regulator-boot-on;
345 };
346
347 ldo9_reg: ldo9 {
348 /* VDD_RTC */
349 regulator-name = "ldo9";
350 regulator-min-microvolt = <1050000>;
351 regulator-max-microvolt = <1050000>;
352 regulator-boot-on;
353 };
354
355 ldoln_reg: ldoln {
356 /* VDDA_1V8_PLL */
357 regulator-name = "ldoln";
358 regulator-min-microvolt = <1800000>;
359 regulator-max-microvolt = <1800000>;
360 regulator-always-on;
361 regulator-boot-on;
362 };
363
364 ldousb_reg: ldousb {
365 /* VDDA_3V_USB: VDDA_USBHS33 */
366 regulator-name = "ldousb";
367 regulator-min-microvolt = <3300000>;
368 regulator-max-microvolt = <3300000>;
369 regulator-boot-on;
370 };
371 };
372 };
373 };
6e58b8f1
S		 374};
375
376&i2c2 {
377 status = "okay";
378 pinctrl-names = "default";
379 pinctrl-0 = <&i2c2_pins>;
380 clock-frequency = <400000>;
381};
382
383&i2c3 {
384 status = "okay";
385 pinctrl-names = "default";
386 pinctrl-0 = <&i2c3_pins>;
544d63d0 387 clock-frequency = <400000>;
6e58b8f1
S		 388};
389
390&mcspi1 {
391 status = "okay";
392 pinctrl-names = "default";
393 pinctrl-0 = <&mcspi1_pins>;
394};
395
396&mcspi2 {
397 status = "okay";
398 pinctrl-names = "default";
399 pinctrl-0 = <&mcspi2_pins>;
400};
401
402&uart1 {
403 status = "okay";
404 pinctrl-names = "default";
405 pinctrl-0 = <&uart1_pins>;
66b04369
NM		 406 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
407 <&dra7_pmx_core 0x3e0>;
6e58b8f1
S		 408};
409
410&uart2 {
411 status = "okay";
412 pinctrl-names = "default";
413 pinctrl-0 = <&uart2_pins>;
414};
415
416&uart3 {
417 status = "okay";
418 pinctrl-names = "default";
419 pinctrl-0 = <&uart3_pins>;
420};
bf1788df
B		 421
422&mmc1 {
423 status = "okay";
424 vmmc-supply = <&ldo1_reg>;
425 bus-width = <4>;
426};
6cf02dbb
B		 427
428&mmc2 {
429 status = "okay";
430 vmmc-supply = <&mmc2_3v3>;
431 bus-width = <8>;
432};
22f1e7ef
K		 433
434&cpu0 {
435 cpu0-supply = <&smps123_reg>;
436};
dc2dd5b8
SP		 437
438&qspi {
439 status = "okay";
440 pinctrl-names = "default";
441 pinctrl-0 = <&qspi1_pins>;
442
443 spi-max-frequency = <48000000>;
444 m25p80@0 {
445 compatible = "s25fl256s1";
446 spi-max-frequency = <48000000>;
447 reg = <0>;
448 spi-tx-bus-width = <1>;
449 spi-rx-bus-width = <4>;
450 spi-cpol;
451 spi-cpha;
452 #address-cells = <1>;
453 #size-cells = <1>;
454
455 /* MTD partition table.
456 * The ROM checks the first four physical blocks
457 * for a valid file to boot and the flash here is
458 * 64KiB block size.
459 */
460 partition@0 {
461 label = "QSPI.SPL";
462 reg = <0x00000000 0x000010000>;
463 };
464 partition@1 {
465 label = "QSPI.SPL.backup1";
466 reg = <0x00010000 0x00010000>;
467 };
468 partition@2 {
469 label = "QSPI.SPL.backup2";
470 reg = <0x00020000 0x00010000>;
471 };
472 partition@3 {
473 label = "QSPI.SPL.backup3";
474 reg = <0x00030000 0x00010000>;
475 };
476 partition@4 {
477 label = "QSPI.u-boot";
478 reg = <0x00040000 0x00100000>;
479 };
480 partition@5 {
481 label = "QSPI.u-boot-spl-os";
482 reg = <0x00140000 0x00010000>;
483 };
484 partition@6 {
485 label = "QSPI.u-boot-env";
486 reg = <0x00150000 0x00010000>;
487 };
488 partition@7 {
489 label = "QSPI.u-boot-env.backup1";
490 reg = <0x00160000 0x0010000>;
491 };
492 partition@8 {
493 label = "QSPI.kernel";
494 reg = <0x00170000 0x0800000>;
495 };
496 partition@9 {
497 label = "QSPI.file-system";
498 reg = <0x00970000 0x01690000>;
499 };
500 };
501};
4b4437cb
RQ		 502
503&usb1 {
504 dr_mode = "peripheral";
505 pinctrl-names = "default";
506 pinctrl-0 = <&usb1_pins>;
507};
508
509&usb2 {
510 dr_mode = "host";
511 pinctrl-names = "default";
512 pinctrl-0 = <&usb2_pins>;
513};
ff66a3c8
MS		 514
515&elm {
516 status = "okay";
517};
518
519&gpmc {
520 status = "okay";
521 pinctrl-names = "default";
522 pinctrl-0 = <&nand_flash_x16>;
523 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
524 nand@0,0 {
525 reg = <0 0 4>; /* device IO registers */
526 ti,nand-ecc-opt = "bch8";
527 ti,elm-id = <&elm>;
528 nand-bus-width = <16>;
529 gpmc,device-width = <2>;
530 gpmc,sync-clk-ps = <0>;
531 gpmc,cs-on-ns = <0>;
5990047c
RQ		 532 gpmc,cs-rd-off-ns = <80>;
533 gpmc,cs-wr-off-ns = <80>;
ff66a3c8 534 gpmc,adv-on-ns = <0>;
5990047c
RQ		 535 gpmc,adv-rd-off-ns = <60>;
536 gpmc,adv-wr-off-ns = <60>;
537 gpmc,we-on-ns = <10>;
538 gpmc,we-off-ns = <50>;
539 gpmc,oe-on-ns = <4>;
540 gpmc,oe-off-ns = <40>;
541 gpmc,access-ns = <40>;
542 gpmc,wr-access-ns = <80>;
543 gpmc,rd-cycle-ns = <80>;
544 gpmc,wr-cycle-ns = <80>;
ff66a3c8
MS		 545 gpmc,bus-turnaround-ns = <0>;
546 gpmc,cycle2cycle-delay-ns = <0>;
547 gpmc,clk-activation-ns = <0>;
548 gpmc,wait-monitoring-ns = <0>;
549 gpmc,wr-data-mux-bus-ns = <0>;
550 /* MTD partition table */
551 /* All SPL-* partitions are sized to minimal length
552 * which can be independently programmable. For
553 * NAND flash this is equal to size of erase-block */
554 #address-cells = <1>;
555 #size-cells = <1>;
556 partition@0 {
557 label = "NAND.SPL";
558 reg = <0x00000000 0x000020000>;
559 };
560 partition@1 {
561 label = "NAND.SPL.backup1";
562 reg = <0x00020000 0x00020000>;
563 };
564 partition@2 {
565 label = "NAND.SPL.backup2";
566 reg = <0x00040000 0x00020000>;
567 };
568 partition@3 {
569 label = "NAND.SPL.backup3";
570 reg = <0x00060000 0x00020000>;
571 };
572 partition@4 {
573 label = "NAND.u-boot-spl-os";
574 reg = <0x00080000 0x00040000>;
575 };
576 partition@5 {
577 label = "NAND.u-boot";
578 reg = <0x000c0000 0x00100000>;
579 };
580 partition@6 {
581 label = "NAND.u-boot-env";
582 reg = <0x001c0000 0x00020000>;
583 };
584 partition@7 {
f0e9fab3 585 label = "NAND.u-boot-env.backup1";
ff66a3c8
MS		 586 reg = <0x001e0000 0x00020000>;
587 };
588 partition@8 {
589 label = "NAND.kernel";
590 reg = <0x00200000 0x00800000>;
591 };
592 partition@9 {
593 label = "NAND.file-system";
594 reg = <0x00a00000 0x0f600000>;
595 };
596 };
597};
ae28ea88
RQ		 598
599&usb2_phy1 {
600 phy-supply = <&ldousb_reg>;
601};
602
603&usb2_phy2 {
604 phy-supply = <&ldousb_reg>;
605};
c7cc9ba1
LV		 606
607&gpio7 {
608 ti,no-reset-on-init;
609 ti,no-idle-on-init;
610};
8d039290
M		 611
612&mac {
613 status = "okay";
614 pinctrl-names = "default", "sleep";
615 pinctrl-0 = <&cpsw_default>;
616 pinctrl-1 = <&cpsw_sleep>;
617 dual_emac;
618};
619
620&cpsw_emac0 {
621 phy_id = <&davinci_mdio>, <2>;
622 phy-mode = "rgmii";
623 dual_emac_res_vlan = <1>;
624};
625
626&cpsw_emac1 {
627 phy_id = <&davinci_mdio>, <3>;
628 phy-mode = "rgmii";
629 dual_emac_res_vlan = <2>;
630};
631
632&davinci_mdio {
633 pinctrl-names = "default", "sleep";
634 pinctrl-0 = <&davinci_mdio_default>;
635 pinctrl-1 = <&davinci_mdio_sleep>;
636};
Ubuntu Hirsute Linux kernel mirror