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ARM: DRA7/AM43XX: fix header definition for omap44xx_restart
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / dra7-evm.dts
CommitLineData
6e58b8f1
S		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
38b248db 10#include "dra74x.dtsi"
6e58b8f1
S		 11
12/ {
38b248db
RN		 13 model = "TI DRA742";
14 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
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S		 15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x60000000>; /* 1536 MB */
19 };
6cf02dbb
B		 20
21 mmc2_3v3: fixedregulator-mmc2 {
22 compatible = "regulator-fixed";
23 regulator-name = "mmc2_3v3";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 };
6e58b8f1
S		 27};
28
29&dra7_pmx_core {
30 i2c1_pins: pinmux_i2c1_pins {
31 pinctrl-single,pins = <
32 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
33 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
34 >;
35 };
36
37 i2c2_pins: pinmux_i2c2_pins {
38 pinctrl-single,pins = <
39 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
40 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
41 >;
42 };
43
44 i2c3_pins: pinmux_i2c3_pins {
45 pinctrl-single,pins = <
46 0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
47 0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
48 >;
49 };
50
51 mcspi1_pins: pinmux_mcspi1_pins {
52 pinctrl-single,pins = <
53 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */
54 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */
55 0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */
56 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
57 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */
58 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */
59 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
60 >;
61 };
62
63 mcspi2_pins: pinmux_mcspi2_pins {
64 pinctrl-single,pins = <
65 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
66 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
67 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
68 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
69 >;
70 };
71
72 uart1_pins: pinmux_uart1_pins {
73 pinctrl-single,pins = <
74 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
75 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
76 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
77 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
78 >;
79 };
80
81 uart2_pins: pinmux_uart2_pins {
82 pinctrl-single,pins = <
83 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
84 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
85 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
86 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
87 >;
88 };
89
90 uart3_pins: pinmux_uart3_pins {
91 pinctrl-single,pins = <
92 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
93 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
94 >;
95 };
dc2dd5b8
SP		 96
97 qspi1_pins: pinmux_qspi1_pins {
98 pinctrl-single,pins = <
99 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
100 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
101 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
102 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
103 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
104 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
105 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
106 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
107 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
108 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
109 >;
110 };
4b4437cb
RQ		 111
112 usb1_pins: pinmux_usb1_pins {
113 pinctrl-single,pins = <
114 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
115 >;
116 };
117
118 usb2_pins: pinmux_usb2_pins {
119 pinctrl-single,pins = <
120 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
121 >;
122 };
ff66a3c8
MS		 123
124 nand_flash_x16: nand_flash_x16 {
125 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
126 * So NAND flash requires following switch settings:
127 * SW5.9 (GPMC_WPN) = LOW
128 * SW5.1 (NAND_BOOTn) = HIGH */
129 pinctrl-single,pins = <
130 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
131 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
132 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
133 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
134 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
135 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
136 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
137 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
138 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
139 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
140 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
141 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
142 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
143 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
144 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
145 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
146 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
147 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
148 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
149 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
150 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
151 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
152 >;
153 };
6e58b8f1
S		 154};
155
156&i2c1 {
157 status = "okay";
158 pinctrl-names = "default";
159 pinctrl-0 = <&i2c1_pins>;
160 clock-frequency = <400000>;
c56a831c
K		 161
162 tps659038: tps659038@58 {
163 compatible = "ti,tps659038";
164 reg = <0x58>;
165
166 tps659038_pmic {
167 compatible = "ti,tps659038-pmic";
168
169 regulators {
170 smps123_reg: smps123 {
171 /* VDD_MPU */
172 regulator-name = "smps123";
173 regulator-min-microvolt = < 850000>;
174 regulator-max-microvolt = <1250000>;
175 regulator-always-on;
176 regulator-boot-on;
177 };
178
179 smps45_reg: smps45 {
180 /* VDD_DSPEVE */
181 regulator-name = "smps45";
182 regulator-min-microvolt = < 850000>;
183 regulator-max-microvolt = <1150000>;
184 regulator-boot-on;
185 };
186
187 smps6_reg: smps6 {
188 /* VDD_GPU - over VDD_SMPS6 */
189 regulator-name = "smps6";
190 regulator-min-microvolt = <850000>;
191 regulator-max-microvolt = <12500000>;
192 regulator-boot-on;
193 };
194
195 smps7_reg: smps7 {
196 /* CORE_VDD */
197 regulator-name = "smps7";
198 regulator-min-microvolt = <850000>;
199 regulator-max-microvolt = <1030000>;
200 regulator-always-on;
201 regulator-boot-on;
202 };
203
204 smps8_reg: smps8 {
205 /* VDD_IVAHD */
206 regulator-name = "smps8";
207 regulator-min-microvolt = < 850000>;
208 regulator-max-microvolt = <1250000>;
209 regulator-boot-on;
210 };
211
212 smps9_reg: smps9 {
213 /* VDDS1V8 */
214 regulator-name = "smps9";
215 regulator-min-microvolt = <1800000>;
216 regulator-max-microvolt = <1800000>;
217 regulator-always-on;
218 regulator-boot-on;
219 };
220
221 ldo1_reg: ldo1 {
222 /* LDO1_OUT --> SDIO */
223 regulator-name = "ldo1";
224 regulator-min-microvolt = <1800000>;
225 regulator-max-microvolt = <3300000>;
226 regulator-boot-on;
227 };
228
229 ldo2_reg: ldo2 {
230 /* VDD_RTCIO */
231 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
232 regulator-name = "ldo2";
233 regulator-min-microvolt = <3300000>;
234 regulator-max-microvolt = <3300000>;
235 regulator-boot-on;
236 };
237
238 ldo3_reg: ldo3 {
239 /* VDDA_1V8_PHY */
240 regulator-name = "ldo3";
241 regulator-min-microvolt = <1800000>;
242 regulator-max-microvolt = <1800000>;
243 regulator-boot-on;
244 };
245
246 ldo9_reg: ldo9 {
247 /* VDD_RTC */
248 regulator-name = "ldo9";
249 regulator-min-microvolt = <1050000>;
250 regulator-max-microvolt = <1050000>;
251 regulator-boot-on;
252 };
253
254 ldoln_reg: ldoln {
255 /* VDDA_1V8_PLL */
256 regulator-name = "ldoln";
257 regulator-min-microvolt = <1800000>;
258 regulator-max-microvolt = <1800000>;
259 regulator-always-on;
260 regulator-boot-on;
261 };
262
263 ldousb_reg: ldousb {
264 /* VDDA_3V_USB: VDDA_USBHS33 */
265 regulator-name = "ldousb";
266 regulator-min-microvolt = <3300000>;
267 regulator-max-microvolt = <3300000>;
268 regulator-boot-on;
269 };
270 };
271 };
272 };
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S		 273};
274
275&i2c2 {
276 status = "okay";
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c2_pins>;
279 clock-frequency = <400000>;
280};
281
282&i2c3 {
283 status = "okay";
284 pinctrl-names = "default";
285 pinctrl-0 = <&i2c3_pins>;
286 clock-frequency = <3400000>;
287};
288
289&mcspi1 {
290 status = "okay";
291 pinctrl-names = "default";
292 pinctrl-0 = <&mcspi1_pins>;
293};
294
295&mcspi2 {
296 status = "okay";
297 pinctrl-names = "default";
298 pinctrl-0 = <&mcspi2_pins>;
299};
300
301&uart1 {
302 status = "okay";
303 pinctrl-names = "default";
304 pinctrl-0 = <&uart1_pins>;
305};
306
307&uart2 {
308 status = "okay";
309 pinctrl-names = "default";
310 pinctrl-0 = <&uart2_pins>;
311};
312
313&uart3 {
314 status = "okay";
315 pinctrl-names = "default";
316 pinctrl-0 = <&uart3_pins>;
317};
bf1788df
B		 318
319&mmc1 {
320 status = "okay";
321 vmmc-supply = <&ldo1_reg>;
322 bus-width = <4>;
323};
6cf02dbb
B		 324
325&mmc2 {
326 status = "okay";
327 vmmc-supply = <&mmc2_3v3>;
328 bus-width = <8>;
329};
22f1e7ef
K		 330
331&cpu0 {
332 cpu0-supply = <&smps123_reg>;
333};
dc2dd5b8
SP		 334
335&qspi {
336 status = "okay";
337 pinctrl-names = "default";
338 pinctrl-0 = <&qspi1_pins>;
339
340 spi-max-frequency = <48000000>;
341 m25p80@0 {
342 compatible = "s25fl256s1";
343 spi-max-frequency = <48000000>;
344 reg = <0>;
345 spi-tx-bus-width = <1>;
346 spi-rx-bus-width = <4>;
347 spi-cpol;
348 spi-cpha;
349 #address-cells = <1>;
350 #size-cells = <1>;
351
352 /* MTD partition table.
353 * The ROM checks the first four physical blocks
354 * for a valid file to boot and the flash here is
355 * 64KiB block size.
356 */
357 partition@0 {
358 label = "QSPI.SPL";
359 reg = <0x00000000 0x000010000>;
360 };
361 partition@1 {
362 label = "QSPI.SPL.backup1";
363 reg = <0x00010000 0x00010000>;
364 };
365 partition@2 {
366 label = "QSPI.SPL.backup2";
367 reg = <0x00020000 0x00010000>;
368 };
369 partition@3 {
370 label = "QSPI.SPL.backup3";
371 reg = <0x00030000 0x00010000>;
372 };
373 partition@4 {
374 label = "QSPI.u-boot";
375 reg = <0x00040000 0x00100000>;
376 };
377 partition@5 {
378 label = "QSPI.u-boot-spl-os";
379 reg = <0x00140000 0x00010000>;
380 };
381 partition@6 {
382 label = "QSPI.u-boot-env";
383 reg = <0x00150000 0x00010000>;
384 };
385 partition@7 {
386 label = "QSPI.u-boot-env.backup1";
387 reg = <0x00160000 0x0010000>;
388 };
389 partition@8 {
390 label = "QSPI.kernel";
391 reg = <0x00170000 0x0800000>;
392 };
393 partition@9 {
394 label = "QSPI.file-system";
395 reg = <0x00970000 0x01690000>;
396 };
397 };
398};
4b4437cb
RQ		 399
400&usb1 {
401 dr_mode = "peripheral";
402 pinctrl-names = "default";
403 pinctrl-0 = <&usb1_pins>;
404};
405
406&usb2 {
407 dr_mode = "host";
408 pinctrl-names = "default";
409 pinctrl-0 = <&usb2_pins>;
410};
ff66a3c8
MS		 411
412&elm {
413 status = "okay";
414};
415
416&gpmc {
417 status = "okay";
418 pinctrl-names = "default";
419 pinctrl-0 = <&nand_flash_x16>;
420 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
421 nand@0,0 {
422 reg = <0 0 4>; /* device IO registers */
423 ti,nand-ecc-opt = "bch8";
424 ti,elm-id = <&elm>;
425 nand-bus-width = <16>;
426 gpmc,device-width = <2>;
427 gpmc,sync-clk-ps = <0>;
428 gpmc,cs-on-ns = <0>;
429 gpmc,cs-rd-off-ns = <40>;
430 gpmc,cs-wr-off-ns = <40>;
431 gpmc,adv-on-ns = <0>;
432 gpmc,adv-rd-off-ns = <30>;
433 gpmc,adv-wr-off-ns = <30>;
434 gpmc,we-on-ns = <5>;
435 gpmc,we-off-ns = <25>;
436 gpmc,oe-on-ns = <2>;
437 gpmc,oe-off-ns = <20>;
438 gpmc,access-ns = <20>;
439 gpmc,wr-access-ns = <40>;
440 gpmc,rd-cycle-ns = <40>;
441 gpmc,wr-cycle-ns = <40>;
442 gpmc,wait-pin = <0>;
443 gpmc,wait-on-read;
444 gpmc,wait-on-write;
445 gpmc,bus-turnaround-ns = <0>;
446 gpmc,cycle2cycle-delay-ns = <0>;
447 gpmc,clk-activation-ns = <0>;
448 gpmc,wait-monitoring-ns = <0>;
449 gpmc,wr-data-mux-bus-ns = <0>;
450 /* MTD partition table */
451 /* All SPL-* partitions are sized to minimal length
452 * which can be independently programmable. For
453 * NAND flash this is equal to size of erase-block */
454 #address-cells = <1>;
455 #size-cells = <1>;
456 partition@0 {
457 label = "NAND.SPL";
458 reg = <0x00000000 0x000020000>;
459 };
460 partition@1 {
461 label = "NAND.SPL.backup1";
462 reg = <0x00020000 0x00020000>;
463 };
464 partition@2 {
465 label = "NAND.SPL.backup2";
466 reg = <0x00040000 0x00020000>;
467 };
468 partition@3 {
469 label = "NAND.SPL.backup3";
470 reg = <0x00060000 0x00020000>;
471 };
472 partition@4 {
473 label = "NAND.u-boot-spl-os";
474 reg = <0x00080000 0x00040000>;
475 };
476 partition@5 {
477 label = "NAND.u-boot";
478 reg = <0x000c0000 0x00100000>;
479 };
480 partition@6 {
481 label = "NAND.u-boot-env";
482 reg = <0x001c0000 0x00020000>;
483 };
484 partition@7 {
485 label = "NAND.u-boot-env";
486 reg = <0x001e0000 0x00020000>;
487 };
488 partition@8 {
489 label = "NAND.kernel";
490 reg = <0x00200000 0x00800000>;
491 };
492 partition@9 {
493 label = "NAND.file-system";
494 reg = <0x00a00000 0x0f600000>;
495 };
496 };
497};
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