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Merge remote-tracking branches 'regmap/fix/irq', 'regmap/fix/rbtree' and 'regmap...
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / dra7-evm.dts
CommitLineData
6e58b8f1
S		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
38b248db 10#include "dra74x.dtsi"
c7cc9ba1 11#include <dt-bindings/gpio/gpio.h>
6e58b8f1
S		 12
13/ {
38b248db
RN		 14 model = "TI DRA742";
15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
6e58b8f1
S		 16
17 memory {
18 device_type = "memory";
19 reg = <0x80000000 0x60000000>; /* 1536 MB */
20 };
6cf02dbb
B		 21
22 mmc2_3v3: fixedregulator-mmc2 {
23 compatible = "regulator-fixed";
24 regulator-name = "mmc2_3v3";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 };
c7cc9ba1 28
87517d26
RQ		 29 extcon_usb1: extcon_usb1 {
30 compatible = "linux,extcon-usb-gpio";
31 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
32 };
33
34 extcon_usb2: extcon_usb2 {
35 compatible = "linux,extcon-usb-gpio";
36 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
37 };
38
c7cc9ba1
LV		 39 vtt_fixed: fixedregulator-vtt {
40 compatible = "regulator-fixed";
41 regulator-name = "vtt_fixed";
42 regulator-min-microvolt = <1350000>;
43 regulator-max-microvolt = <1350000>;
44 regulator-always-on;
45 regulator-boot-on;
46 enable-active-high;
47 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
48 };
6e58b8f1
S		 49};
50
51&dra7_pmx_core {
c7cc9ba1
LV		 52 pinctrl-names = "default";
53 pinctrl-0 = <&vtt_pin>;
54
55 vtt_pin: pinmux_vtt_pin {
56 pinctrl-single,pins = <
57 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
58 >;
59 };
60
6e58b8f1
S		 61 i2c1_pins: pinmux_i2c1_pins {
62 pinctrl-single,pins = <
63 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
64 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
65 >;
66 };
67
68 i2c2_pins: pinmux_i2c2_pins {
69 pinctrl-single,pins = <
70 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
71 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
72 >;
73 };
74
75 i2c3_pins: pinmux_i2c3_pins {
76 pinctrl-single,pins = <
544d63d0
RQ		 77 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
78 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
6e58b8f1
S		 79 >;
80 };
81
82 mcspi1_pins: pinmux_mcspi1_pins {
83 pinctrl-single,pins = <
68e4d9e5
NM		 84 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
85 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
86 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
87 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
68e4d9e5
NM		 88 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
89 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
6e58b8f1
S		 90 >;
91 };
92
93 mcspi2_pins: pinmux_mcspi2_pins {
94 pinctrl-single,pins = <
95 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
96 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
97 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
98 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
99 >;
100 };
101
102 uart1_pins: pinmux_uart1_pins {
103 pinctrl-single,pins = <
104 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
105 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
106 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
107 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
108 >;
109 };
110
111 uart2_pins: pinmux_uart2_pins {
112 pinctrl-single,pins = <
113 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
114 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
115 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
116 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
117 >;
118 };
119
120 uart3_pins: pinmux_uart3_pins {
121 pinctrl-single,pins = <
122 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
123 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
124 >;
125 };
dc2dd5b8
SP		 126
127 qspi1_pins: pinmux_qspi1_pins {
128 pinctrl-single,pins = <
129 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
130 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
131 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
132 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
133 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
134 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
135 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
136 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
137 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
138 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
139 >;
140 };
4b4437cb
RQ		 141
142 usb1_pins: pinmux_usb1_pins {
143 pinctrl-single,pins = <
144 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
145 >;
146 };
147
148 usb2_pins: pinmux_usb2_pins {
149 pinctrl-single,pins = <
150 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
151 >;
152 };
ff66a3c8
MS		 153
154 nand_flash_x16: nand_flash_x16 {
155 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
156 * So NAND flash requires following switch settings:
157 * SW5.9 (GPMC_WPN) = LOW
158 * SW5.1 (NAND_BOOTn) = HIGH */
159 pinctrl-single,pins = <
160 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
161 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
162 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
163 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
164 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
165 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
166 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
167 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
168 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
169 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
170 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
171 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
172 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
173 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
174 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
175 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
176 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
177 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
178 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
179 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
180 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
181 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
182 >;
183 };
8d039290
M		 184
185 cpsw_default: cpsw_default {
186 pinctrl-single,pins = <
187 /* Slave 1 */
188 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
189 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
190 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
191 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
192 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
193 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
194 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
195 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
196 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
197 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
198 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
199 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
200
201 /* Slave 2 */
202 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
203 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
204 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
205 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
206 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
207 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
208 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
209 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
210 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
211 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
212 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
213 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
214 >;
215
216 };
217
218 cpsw_sleep: cpsw_sleep {
219 pinctrl-single,pins = <
220 /* Slave 1 */
221 0x250 (MUX_MODE15)
222 0x254 (MUX_MODE15)
223 0x258 (MUX_MODE15)
224 0x25c (MUX_MODE15)
225 0x260 (MUX_MODE15)
226 0x264 (MUX_MODE15)
227 0x268 (MUX_MODE15)
228 0x26c (MUX_MODE15)
229 0x270 (MUX_MODE15)
230 0x274 (MUX_MODE15)
231 0x278 (MUX_MODE15)
232 0x27c (MUX_MODE15)
233
234 /* Slave 2 */
235 0x198 (MUX_MODE15)
236 0x19c (MUX_MODE15)
237 0x1a0 (MUX_MODE15)
238 0x1a4 (MUX_MODE15)
239 0x1a8 (MUX_MODE15)
240 0x1ac (MUX_MODE15)
241 0x1b0 (MUX_MODE15)
242 0x1b4 (MUX_MODE15)
243 0x1b8 (MUX_MODE15)
244 0x1bc (MUX_MODE15)
245 0x1c0 (MUX_MODE15)
246 0x1c4 (MUX_MODE15)
247 >;
248 };
249
250 davinci_mdio_default: davinci_mdio_default {
251 pinctrl-single,pins = <
252 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
253 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
254 >;
255 };
256
257 davinci_mdio_sleep: davinci_mdio_sleep {
258 pinctrl-single,pins = <
259 0x23c (MUX_MODE15)
260 0x240 (MUX_MODE15)
261 >;
262 };
263
b41502e0
RQ		 264 dcan1_pins_default: dcan1_pins_default {
265 pinctrl-single,pins = <
266 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
267 0x3d4 (MUX_MODE15) /* dcan1_rx.off */
268 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
269 >;
270 };
271
272 dcan1_pins_sleep: dcan1_pins_sleep {
273 pinctrl-single,pins = <
274 0x3d0 (MUX_MODE15) /* dcan1_tx.off */
275 0x3d4 (MUX_MODE15) /* dcan1_rx.off */
276 0x418 (MUX_MODE15) /* wakeup0.off */
277 >;
278 };
6e58b8f1
S		 279};
280
281&i2c1 {
282 status = "okay";
283 pinctrl-names = "default";
284 pinctrl-0 = <&i2c1_pins>;
285 clock-frequency = <400000>;
c56a831c
K		 286
287 tps659038: tps659038@58 {
288 compatible = "ti,tps659038";
289 reg = <0x58>;
290
291 tps659038_pmic {
292 compatible = "ti,tps659038-pmic";
293
294 regulators {
295 smps123_reg: smps123 {
296 /* VDD_MPU */
297 regulator-name = "smps123";
298 regulator-min-microvolt = < 850000>;
299 regulator-max-microvolt = <1250000>;
300 regulator-always-on;
301 regulator-boot-on;
302 };
303
304 smps45_reg: smps45 {
305 /* VDD_DSPEVE */
306 regulator-name = "smps45";
307 regulator-min-microvolt = < 850000>;
308 regulator-max-microvolt = <1150000>;
395b23ca 309 regulator-always-on;
c56a831c
K		 310 regulator-boot-on;
311 };
312
313 smps6_reg: smps6 {
314 /* VDD_GPU - over VDD_SMPS6 */
315 regulator-name = "smps6";
316 regulator-min-microvolt = <850000>;
d114e854 317 regulator-max-microvolt = <1250000>;
395b23ca 318 regulator-always-on;
c56a831c
K		 319 regulator-boot-on;
320 };
321
322 smps7_reg: smps7 {
323 /* CORE_VDD */
324 regulator-name = "smps7";
325 regulator-min-microvolt = <850000>;
70fcaf92 326 regulator-max-microvolt = <1060000>;
c56a831c
K		 327 regulator-always-on;
328 regulator-boot-on;
329 };
330
331 smps8_reg: smps8 {
332 /* VDD_IVAHD */
333 regulator-name = "smps8";
334 regulator-min-microvolt = < 850000>;
335 regulator-max-microvolt = <1250000>;
395b23ca 336 regulator-always-on;
c56a831c
K		 337 regulator-boot-on;
338 };
339
340 smps9_reg: smps9 {
341 /* VDDS1V8 */
342 regulator-name = "smps9";
343 regulator-min-microvolt = <1800000>;
344 regulator-max-microvolt = <1800000>;
345 regulator-always-on;
346 regulator-boot-on;
347 };
348
349 ldo1_reg: ldo1 {
350 /* LDO1_OUT --> SDIO */
351 regulator-name = "ldo1";
352 regulator-min-microvolt = <1800000>;
353 regulator-max-microvolt = <3300000>;
354 regulator-boot-on;
355 };
356
357 ldo2_reg: ldo2 {
358 /* VDD_RTCIO */
359 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
360 regulator-name = "ldo2";
361 regulator-min-microvolt = <3300000>;
362 regulator-max-microvolt = <3300000>;
395b23ca 363 regulator-always-on;
c56a831c
K		 364 regulator-boot-on;
365 };
366
367 ldo3_reg: ldo3 {
368 /* VDDA_1V8_PHY */
369 regulator-name = "ldo3";
370 regulator-min-microvolt = <1800000>;
371 regulator-max-microvolt = <1800000>;
e120fb45 372 regulator-always-on;
c56a831c
K		 373 regulator-boot-on;
374 };
375
376 ldo9_reg: ldo9 {
377 /* VDD_RTC */
378 regulator-name = "ldo9";
379 regulator-min-microvolt = <1050000>;
380 regulator-max-microvolt = <1050000>;
395b23ca 381 regulator-always-on;
c56a831c
K		 382 regulator-boot-on;
383 };
384
385 ldoln_reg: ldoln {
386 /* VDDA_1V8_PLL */
387 regulator-name = "ldoln";
388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>;
390 regulator-always-on;
391 regulator-boot-on;
392 };
393
394 ldousb_reg: ldousb {
395 /* VDDA_3V_USB: VDDA_USBHS33 */
396 regulator-name = "ldousb";
397 regulator-min-microvolt = <3300000>;
398 regulator-max-microvolt = <3300000>;
399 regulator-boot-on;
400 };
401 };
402 };
403 };
87517d26
RQ		 404
405 pcf_gpio_21: gpio@21 {
406 compatible = "ti,pcf8575";
407 reg = <0x21>;
408 lines-initial-states = <0x1408>;
409 gpio-controller;
410 #gpio-cells = <2>;
411 interrupt-parent = <&gpio6>;
412 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
413 interrupt-controller;
414 #interrupt-cells = <2>;
415 };
416
6e58b8f1
S		 417};
418
419&i2c2 {
420 status = "okay";
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c2_pins>;
423 clock-frequency = <400000>;
424};
425
426&i2c3 {
427 status = "okay";
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2c3_pins>;
544d63d0 430 clock-frequency = <400000>;
6e58b8f1
S		 431};
432
433&mcspi1 {
434 status = "okay";
435 pinctrl-names = "default";
436 pinctrl-0 = <&mcspi1_pins>;
437};
438
439&mcspi2 {
440 status = "okay";
441 pinctrl-names = "default";
442 pinctrl-0 = <&mcspi2_pins>;
443};
444
445&uart1 {
446 status = "okay";
447 pinctrl-names = "default";
448 pinctrl-0 = <&uart1_pins>;
66b04369
NM		 449 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
450 <&dra7_pmx_core 0x3e0>;
6e58b8f1
S		 451};
452
453&uart2 {
454 status = "okay";
455 pinctrl-names = "default";
456 pinctrl-0 = <&uart2_pins>;
457};
458
459&uart3 {
460 status = "okay";
461 pinctrl-names = "default";
462 pinctrl-0 = <&uart3_pins>;
463};
bf1788df
B		 464
465&mmc1 {
466 status = "okay";
467 vmmc-supply = <&ldo1_reg>;
468 bus-width = <4>;
469};
6cf02dbb
B		 470
471&mmc2 {
472 status = "okay";
473 vmmc-supply = <&mmc2_3v3>;
474 bus-width = <8>;
475};
22f1e7ef
K		 476
477&cpu0 {
478 cpu0-supply = <&smps123_reg>;
479};
dc2dd5b8
SP		 480
481&qspi {
482 status = "okay";
483 pinctrl-names = "default";
484 pinctrl-0 = <&qspi1_pins>;
485
486 spi-max-frequency = <48000000>;
487 m25p80@0 {
488 compatible = "s25fl256s1";
489 spi-max-frequency = <48000000>;
490 reg = <0>;
491 spi-tx-bus-width = <1>;
492 spi-rx-bus-width = <4>;
493 spi-cpol;
494 spi-cpha;
495 #address-cells = <1>;
496 #size-cells = <1>;
497
498 /* MTD partition table.
499 * The ROM checks the first four physical blocks
500 * for a valid file to boot and the flash here is
501 * 64KiB block size.
502 */
503 partition@0 {
504 label = "QSPI.SPL";
505 reg = <0x00000000 0x000010000>;
506 };
507 partition@1 {
508 label = "QSPI.SPL.backup1";
509 reg = <0x00010000 0x00010000>;
510 };
511 partition@2 {
512 label = "QSPI.SPL.backup2";
513 reg = <0x00020000 0x00010000>;
514 };
515 partition@3 {
516 label = "QSPI.SPL.backup3";
517 reg = <0x00030000 0x00010000>;
518 };
519 partition@4 {
520 label = "QSPI.u-boot";
521 reg = <0x00040000 0x00100000>;
522 };
523 partition@5 {
524 label = "QSPI.u-boot-spl-os";
69d2626f 525 reg = <0x00140000 0x00080000>;
dc2dd5b8
SP		 526 };
527 partition@6 {
528 label = "QSPI.u-boot-env";
69d2626f 529 reg = <0x001c0000 0x00010000>;
dc2dd5b8
SP		 530 };
531 partition@7 {
532 label = "QSPI.u-boot-env.backup1";
69d2626f 533 reg = <0x001d0000 0x0010000>;
dc2dd5b8
SP		 534 };
535 partition@8 {
536 label = "QSPI.kernel";
69d2626f 537 reg = <0x001e0000 0x0800000>;
dc2dd5b8
SP		 538 };
539 partition@9 {
540 label = "QSPI.file-system";
69d2626f 541 reg = <0x009e0000 0x01620000>;
dc2dd5b8
SP		 542 };
543 };
544};
4b4437cb
RQ		 545
546&usb1 {
547 dr_mode = "peripheral";
548 pinctrl-names = "default";
549 pinctrl-0 = <&usb1_pins>;
550};
551
552&usb2 {
553 dr_mode = "host";
554 pinctrl-names = "default";
555 pinctrl-0 = <&usb2_pins>;
556};
ff66a3c8
MS		 557
558&elm {
559 status = "okay";
560};
561
562&gpmc {
563 status = "okay";
564 pinctrl-names = "default";
565 pinctrl-0 = <&nand_flash_x16>;
566 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
567 nand@0,0 {
568 reg = <0 0 4>; /* device IO registers */
569 ti,nand-ecc-opt = "bch8";
570 ti,elm-id = <&elm>;
571 nand-bus-width = <16>;
572 gpmc,device-width = <2>;
573 gpmc,sync-clk-ps = <0>;
574 gpmc,cs-on-ns = <0>;
5990047c
RQ		 575 gpmc,cs-rd-off-ns = <80>;
576 gpmc,cs-wr-off-ns = <80>;
ff66a3c8 577 gpmc,adv-on-ns = <0>;
5990047c
RQ		 578 gpmc,adv-rd-off-ns = <60>;
579 gpmc,adv-wr-off-ns = <60>;
580 gpmc,we-on-ns = <10>;
581 gpmc,we-off-ns = <50>;
582 gpmc,oe-on-ns = <4>;
583 gpmc,oe-off-ns = <40>;
584 gpmc,access-ns = <40>;
585 gpmc,wr-access-ns = <80>;
586 gpmc,rd-cycle-ns = <80>;
587 gpmc,wr-cycle-ns = <80>;
ff66a3c8
MS		 588 gpmc,bus-turnaround-ns = <0>;
589 gpmc,cycle2cycle-delay-ns = <0>;
590 gpmc,clk-activation-ns = <0>;
591 gpmc,wait-monitoring-ns = <0>;
592 gpmc,wr-data-mux-bus-ns = <0>;
593 /* MTD partition table */
594 /* All SPL-* partitions are sized to minimal length
595 * which can be independently programmable. For
596 * NAND flash this is equal to size of erase-block */
597 #address-cells = <1>;
598 #size-cells = <1>;
599 partition@0 {
600 label = "NAND.SPL";
601 reg = <0x00000000 0x000020000>;
602 };
603 partition@1 {
604 label = "NAND.SPL.backup1";
605 reg = <0x00020000 0x00020000>;
606 };
607 partition@2 {
608 label = "NAND.SPL.backup2";
609 reg = <0x00040000 0x00020000>;
610 };
611 partition@3 {
612 label = "NAND.SPL.backup3";
613 reg = <0x00060000 0x00020000>;
614 };
615 partition@4 {
616 label = "NAND.u-boot-spl-os";
617 reg = <0x00080000 0x00040000>;
618 };
619 partition@5 {
620 label = "NAND.u-boot";
621 reg = <0x000c0000 0x00100000>;
622 };
623 partition@6 {
624 label = "NAND.u-boot-env";
625 reg = <0x001c0000 0x00020000>;
626 };
627 partition@7 {
f0e9fab3 628 label = "NAND.u-boot-env.backup1";
ff66a3c8
MS		 629 reg = <0x001e0000 0x00020000>;
630 };
631 partition@8 {
632 label = "NAND.kernel";
633 reg = <0x00200000 0x00800000>;
634 };
635 partition@9 {
636 label = "NAND.file-system";
637 reg = <0x00a00000 0x0f600000>;
638 };
639 };
640};
ae28ea88
RQ		 641
642&usb2_phy1 {
643 phy-supply = <&ldousb_reg>;
644};
645
646&usb2_phy2 {
647 phy-supply = <&ldousb_reg>;
648};
c7cc9ba1
LV		 649
650&gpio7 {
651 ti,no-reset-on-init;
652 ti,no-idle-on-init;
653};
8d039290
M		 654
655&mac {
656 status = "okay";
657 pinctrl-names = "default", "sleep";
658 pinctrl-0 = <&cpsw_default>;
659 pinctrl-1 = <&cpsw_sleep>;
660 dual_emac;
661};
662
663&cpsw_emac0 {
664 phy_id = <&davinci_mdio>, <2>;
665 phy-mode = "rgmii";
666 dual_emac_res_vlan = <1>;
667};
668
669&cpsw_emac1 {
670 phy_id = <&davinci_mdio>, <3>;
671 phy-mode = "rgmii";
672 dual_emac_res_vlan = <2>;
673};
674
675&davinci_mdio {
676 pinctrl-names = "default", "sleep";
677 pinctrl-0 = <&davinci_mdio_default>;
678 pinctrl-1 = <&davinci_mdio_sleep>;
679};
b41502e0
RQ		 680
681&dcan1 {
682 status = "ok";
683 pinctrl-names = "default", "sleep";
684 pinctrl-0 = <&dcan1_pins_default>;
685 pinctrl-1 = <&dcan1_pins_sleep>;
686};
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