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ARM: dts: DRA7: Add pcie1 dt node for EP mode
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / dra7-evm.dts
CommitLineData
6e58b8f1
S		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
38b248db 10#include "dra74x.dtsi"
c7cc9ba1 11#include <dt-bindings/gpio/gpio.h>
a9347bfa 12#include <dt-bindings/clk/ti-dra7-atl.h>
863987af 13#include <dt-bindings/input/input.h>
6e58b8f1
S		 14
15/ {
38b248db
RN		 16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
6e58b8f1 18
5c4d9f0d 19 memory@0 {
6e58b8f1 20 device_type = "memory";
dae320ec 21 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
6e58b8f1 22 };
6cf02dbb 23
220fbc13
LV		 24 chosen {
25 stdout-path = &uart1;
26 };
27
b5ca62a5
RK		 28 evm_1v8_sw: fixedregulator-evm_1v8 {
29 compatible = "regulator-fixed";
30 regulator-name = "evm_1v8";
31 vin-supply = <&smps9_reg>;
32 regulator-min-microvolt = <1800000>;
33 regulator-max-microvolt = <1800000>;
34 };
35
4b935215
B		 36 evm_3v3_sd: fixedregulator-sd {
37 compatible = "regulator-fixed";
38 regulator-name = "evm_3v3_sd";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 enable-active-high;
42 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
43 };
44
27f39e5f 45 evm_3v3_sw: fixedregulator-evm_3v3_sw {
6cf02dbb 46 compatible = "regulator-fixed";
27f39e5f 47 regulator-name = "evm_3v3_sw";
8695add6 48 vin-supply = <&sysen1>;
6cf02dbb
B		 49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 };
c7cc9ba1 52
d6818223
PU		 53 aic_dvdd: fixedregulator-aic_dvdd {
54 /* TPS77018DBVT */
55 compatible = "regulator-fixed";
56 regulator-name = "aic_dvdd";
57 vin-supply = <&evm_3v3_sw>;
58 regulator-min-microvolt = <1800000>;
59 regulator-max-microvolt = <1800000>;
60 };
61
87517d26
RQ		 62 extcon_usb1: extcon_usb1 {
63 compatible = "linux,extcon-usb-gpio";
64 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
65 };
66
67 extcon_usb2: extcon_usb2 {
68 compatible = "linux,extcon-usb-gpio";
69 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
70 };
71
c7cc9ba1
LV		 72 vtt_fixed: fixedregulator-vtt {
73 compatible = "regulator-fixed";
74 regulator-name = "vtt_fixed";
75 regulator-min-microvolt = <1350000>;
76 regulator-max-microvolt = <1350000>;
77 regulator-always-on;
78 regulator-boot-on;
79 enable-active-high;
8695add6 80 vin-supply = <&sysen2>;
c7cc9ba1
LV		 81 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
82 };
a9347bfa 83
4e8603ef 84 sound0: sound0 {
a9347bfa
PU		 85 compatible = "simple-audio-card";
86 simple-audio-card,name = "DRA7xx-EVM";
87 simple-audio-card,widgets =
88 "Headphone", "Headphone Jack",
89 "Line", "Line Out",
90 "Microphone", "Mic Jack",
91 "Line", "Line In";
92 simple-audio-card,routing =
93 "Headphone Jack", "HPLOUT",
94 "Headphone Jack", "HPROUT",
95 "Line Out", "LLOUT",
96 "Line Out", "RLOUT",
97 "MIC3L", "Mic Jack",
98 "MIC3R", "Mic Jack",
99 "Mic Jack", "Mic Bias",
100 "LINE1L", "Line In",
101 "LINE1R", "Line In";
102 simple-audio-card,format = "dsp_b";
103 simple-audio-card,bitclock-master = <&sound0_master>;
104 simple-audio-card,frame-master = <&sound0_master>;
105 simple-audio-card,bitclock-inversion;
106
107 sound0_master: simple-audio-card,cpu {
108 sound-dai = <&mcasp3>;
109 system-clock-frequency = <5644800>;
110 };
111
112 simple-audio-card,codec {
113 sound-dai = <&tlv320aic3106>;
114 clocks = <&atl_clkin2_ck>;
115 };
116 };
a96e8808
GS		 117
118 leds {
119 compatible = "gpio-leds";
08ef9806 120 led0 {
a96e8808
GS		 121 label = "dra7:usr1";
122 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
123 default-state = "off";
124 };
125
08ef9806 126 led1 {
a96e8808
GS		 127 label = "dra7:usr2";
128 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
129 default-state = "off";
130 };
131
08ef9806 132 led2 {
a96e8808
GS		 133 label = "dra7:usr3";
134 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
135 default-state = "off";
136 };
137
08ef9806 138 led3 {
a96e8808
GS		 139 label = "dra7:usr4";
140 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
141 default-state = "off";
142 };
143 };
863987af
GS		 144
145 gpio_keys {
146 compatible = "gpio-keys";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 autorepeat;
150
151 USER1 {
152 label = "btnUser1";
153 linux,code = <BTN_0>;
154 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
155 };
156
157 USER2 {
158 label = "btnUser2";
159 linux,code = <BTN_1>;
160 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
161 };
162 };
6e58b8f1
S		 163};
164
165&dra7_pmx_core {
b41502e0
RQ		 166 dcan1_pins_default: dcan1_pins_default {
167 pinctrl-single,pins = <
c78be3d8
JMC		 168 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
169 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
b41502e0
RQ		 170 >;
171 };
172
173 dcan1_pins_sleep: dcan1_pins_sleep {
174 pinctrl-single,pins = <
c78be3d8
JMC		 175 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
176 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
b41502e0
RQ		 177 >;
178 };
0c8a507f
KVA		 179
180 mmc1_pins_default: mmc1_pins_default {
181 pinctrl-single,pins = <
182 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
183 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
184 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
185 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
186 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
187 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
188 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
189 >;
190 };
191
192 mmc2_pins_default: mmc2_pins_default {
193 pinctrl-single,pins = <
194 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
195 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
196 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
197 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
198 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
199 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
200 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
201 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
202 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
203 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
204 >;
205 };
6e58b8f1
S		 206};
207
208&i2c1 {
209 status = "okay";
6e58b8f1 210 clock-frequency = <400000>;
c56a831c
K		 211
212 tps659038: tps659038@58 {
213 compatible = "ti,tps659038";
214 reg = <0x58>;
7c62de5f
K		 215 ti,palmas-override-powerhold;
216 ti,system-power-controller;
c56a831c
K		 217
218 tps659038_pmic {
219 compatible = "ti,tps659038-pmic";
220
221 regulators {
222 smps123_reg: smps123 {
223 /* VDD_MPU */
224 regulator-name = "smps123";
225 regulator-min-microvolt = < 850000>;
226 regulator-max-microvolt = <1250000>;
227 regulator-always-on;
228 regulator-boot-on;
229 };
230
231 smps45_reg: smps45 {
232 /* VDD_DSPEVE */
233 regulator-name = "smps45";
234 regulator-min-microvolt = < 850000>;
54d03c5d 235 regulator-max-microvolt = <1250000>;
395b23ca 236 regulator-always-on;
c56a831c
K		 237 regulator-boot-on;
238 };
239
240 smps6_reg: smps6 {
241 /* VDD_GPU - over VDD_SMPS6 */
242 regulator-name = "smps6";
243 regulator-min-microvolt = <850000>;
d114e854 244 regulator-max-microvolt = <1250000>;
395b23ca 245 regulator-always-on;
c56a831c
K		 246 regulator-boot-on;
247 };
248
249 smps7_reg: smps7 {
250 /* CORE_VDD */
251 regulator-name = "smps7";
252 regulator-min-microvolt = <850000>;
54d03c5d 253 regulator-max-microvolt = <1150000>;
c56a831c
K		 254 regulator-always-on;
255 regulator-boot-on;
256 };
257
258 smps8_reg: smps8 {
259 /* VDD_IVAHD */
260 regulator-name = "smps8";
261 regulator-min-microvolt = < 850000>;
262 regulator-max-microvolt = <1250000>;
395b23ca 263 regulator-always-on;
c56a831c
K		 264 regulator-boot-on;
265 };
266
267 smps9_reg: smps9 {
268 /* VDDS1V8 */
269 regulator-name = "smps9";
270 regulator-min-microvolt = <1800000>;
271 regulator-max-microvolt = <1800000>;
272 regulator-always-on;
273 regulator-boot-on;
274 };
275
276 ldo1_reg: ldo1 {
277 /* LDO1_OUT --> SDIO */
278 regulator-name = "ldo1";
279 regulator-min-microvolt = <1800000>;
280 regulator-max-microvolt = <3300000>;
9f04ceeb 281 regulator-always-on;
c56a831c
K		 282 regulator-boot-on;
283 };
284
285 ldo2_reg: ldo2 {
286 /* VDD_RTCIO */
287 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
288 regulator-name = "ldo2";
289 regulator-min-microvolt = <3300000>;
290 regulator-max-microvolt = <3300000>;
395b23ca 291 regulator-always-on;
c56a831c
K		 292 regulator-boot-on;
293 };
294
295 ldo3_reg: ldo3 {
296 /* VDDA_1V8_PHY */
297 regulator-name = "ldo3";
298 regulator-min-microvolt = <1800000>;
299 regulator-max-microvolt = <1800000>;
e120fb45 300 regulator-always-on;
c56a831c
K		 301 regulator-boot-on;
302 };
303
304 ldo9_reg: ldo9 {
305 /* VDD_RTC */
306 regulator-name = "ldo9";
307 regulator-min-microvolt = <1050000>;
308 regulator-max-microvolt = <1050000>;
395b23ca 309 regulator-always-on;
c56a831c 310 regulator-boot-on;
fcf58958 311 regulator-allow-bypass;
c56a831c
K		 312 };
313
314 ldoln_reg: ldoln {
315 /* VDDA_1V8_PLL */
316 regulator-name = "ldoln";
317 regulator-min-microvolt = <1800000>;
318 regulator-max-microvolt = <1800000>;
319 regulator-always-on;
320 regulator-boot-on;
321 };
322
323 ldousb_reg: ldousb {
324 /* VDDA_3V_USB: VDDA_USBHS33 */
325 regulator-name = "ldousb";
326 regulator-min-microvolt = <3300000>;
327 regulator-max-microvolt = <3300000>;
328 regulator-boot-on;
329 };
8695add6
NM		 330
331 /* REGEN1 is unused */
332
333 regen2: regen2 {
334 /* Needed for PMIC internal resources */
335 regulator-name = "regen2";
336 regulator-boot-on;
337 regulator-always-on;
338 };
339
340 /* REGEN3 is unused */
341
342 sysen1: sysen1 {
343 /* PMIC_REGEN_3V3 */
344 regulator-name = "sysen1";
345 regulator-boot-on;
346 regulator-always-on;
347 };
348
349 sysen2: sysen2 {
350 /* PMIC_REGEN_DDR */
351 regulator-name = "sysen2";
352 regulator-boot-on;
353 regulator-always-on;
354 };
c56a831c
K		 355 };
356 };
357 };
87517d26 358
4fbdc6ab 359 pcf_lcd: gpio@20 {
86f196f8 360 compatible = "ti,pcf8575", "nxp,pcf8575";
4fbdc6ab
GS		 361 reg = <0x20>;
362 gpio-controller;
363 #gpio-cells = <2>;
364 interrupt-parent = <&gpio6>;
365 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 };
369
87517d26 370 pcf_gpio_21: gpio@21 {
86f196f8 371 compatible = "ti,pcf8575", "nxp,pcf8575";
87517d26
RQ		 372 reg = <0x21>;
373 lines-initial-states = <0x1408>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-parent = <&gpio6>;
377 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
378 interrupt-controller;
379 #interrupt-cells = <2>;
380 };
381
a9347bfa
PU		 382 tlv320aic3106: tlv320aic3106@19 {
383 #sound-dai-cells = <0>;
384 compatible = "ti,tlv320aic3106";
385 reg = <0x19>;
386 adc-settle-ms = <40>;
387 ai3x-micbias-vg = <1>; /* 2.0V */
388 status = "okay";
389
390 /* Regulators */
391 AVDD-supply = <&evm_3v3_sw>;
392 IOVDD-supply = <&evm_3v3_sw>;
393 DRVDD-supply = <&evm_3v3_sw>;
394 DVDD-supply = <&aic_dvdd>;
395 };
6e58b8f1
S		 396};
397
398&i2c2 {
399 status = "okay";
6e58b8f1 400 clock-frequency = <400000>;
c5d294db
PU		 401
402 pcf_hdmi: gpio@26 {
86f196f8 403 compatible = "ti,pcf8575", "nxp,pcf8575";
c5d294db
PU		 404 reg = <0x26>;
405 gpio-controller;
406 #gpio-cells = <2>;
407 p1 {
408 /* vin6_sel_s0: high: VIN6, low: audio */
409 gpio-hog;
410 gpios = <1 GPIO_ACTIVE_HIGH>;
411 output-low;
412 line-name = "vin6_sel_s0";
413 };
414 };
6e58b8f1
S		 415};
416
417&i2c3 {
418 status = "okay";
544d63d0 419 clock-frequency = <400000>;
6e58b8f1
S		 420};
421
422&mcspi1 {
423 status = "okay";
6e58b8f1
S		 424};
425
426&mcspi2 {
427 status = "okay";
6e58b8f1
S		 428};
429
430&uart1 {
431 status = "okay";
783d3186 432 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
66b04369 433 <&dra7_pmx_core 0x3e0>;
6e58b8f1
S		 434};
435
436&uart2 {
437 status = "okay";
6e58b8f1
S		 438};
439
440&uart3 {
441 status = "okay";
6e58b8f1 442};
bf1788df
B		 443
444&mmc1 {
445 status = "okay";
0c8a507f
KVA		 446 pinctrl-names = "default";
447 pinctrl-0 = <&mmc1_pins_default>;
4b935215 448 vmmc-supply = <&evm_3v3_sd>;
45ea75eb 449 vqmmc-supply = <&ldo1_reg>;
bf1788df 450 bus-width = <4>;
f4eaf9e0
NM		 451 /*
452 * SDCD signal is not being used here - using the fact that GPIO mode
453 * is always hardwired.
454 */
267068d8 455 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
bf1788df 456};
6cf02dbb
B		 457
458&mmc2 {
459 status = "okay";
0c8a507f
KVA		 460 pinctrl-names = "default";
461 pinctrl-0 = <&mmc2_pins_default>;
b5ca62a5 462 vmmc-supply = <&evm_1v8_sw>;
6cf02dbb
B		 463 bus-width = <8>;
464};
22f1e7ef
K		 465
466&cpu0 {
467 cpu0-supply = <&smps123_reg>;
468};
dc2dd5b8
SP		 469
470&qspi {
471 status = "okay";
dc2dd5b8 472
a0b83af0 473 spi-max-frequency = <76800000>;
dc2dd5b8
SP		 474 m25p80@0 {
475 compatible = "s25fl256s1";
a0b83af0 476 spi-max-frequency = <76800000>;
dc2dd5b8
SP		 477 reg = <0>;
478 spi-tx-bus-width = <1>;
479 spi-rx-bus-width = <4>;
dc2dd5b8
SP		 480 #address-cells = <1>;
481 #size-cells = <1>;
482
483 /* MTD partition table.
484 * The ROM checks the first four physical blocks
485 * for a valid file to boot and the flash here is
486 * 64KiB block size.
487 */
488 partition@0 {
489 label = "QSPI.SPL";
490 reg = <0x00000000 0x000010000>;
491 };
492 partition@1 {
493 label = "QSPI.SPL.backup1";
494 reg = <0x00010000 0x00010000>;
495 };
496 partition@2 {
497 label = "QSPI.SPL.backup2";
498 reg = <0x00020000 0x00010000>;
499 };
500 partition@3 {
501 label = "QSPI.SPL.backup3";
502 reg = <0x00030000 0x00010000>;
503 };
504 partition@4 {
505 label = "QSPI.u-boot";
506 reg = <0x00040000 0x00100000>;
507 };
508 partition@5 {
509 label = "QSPI.u-boot-spl-os";
69d2626f 510 reg = <0x00140000 0x00080000>;
dc2dd5b8
SP		 511 };
512 partition@6 {
513 label = "QSPI.u-boot-env";
69d2626f 514 reg = <0x001c0000 0x00010000>;
dc2dd5b8
SP		 515 };
516 partition@7 {
517 label = "QSPI.u-boot-env.backup1";
69d2626f 518 reg = <0x001d0000 0x0010000>;
dc2dd5b8
SP		 519 };
520 partition@8 {
521 label = "QSPI.kernel";
69d2626f 522 reg = <0x001e0000 0x0800000>;
dc2dd5b8
SP		 523 };
524 partition@9 {
525 label = "QSPI.file-system";
69d2626f 526 reg = <0x009e0000 0x01620000>;
dc2dd5b8
SP		 527 };
528 };
529};
4b4437cb 530
a7b0aa19
RQ		 531&omap_dwc3_1 {
532 extcon = <&extcon_usb1>;
533};
534
535&omap_dwc3_2 {
536 extcon = <&extcon_usb2>;
537};
538
4b4437cb 539&usb1 {
a6f627e2
RQ		 540 dr_mode = "otg";
541 extcon = <&extcon_usb1>;
4b4437cb
RQ		 542};
543
544&usb2 {
545 dr_mode = "host";
4b4437cb 546};
ff66a3c8
MS		 547
548&elm {
549 status = "okay";
550};
551
552&gpmc {
d888e9d7
SN		 553 /*
554 * For the existing IOdelay configuration via U-Boot we don't
555 * support NAND on dra7-evm. Keep it disabled. Enabling it
556 * requires a different configuration by U-Boot.
557 */
558 status = "disabled";
488f270d 559 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
ff66a3c8 560 nand@0,0 {
488f270d 561 compatible = "ti,omap2-nand";
ff66a3c8 562 reg = <0 0 4>; /* device IO registers */
488f270d
RQ		 563 interrupt-parent = <&gpmc>;
564 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
565 <1 IRQ_TYPE_NONE>; /* termcount */
a23fc155 566 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
a46394be 567 ti,nand-xfer-type = "prefetch-dma";
ff66a3c8
MS		 568 ti,nand-ecc-opt = "bch8";
569 ti,elm-id = <&elm>;
570 nand-bus-width = <16>;
571 gpmc,device-width = <2>;
572 gpmc,sync-clk-ps = <0>;
573 gpmc,cs-on-ns = <0>;
5990047c
RQ		 574 gpmc,cs-rd-off-ns = <80>;
575 gpmc,cs-wr-off-ns = <80>;
ff66a3c8 576 gpmc,adv-on-ns = <0>;
5990047c
RQ		 577 gpmc,adv-rd-off-ns = <60>;
578 gpmc,adv-wr-off-ns = <60>;
579 gpmc,we-on-ns = <10>;
580 gpmc,we-off-ns = <50>;
581 gpmc,oe-on-ns = <4>;
582 gpmc,oe-off-ns = <40>;
583 gpmc,access-ns = <40>;
584 gpmc,wr-access-ns = <80>;
585 gpmc,rd-cycle-ns = <80>;
586 gpmc,wr-cycle-ns = <80>;
ff66a3c8
MS		 587 gpmc,bus-turnaround-ns = <0>;
588 gpmc,cycle2cycle-delay-ns = <0>;
589 gpmc,clk-activation-ns = <0>;
ff66a3c8
MS		 590 gpmc,wr-data-mux-bus-ns = <0>;
591 /* MTD partition table */
592 /* All SPL-* partitions are sized to minimal length
593 * which can be independently programmable. For
594 * NAND flash this is equal to size of erase-block */
595 #address-cells = <1>;
596 #size-cells = <1>;
597 partition@0 {
598 label = "NAND.SPL";
599 reg = <0x00000000 0x000020000>;
600 };
601 partition@1 {
602 label = "NAND.SPL.backup1";
603 reg = <0x00020000 0x00020000>;
604 };
605 partition@2 {
606 label = "NAND.SPL.backup2";
607 reg = <0x00040000 0x00020000>;
608 };
609 partition@3 {
610 label = "NAND.SPL.backup3";
611 reg = <0x00060000 0x00020000>;
612 };
613 partition@4 {
614 label = "NAND.u-boot-spl-os";
615 reg = <0x00080000 0x00040000>;
616 };
617 partition@5 {
618 label = "NAND.u-boot";
619 reg = <0x000c0000 0x00100000>;
620 };
621 partition@6 {
622 label = "NAND.u-boot-env";
623 reg = <0x001c0000 0x00020000>;
624 };
625 partition@7 {
f0e9fab3 626 label = "NAND.u-boot-env.backup1";
ff66a3c8
MS		 627 reg = <0x001e0000 0x00020000>;
628 };
629 partition@8 {
630 label = "NAND.kernel";
631 reg = <0x00200000 0x00800000>;
632 };
633 partition@9 {
634 label = "NAND.file-system";
635 reg = <0x00a00000 0x0f600000>;
636 };
637 };
638};
ae28ea88
RQ		 639
640&usb2_phy1 {
641 phy-supply = <&ldousb_reg>;
642};
643
644&usb2_phy2 {
645 phy-supply = <&ldousb_reg>;
646};
c7cc9ba1
LV		 647
648&gpio7 {
649 ti,no-reset-on-init;
650 ti,no-idle-on-init;
651};
8d039290
M		 652
653&mac {
654 status = "okay";
8d039290
M		 655 dual_emac;
656};
657
658&cpsw_emac0 {
659 phy_id = <&davinci_mdio>, <2>;
660 phy-mode = "rgmii";
661 dual_emac_res_vlan = <1>;
662};
663
664&cpsw_emac1 {
665 phy_id = <&davinci_mdio>, <3>;
666 phy-mode = "rgmii";
667 dual_emac_res_vlan = <2>;
668};
669
b41502e0
RQ		 670&dcan1 {
671 status = "ok";
2acb5c30
RQ		 672 pinctrl-names = "default", "sleep", "active";
673 pinctrl-0 = <&dcan1_pins_sleep>;
b41502e0 674 pinctrl-1 = <&dcan1_pins_sleep>;
2acb5c30 675 pinctrl-2 = <&dcan1_pins_default>;
b41502e0 676};
a9347bfa
PU		 677
678&atl {
a9347bfa
PU		 679 assigned-clocks = <&abe_dpll_sys_clk_mux>,
680 <&atl_gfclk_mux>,
681 <&dpll_abe_ck>,
682 <&dpll_abe_m2x2_ck>,
683 <&atl_clkin2_ck>;
684 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
685 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
686
687 status = "okay";
688
689 atl2 {
690 bws = <DRA7_ATL_WS_MCASP2_FSX>;
691 aws = <DRA7_ATL_WS_MCASP3_FSX>;
692 };
693};
694
695&mcasp3 {
696 #sound-dai-cells = <0>;
a9347bfa
PU		 697
698 assigned-clocks = <&mcasp3_ahclkx_mux>;
699 assigned-clock-parents = <&atl_clkin2_ck>;
700
701 status = "okay";
702
703 op-mode = <0>; /* MCASP_IIS_MODE */
704 tdm-slots = <2>;
705 /* 4 serializer */
706 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
707 1 2 0 0
708 >;
27701fc2
PU		 709 tx-num-evt = <32>;
710 rx-num-evt = <32>;
a9347bfa 711};
2bee8679
SA		 712
713&mailbox5 {
714 status = "okay";
715 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
716 status = "okay";
717 };
718 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
719 status = "okay";
720 };
721};
722
723&mailbox6 {
724 status = "okay";
725 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
726 status = "okay";
727 };
728 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
729 status = "okay";
730 };
731};
d23f3839
KVA		 732
733&pcie1_rc {
734 status = "okay";
735};
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