]>
Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6e58b8f1 S |
2 | /* |
3 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
4 | * | |
6e58b8f1 S |
5 | * Based on "omap4.dtsi" |
6 | */ | |
7 | ||
e14d7e53 TL |
8 | #include <dt-bindings/bus/ti-sysc.h> |
9 | #include <dt-bindings/clock/dra7.h> | |
6e58b8f1 S |
10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
11 | #include <dt-bindings/pinctrl/dra.h> | |
1839533f | 12 | #include <dt-bindings/clock/dra7.h> |
6e58b8f1 | 13 | |
a46631c4 | 14 | #define MAX_SOURCES 400 |
a46631c4 | 15 | |
6e58b8f1 | 16 | / { |
dae320ec LV |
17 | #address-cells = <2>; |
18 | #size-cells = <2>; | |
6e58b8f1 S |
19 | |
20 | compatible = "ti,dra7xx"; | |
783d3186 | 21 | interrupt-parent = <&crossbar_mpu>; |
7f6c857b | 22 | chosen { }; |
6e58b8f1 S |
23 | |
24 | aliases { | |
20b80942 NM |
25 | i2c0 = &i2c1; |
26 | i2c1 = &i2c2; | |
27 | i2c2 = &i2c3; | |
28 | i2c3 = &i2c4; | |
29 | i2c4 = &i2c5; | |
6e58b8f1 S |
30 | serial0 = &uart1; |
31 | serial1 = &uart2; | |
32 | serial2 = &uart3; | |
33 | serial3 = &uart4; | |
34 | serial4 = &uart5; | |
35 | serial5 = &uart6; | |
065bd7fe NM |
36 | serial6 = &uart7; |
37 | serial7 = &uart8; | |
38 | serial8 = &uart9; | |
39 | serial9 = &uart10; | |
ef9c5b69 M |
40 | ethernet0 = &cpsw_emac0; |
41 | ethernet1 = &cpsw_emac1; | |
9ec49b9f RQ |
42 | d_can0 = &dcan1; |
43 | d_can1 = &dcan2; | |
480b2b32 | 44 | spi0 = &qspi; |
6e58b8f1 S |
45 | }; |
46 | ||
6e58b8f1 S |
47 | timer { |
48 | compatible = "arm,armv7-timer"; | |
49 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
50 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
51 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
52 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
783d3186 | 53 | interrupt-parent = <&gic>; |
6e58b8f1 S |
54 | }; |
55 | ||
56 | gic: interrupt-controller@48211000 { | |
57 | compatible = "arm,cortex-a15-gic"; | |
58 | interrupt-controller; | |
59 | #interrupt-cells = <3>; | |
dae320ec | 60 | reg = <0x0 0x48211000 0x0 0x1000>, |
387720c9 | 61 | <0x0 0x48212000 0x0 0x2000>, |
dae320ec LV |
62 | <0x0 0x48214000 0x0 0x2000>, |
63 | <0x0 0x48216000 0x0 0x2000>; | |
6e58b8f1 | 64 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
783d3186 | 65 | interrupt-parent = <&gic>; |
6e58b8f1 S |
66 | }; |
67 | ||
7136d457 MZ |
68 | wakeupgen: interrupt-controller@48281000 { |
69 | compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; | |
70 | interrupt-controller; | |
71 | #interrupt-cells = <3>; | |
dae320ec | 72 | reg = <0x0 0x48281000 0x0 0x1000>; |
7136d457 | 73 | interrupt-parent = <&gic>; |
6e58b8f1 S |
74 | }; |
75 | ||
b82ffb33 DG |
76 | cpus { |
77 | #address-cells = <1>; | |
78 | #size-cells = <0>; | |
79 | ||
80 | cpu0: cpu@0 { | |
81 | device_type = "cpu"; | |
82 | compatible = "arm,cortex-a15"; | |
83 | reg = <0>; | |
84 | ||
a4e5e9f9 | 85 | operating-points-v2 = <&cpu0_opp_table>; |
b82ffb33 DG |
86 | |
87 | clocks = <&dpll_mpu_ck>; | |
88 | clock-names = "cpu"; | |
89 | ||
90 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
91 | ||
92 | /* cooling options */ | |
b82ffb33 | 93 | #cooling-cells = <2>; /* min followed by max */ |
000fb7a0 DG |
94 | |
95 | vbb-supply = <&abb_mpu>; | |
b82ffb33 DG |
96 | }; |
97 | }; | |
98 | ||
a4e5e9f9 DG |
99 | cpu0_opp_table: opp-table { |
100 | compatible = "operating-points-v2-ti-cpu"; | |
101 | syscon = <&scm_wkup>; | |
102 | ||
b9cb2ba7 | 103 | opp_nom-1000000000 { |
a4e5e9f9 | 104 | opp-hz = /bits/ 64 <1000000000>; |
000fb7a0 DG |
105 | opp-microvolt = <1060000 850000 1150000>, |
106 | <1060000 850000 1150000>; | |
a4e5e9f9 DG |
107 | opp-supported-hw = <0xFF 0x01>; |
108 | opp-suspend; | |
109 | }; | |
110 | ||
b9cb2ba7 | 111 | opp_od-1176000000 { |
a4e5e9f9 | 112 | opp-hz = /bits/ 64 <1176000000>; |
000fb7a0 DG |
113 | opp-microvolt = <1160000 885000 1160000>, |
114 | <1160000 885000 1160000>; | |
115 | ||
a4e5e9f9 DG |
116 | opp-supported-hw = <0xFF 0x02>; |
117 | }; | |
bc69fed3 DG |
118 | |
119 | opp_high@1500000000 { | |
120 | opp-hz = /bits/ 64 <1500000000>; | |
121 | opp-microvolt = <1210000 950000 1250000>, | |
122 | <1210000 950000 1250000>; | |
123 | opp-supported-hw = <0xFF 0x04>; | |
124 | }; | |
a4e5e9f9 DG |
125 | }; |
126 | ||
6e58b8f1 | 127 | /* |
5c5be9db | 128 | * The soc node represents the soc top level view. It is used for IPs |
6e58b8f1 S |
129 | * that are not memory mapped in the MPU view or for the MPU itself. |
130 | */ | |
131 | soc { | |
132 | compatible = "ti,omap-infra"; | |
133 | mpu { | |
134 | compatible = "ti,omap5-mpu"; | |
135 | ti,hwmods = "mpu"; | |
136 | }; | |
137 | }; | |
138 | ||
139 | /* | |
140 | * XXX: Use a flat representation of the SOC interconnect. | |
141 | * The real OMAP interconnect network is quite complex. | |
b7ab524b | 142 | * Since it will not bring real advantage to represent that in DT for |
6e58b8f1 S |
143 | * the moment, just use a fake OCP bus entry to represent the whole bus |
144 | * hierarchy. | |
145 | */ | |
146 | ocp { | |
fba387a6 | 147 | compatible = "ti,dra7-l3-noc", "simple-bus"; |
6e58b8f1 S |
148 | #address-cells = <1>; |
149 | #size-cells = <1>; | |
dae320ec | 150 | ranges = <0x0 0x0 0x0 0xc0000000>; |
6e58b8f1 | 151 | ti,hwmods = "l3_main_1", "l3_main_2"; |
dae320ec LV |
152 | reg = <0x0 0x44000000 0x0 0x1000000>, |
153 | <0x0 0x45000000 0x0 0x1000>; | |
783d3186 | 154 | interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
7136d457 | 155 | <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 | 156 | |
4ed0dfe3 | 157 | l4_cfg: interconnect@4a000000 { |
d919501f | 158 | }; |
4ed0dfe3 TL |
159 | l4_wkup: interconnect@4ae00000 { |
160 | }; | |
161 | l4_per1: interconnect@48000000 { | |
162 | }; | |
163 | l4_per2: interconnect@48400000 { | |
164 | }; | |
165 | l4_per3: interconnect@48800000 { | |
ee6c7507 TK |
166 | }; |
167 | ||
18dcd79d KVA |
168 | axi@0 { |
169 | compatible = "simple-bus"; | |
170 | #size-cells = <1>; | |
171 | #address-cells = <1>; | |
172 | ranges = <0x51000000 0x51000000 0x3000 | |
173 | 0x0 0x20000000 0x10000000>; | |
d23f3839 KVA |
174 | /** |
175 | * To enable PCI endpoint mode, disable the pcie1_rc | |
176 | * node and enable pcie1_ep mode. | |
177 | */ | |
178 | pcie1_rc: pcie@51000000 { | |
18dcd79d KVA |
179 | reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; |
180 | reg-names = "rc_dbics", "ti_conf", "config"; | |
181 | interrupts = <0 232 0x4>, <0 233 0x4>; | |
182 | #address-cells = <3>; | |
183 | #size-cells = <2>; | |
184 | device_type = "pci"; | |
185 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
186 | 0x82000000 0 0x20013000 0x13000 0 0xffed000>; | |
7d79f609 | 187 | bus-range = <0x00 0xff>; |
18dcd79d KVA |
188 | #interrupt-cells = <1>; |
189 | num-lanes = <1>; | |
bed596da | 190 | linux,pci-domain = <0>; |
18dcd79d KVA |
191 | ti,hwmods = "pcie1"; |
192 | phys = <&pcie1_phy>; | |
193 | phy-names = "pcie-phy0"; | |
b5acec09 | 194 | ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; |
18dcd79d KVA |
195 | interrupt-map-mask = <0 0 0 7>; |
196 | interrupt-map = <0 0 0 1 &pcie1_intc 1>, | |
197 | <0 0 0 2 &pcie1_intc 2>, | |
198 | <0 0 0 3 &pcie1_intc 3>, | |
199 | <0 0 0 4 &pcie1_intc 4>; | |
b830526f | 200 | ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; |
d23f3839 | 201 | status = "disabled"; |
18dcd79d KVA |
202 | pcie1_intc: interrupt-controller { |
203 | interrupt-controller; | |
204 | #address-cells = <0>; | |
205 | #interrupt-cells = <1>; | |
206 | }; | |
207 | }; | |
d23f3839 KVA |
208 | |
209 | pcie1_ep: pcie_ep@51000000 { | |
d23f3839 KVA |
210 | reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; |
211 | reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; | |
212 | interrupts = <0 232 0x4>; | |
213 | num-lanes = <1>; | |
214 | num-ib-windows = <4>; | |
215 | num-ob-windows = <16>; | |
216 | ti,hwmods = "pcie1"; | |
217 | phys = <&pcie1_phy>; | |
218 | phy-names = "pcie-phy0"; | |
6d0af44a | 219 | ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; |
b5acec09 | 220 | ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; |
d23f3839 KVA |
221 | status = "disabled"; |
222 | }; | |
18dcd79d KVA |
223 | }; |
224 | ||
225 | axi@1 { | |
226 | compatible = "simple-bus"; | |
227 | #size-cells = <1>; | |
228 | #address-cells = <1>; | |
229 | ranges = <0x51800000 0x51800000 0x3000 | |
230 | 0x0 0x30000000 0x10000000>; | |
231 | status = "disabled"; | |
1ac19c8b | 232 | pcie2_rc: pcie@51800000 { |
18dcd79d KVA |
233 | reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; |
234 | reg-names = "rc_dbics", "ti_conf", "config"; | |
235 | interrupts = <0 355 0x4>, <0 356 0x4>; | |
236 | #address-cells = <3>; | |
237 | #size-cells = <2>; | |
238 | device_type = "pci"; | |
239 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
240 | 0x82000000 0 0x30013000 0x13000 0 0xffed000>; | |
7d79f609 | 241 | bus-range = <0x00 0xff>; |
18dcd79d KVA |
242 | #interrupt-cells = <1>; |
243 | num-lanes = <1>; | |
bed596da | 244 | linux,pci-domain = <1>; |
18dcd79d KVA |
245 | ti,hwmods = "pcie2"; |
246 | phys = <&pcie2_phy>; | |
247 | phy-names = "pcie-phy0"; | |
248 | interrupt-map-mask = <0 0 0 7>; | |
249 | interrupt-map = <0 0 0 1 &pcie2_intc 1>, | |
250 | <0 0 0 2 &pcie2_intc 2>, | |
251 | <0 0 0 3 &pcie2_intc 3>, | |
252 | <0 0 0 4 &pcie2_intc 4>; | |
b830526f | 253 | ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; |
18dcd79d KVA |
254 | pcie2_intc: interrupt-controller { |
255 | interrupt-controller; | |
256 | #address-cells = <0>; | |
257 | #interrupt-cells = <1>; | |
258 | }; | |
259 | }; | |
260 | }; | |
261 | ||
a5fa09b6 DG |
262 | ocmcram1: ocmcram@40300000 { |
263 | compatible = "mmio-sram"; | |
264 | reg = <0x40300000 0x80000>; | |
265 | ranges = <0x0 0x40300000 0x80000>; | |
266 | #address-cells = <1>; | |
267 | #size-cells = <1>; | |
fae3a9f0 DG |
268 | /* |
269 | * This is a placeholder for an optional reserved | |
270 | * region for use by secure software. The size | |
271 | * of this region is not known until runtime so it | |
272 | * is set as zero to either be updated to reserve | |
273 | * space or left unchanged to leave all SRAM for use. | |
274 | * On HS parts that that require the reserved region | |
275 | * either the bootloader can update the size to | |
276 | * the required amount or the node can be overridden | |
277 | * from the board dts file for the secure platform. | |
278 | */ | |
279 | sram-hs@0 { | |
280 | compatible = "ti,secure-ram"; | |
281 | reg = <0x0 0x0>; | |
282 | }; | |
a5fa09b6 DG |
283 | }; |
284 | ||
285 | /* | |
286 | * NOTE: ocmcram2 and ocmcram3 are not available on all | |
287 | * DRA7xx and AM57xx variants. Confirm availability in | |
288 | * the data manual for the exact part number in use | |
289 | * before enabling these nodes in the board dts file. | |
290 | */ | |
291 | ocmcram2: ocmcram@40400000 { | |
292 | status = "disabled"; | |
293 | compatible = "mmio-sram"; | |
294 | reg = <0x40400000 0x100000>; | |
295 | ranges = <0x0 0x40400000 0x100000>; | |
296 | #address-cells = <1>; | |
297 | #size-cells = <1>; | |
298 | }; | |
299 | ||
300 | ocmcram3: ocmcram@40500000 { | |
301 | status = "disabled"; | |
302 | compatible = "mmio-sram"; | |
303 | reg = <0x40500000 0x100000>; | |
304 | ranges = <0x0 0x40500000 0x100000>; | |
305 | #address-cells = <1>; | |
306 | #size-cells = <1>; | |
307 | }; | |
308 | ||
f7397edf K |
309 | bandgap: bandgap@4a0021e0 { |
310 | reg = <0x4a0021e0 0xc | |
311 | 0x4a00232c 0xc | |
312 | 0x4a002380 0x2c | |
313 | 0x4a0023C0 0x3c | |
314 | 0x4a002564 0x8 | |
315 | 0x4a002574 0x50>; | |
316 | compatible = "ti,dra752-bandgap"; | |
317 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
318 | #thermal-sensor-cells = <1>; | |
319 | }; | |
320 | ||
99639ace SA |
321 | dsp1_system: dsp_system@40d00000 { |
322 | compatible = "syscon"; | |
323 | reg = <0x40d00000 0x100>; | |
324 | }; | |
325 | ||
eba6130b TL |
326 | dra7_iodelay_core: padconf@4844a000 { |
327 | compatible = "ti,dra7-iodelay"; | |
328 | reg = <0x4844a000 0x0d1c>; | |
329 | #address-cells = <1>; | |
330 | #size-cells = <0>; | |
331 | #pinctrl-cells = <2>; | |
332 | }; | |
333 | ||
248948fb PU |
334 | edma: edma@43300000 { |
335 | compatible = "ti,edma3-tpcc"; | |
336 | ti,hwmods = "tpcc"; | |
337 | reg = <0x43300000 0x100000>; | |
338 | reg-names = "edma3_cc"; | |
339 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, | |
340 | <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, | |
341 | <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; | |
a5206553 | 342 | interrupt-names = "edma3_ccint", "edma3_mperr", |
248948fb PU |
343 | "edma3_ccerrint"; |
344 | dma-requests = <64>; | |
345 | #dma-cells = <2>; | |
346 | ||
347 | ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; | |
348 | ||
349 | /* | |
350 | * memcpy is disabled, can be enabled with: | |
351 | * ti,edma-memcpy-channels = <20 21>; | |
352 | * for example. Note that these channels need to be | |
353 | * masked in the xbar as well. | |
354 | */ | |
355 | }; | |
356 | ||
357 | edma_tptc0: tptc@43400000 { | |
358 | compatible = "ti,edma3-tptc"; | |
359 | ti,hwmods = "tptc0"; | |
360 | reg = <0x43400000 0x100000>; | |
361 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; | |
362 | interrupt-names = "edma3_tcerrint"; | |
363 | }; | |
364 | ||
365 | edma_tptc1: tptc@43500000 { | |
366 | compatible = "ti,edma3-tptc"; | |
367 | ti,hwmods = "tptc1"; | |
368 | reg = <0x43500000 0x100000>; | |
369 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; | |
370 | interrupt-names = "edma3_tcerrint"; | |
371 | }; | |
372 | ||
1a5fe3ca AT |
373 | dmm@4e000000 { |
374 | compatible = "ti,omap5-dmm"; | |
375 | reg = <0x4e000000 0x800>; | |
a46631c4 | 376 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
1a5fe3ca AT |
377 | ti,hwmods = "dmm"; |
378 | }; | |
379 | ||
2c7e07c5 SA |
380 | mmu0_dsp1: mmu@40d01000 { |
381 | compatible = "ti,dra7-dsp-iommu"; | |
382 | reg = <0x40d01000 0x100>; | |
383 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
384 | ti,hwmods = "mmu0_dsp1"; | |
385 | #iommu-cells = <0>; | |
386 | ti,syscon-mmuconfig = <&dsp1_system 0x0>; | |
387 | status = "disabled"; | |
388 | }; | |
389 | ||
390 | mmu1_dsp1: mmu@40d02000 { | |
391 | compatible = "ti,dra7-dsp-iommu"; | |
392 | reg = <0x40d02000 0x100>; | |
393 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
394 | ti,hwmods = "mmu1_dsp1"; | |
395 | #iommu-cells = <0>; | |
396 | ti,syscon-mmuconfig = <&dsp1_system 0x1>; | |
397 | status = "disabled"; | |
398 | }; | |
399 | ||
400 | mmu_ipu1: mmu@58882000 { | |
401 | compatible = "ti,dra7-iommu"; | |
402 | reg = <0x58882000 0x100>; | |
403 | interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; | |
404 | ti,hwmods = "mmu_ipu1"; | |
405 | #iommu-cells = <0>; | |
406 | ti,iommu-bus-err-back; | |
407 | status = "disabled"; | |
408 | }; | |
409 | ||
410 | mmu_ipu2: mmu@55082000 { | |
411 | compatible = "ti,dra7-iommu"; | |
412 | reg = <0x55082000 0x100>; | |
413 | interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; | |
414 | ti,hwmods = "mmu_ipu2"; | |
415 | #iommu-cells = <0>; | |
416 | ti,iommu-bus-err-back; | |
417 | status = "disabled"; | |
418 | }; | |
419 | ||
a1b8ee10 NM |
420 | abb_mpu: regulator-abb-mpu { |
421 | compatible = "ti,abb-v3"; | |
422 | regulator-name = "abb_mpu"; | |
423 | #address-cells = <0>; | |
424 | #size-cells = <0>; | |
425 | clocks = <&sys_clkin1>; | |
426 | ti,settling-time = <50>; | |
427 | ti,clock-cycles = <16>; | |
428 | ||
429 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, | |
18227346 | 430 | <0x4ae06014 0x4>, <0x4a003b20 0xc>, |
a1b8ee10 NM |
431 | <0x4ae0c158 0x4>; |
432 | reg-names = "setup-address", "control-address", | |
433 | "int-address", "efuse-address", | |
434 | "ldo-address"; | |
435 | ti,tranxdone-status-mask = <0x80>; | |
436 | /* LDOVBBMPU_FBB_MUX_CTRL */ | |
437 | ti,ldovbb-override-mask = <0x400>; | |
438 | /* LDOVBBMPU_FBB_VSET_OUT */ | |
439 | ti,ldovbb-vset-mask = <0x1F>; | |
440 | ||
441 | /* | |
442 | * NOTE: only FBB mode used but actual vset will | |
443 | * determine final biasing | |
444 | */ | |
445 | ti,abb_info = < | |
446 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
447 | 1060000 0 0x0 0 0x02000000 0x01F00000 | |
448 | 1160000 0 0x4 0 0x02000000 0x01F00000 | |
449 | 1210000 0 0x8 0 0x02000000 0x01F00000 | |
450 | >; | |
451 | }; | |
452 | ||
453 | abb_ivahd: regulator-abb-ivahd { | |
454 | compatible = "ti,abb-v3"; | |
455 | regulator-name = "abb_ivahd"; | |
456 | #address-cells = <0>; | |
457 | #size-cells = <0>; | |
458 | clocks = <&sys_clkin1>; | |
459 | ti,settling-time = <50>; | |
460 | ti,clock-cycles = <16>; | |
461 | ||
462 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, | |
18227346 | 463 | <0x4ae06010 0x4>, <0x4a0025cc 0xc>, |
a1b8ee10 NM |
464 | <0x4a002470 0x4>; |
465 | reg-names = "setup-address", "control-address", | |
466 | "int-address", "efuse-address", | |
467 | "ldo-address"; | |
468 | ti,tranxdone-status-mask = <0x40000000>; | |
469 | /* LDOVBBIVA_FBB_MUX_CTRL */ | |
470 | ti,ldovbb-override-mask = <0x400>; | |
471 | /* LDOVBBIVA_FBB_VSET_OUT */ | |
472 | ti,ldovbb-vset-mask = <0x1F>; | |
473 | ||
474 | /* | |
475 | * NOTE: only FBB mode used but actual vset will | |
476 | * determine final biasing | |
477 | */ | |
478 | ti,abb_info = < | |
479 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
480 | 1055000 0 0x0 0 0x02000000 0x01F00000 | |
481 | 1150000 0 0x4 0 0x02000000 0x01F00000 | |
482 | 1250000 0 0x8 0 0x02000000 0x01F00000 | |
483 | >; | |
484 | }; | |
485 | ||
486 | abb_dspeve: regulator-abb-dspeve { | |
487 | compatible = "ti,abb-v3"; | |
488 | regulator-name = "abb_dspeve"; | |
489 | #address-cells = <0>; | |
490 | #size-cells = <0>; | |
491 | clocks = <&sys_clkin1>; | |
492 | ti,settling-time = <50>; | |
493 | ti,clock-cycles = <16>; | |
494 | ||
495 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, | |
18227346 | 496 | <0x4ae06010 0x4>, <0x4a0025e0 0xc>, |
a1b8ee10 NM |
497 | <0x4a00246c 0x4>; |
498 | reg-names = "setup-address", "control-address", | |
499 | "int-address", "efuse-address", | |
500 | "ldo-address"; | |
501 | ti,tranxdone-status-mask = <0x20000000>; | |
502 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ | |
503 | ti,ldovbb-override-mask = <0x400>; | |
504 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ | |
505 | ti,ldovbb-vset-mask = <0x1F>; | |
506 | ||
507 | /* | |
508 | * NOTE: only FBB mode used but actual vset will | |
509 | * determine final biasing | |
510 | */ | |
511 | ti,abb_info = < | |
512 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
513 | 1055000 0 0x0 0 0x02000000 0x01F00000 | |
514 | 1150000 0 0x4 0 0x02000000 0x01F00000 | |
515 | 1250000 0 0x8 0 0x02000000 0x01F00000 | |
516 | >; | |
517 | }; | |
518 | ||
519 | abb_gpu: regulator-abb-gpu { | |
520 | compatible = "ti,abb-v3"; | |
521 | regulator-name = "abb_gpu"; | |
522 | #address-cells = <0>; | |
523 | #size-cells = <0>; | |
524 | clocks = <&sys_clkin1>; | |
525 | ti,settling-time = <50>; | |
526 | ti,clock-cycles = <16>; | |
527 | ||
528 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, | |
18227346 | 529 | <0x4ae06010 0x4>, <0x4a003b08 0xc>, |
a1b8ee10 NM |
530 | <0x4ae0c154 0x4>; |
531 | reg-names = "setup-address", "control-address", | |
532 | "int-address", "efuse-address", | |
533 | "ldo-address"; | |
534 | ti,tranxdone-status-mask = <0x10000000>; | |
535 | /* LDOVBBGPU_FBB_MUX_CTRL */ | |
536 | ti,ldovbb-override-mask = <0x400>; | |
537 | /* LDOVBBGPU_FBB_VSET_OUT */ | |
538 | ti,ldovbb-vset-mask = <0x1F>; | |
539 | ||
540 | /* | |
541 | * NOTE: only FBB mode used but actual vset will | |
542 | * determine final biasing | |
543 | */ | |
544 | ti,abb_info = < | |
545 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
546 | 1090000 0 0x0 0 0x02000000 0x01F00000 | |
547 | 1210000 0 0x4 0 0x02000000 0x01F00000 | |
548 | 1280000 0 0x8 0 0x02000000 0x01F00000 | |
549 | >; | |
550 | }; | |
551 | ||
cc893871 | 552 | qspi: spi@4b300000 { |
dc2dd5b8 | 553 | compatible = "ti,dra7xxx-qspi"; |
1929d0b5 V |
554 | reg = <0x4b300000 0x100>, |
555 | <0x5c000000 0x4000000>; | |
556 | reg-names = "qspi_base", "qspi_mmap"; | |
557 | syscon-chipselects = <&scm_conf 0x558>; | |
dc2dd5b8 SP |
558 | #address-cells = <1>; |
559 | #size-cells = <0>; | |
560 | ti,hwmods = "qspi"; | |
b5f8ffbb | 561 | clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; |
dc2dd5b8 SP |
562 | clock-names = "fck"; |
563 | num-cs = <4>; | |
a46631c4 | 564 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
dc2dd5b8 SP |
565 | status = "disabled"; |
566 | }; | |
7be80569 | 567 | |
7be80569 | 568 | /* OCP2SCP3 */ |
7be80569 B |
569 | sata: sata@4a141100 { |
570 | compatible = "snps,dwc-ahci"; | |
571 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; | |
a46631c4 | 572 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
7be80569 B |
573 | phys = <&sata_phy>; |
574 | phy-names = "sata-phy"; | |
b5f8ffbb | 575 | clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; |
7be80569 | 576 | ti,hwmods = "sata"; |
87cb1291 | 577 | ports-implemented = <0x1>; |
7be80569 | 578 | }; |
fbf3e552 | 579 | |
fbf3e552 | 580 | /* OCP2SCP1 */ |
fbf3e552 | 581 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ |
ff66a3c8 MS |
582 | gpmc: gpmc@50000000 { |
583 | compatible = "ti,am3352-gpmc"; | |
584 | ti,hwmods = "gpmc"; | |
585 | reg = <0x50000000 0x37c>; /* device IO registers */ | |
a46631c4 | 586 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
10ce2404 FCJ |
587 | dmas = <&edma_xbar 4 0>; |
588 | dma-names = "rxtx"; | |
ff66a3c8 MS |
589 | gpmc,num-cs = <8>; |
590 | gpmc,num-waitpins = <2>; | |
591 | #address-cells = <2>; | |
592 | #size-cells = <1>; | |
488f270d RQ |
593 | interrupt-controller; |
594 | #interrupt-cells = <2>; | |
845b1a26 RQ |
595 | gpio-controller; |
596 | #gpio-cells = <2>; | |
ff66a3c8 MS |
597 | status = "disabled"; |
598 | }; | |
2ca0945f | 599 | |
783d3186 | 600 | crossbar_mpu: crossbar@4a002a48 { |
a46631c4 S |
601 | compatible = "ti,irq-crossbar"; |
602 | reg = <0x4a002a48 0x130>; | |
783d3186 | 603 | interrupt-controller; |
7136d457 | 604 | interrupt-parent = <&wakeupgen>; |
783d3186 | 605 | #interrupt-cells = <3>; |
a46631c4 S |
606 | ti,max-irqs = <160>; |
607 | ti,max-crossbar-sources = <MAX_SOURCES>; | |
608 | ti,reg-size = <2>; | |
609 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; | |
610 | ti,irqs-skip = <10 133 139 140>; | |
611 | ti,irqs-safe-map = <0>; | |
612 | }; | |
ef9c5b69 | 613 | |
95c1cd13 TV |
614 | dss: dss@58000000 { |
615 | compatible = "ti,dra7-dss"; | |
616 | /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ | |
617 | /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ | |
618 | status = "disabled"; | |
619 | ti,hwmods = "dss_core"; | |
620 | /* CTRL_CORE_DSS_PLL_CONTROL */ | |
621 | syscon-pll-ctrl = <&scm_conf 0x538>; | |
622 | #address-cells = <1>; | |
623 | #size-cells = <1>; | |
624 | ranges; | |
625 | ||
626 | dispc@58001000 { | |
627 | compatible = "ti,dra7-dispc"; | |
628 | reg = <0x58001000 0x1000>; | |
629 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
630 | ti,hwmods = "dss_dispc"; | |
b5f8ffbb | 631 | clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; |
95c1cd13 TV |
632 | clock-names = "fck"; |
633 | /* CTRL_CORE_SMA_SW_1 */ | |
634 | syscon-pol = <&scm_conf 0x534>; | |
635 | }; | |
636 | ||
637 | hdmi: encoder@58060000 { | |
638 | compatible = "ti,dra7-hdmi"; | |
639 | reg = <0x58040000 0x200>, | |
640 | <0x58040200 0x80>, | |
641 | <0x58040300 0x80>, | |
642 | <0x58060000 0x19000>; | |
643 | reg-names = "wp", "pll", "phy", "core"; | |
644 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
645 | status = "disabled"; | |
646 | ti,hwmods = "dss_hdmi"; | |
b5f8ffbb TK |
647 | clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, |
648 | <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; | |
95c1cd13 | 649 | clock-names = "fck", "sys_clk"; |
1239738f PU |
650 | dmas = <&sdma_xbar 76>; |
651 | dma-names = "audio_tx"; | |
95c1cd13 TV |
652 | }; |
653 | }; | |
34370142 | 654 | |
e7fd15c1 JF |
655 | aes1: aes@4b500000 { |
656 | compatible = "ti,omap4-aes"; | |
657 | ti,hwmods = "aes1"; | |
658 | reg = <0x4b500000 0xa0>; | |
659 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
660 | dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; | |
661 | dma-names = "tx", "rx"; | |
662 | clocks = <&l3_iclk_div>; | |
663 | clock-names = "fck"; | |
664 | }; | |
665 | ||
666 | aes2: aes@4b700000 { | |
667 | compatible = "ti,omap4-aes"; | |
668 | ti,hwmods = "aes2"; | |
669 | reg = <0x4b700000 0xa0>; | |
670 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
671 | dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; | |
672 | dma-names = "tx", "rx"; | |
673 | clocks = <&l3_iclk_div>; | |
674 | clock-names = "fck"; | |
675 | }; | |
676 | ||
bac9d0b8 JF |
677 | des: des@480a5000 { |
678 | compatible = "ti,omap4-des"; | |
679 | ti,hwmods = "des"; | |
680 | reg = <0x480a5000 0xa0>; | |
681 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
682 | dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; | |
683 | dma-names = "tx", "rx"; | |
684 | clocks = <&l3_iclk_div>; | |
685 | clock-names = "fck"; | |
686 | }; | |
da34609d LV |
687 | |
688 | sham: sham@53100000 { | |
689 | compatible = "ti,omap5-sham"; | |
690 | ti,hwmods = "sham"; | |
691 | reg = <0x4b101000 0x300>; | |
692 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
693 | dmas = <&edma_xbar 119 0>; | |
694 | dma-names = "rx"; | |
695 | clocks = <&l3_iclk_div>; | |
696 | clock-names = "fck"; | |
697 | }; | |
610e9c4a | 698 | |
dbef1964 DG |
699 | opp_supply_mpu: opp-supply@4a003b20 { |
700 | compatible = "ti,omap5-opp-supply"; | |
701 | reg = <0x4a003b20 0xc>; | |
702 | ti,efuse-settings = < | |
703 | /* uV offset */ | |
704 | 1060000 0x0 | |
705 | 1160000 0x4 | |
706 | 1210000 0x8 | |
707 | >; | |
708 | ti,absolute-max-voltage-uv = <1500000>; | |
709 | }; | |
710 | ||
6e58b8f1 | 711 | }; |
f7397edf K |
712 | |
713 | thermal_zones: thermal-zones { | |
714 | #include "omap4-cpu-thermal.dtsi" | |
715 | #include "omap5-gpu-thermal.dtsi" | |
716 | #include "omap5-core-thermal.dtsi" | |
667f2599 K |
717 | #include "dra7-dspeve-thermal.dtsi" |
718 | #include "dra7-iva-thermal.dtsi" | |
f7397edf K |
719 | }; |
720 | ||
721 | }; | |
722 | ||
723 | &cpu_thermal { | |
724 | polling-delay = <500>; /* milliseconds */ | |
fb51ae0a K |
725 | coefficients = <0 2000>; |
726 | }; | |
727 | ||
728 | &gpu_thermal { | |
729 | coefficients = <0 2000>; | |
730 | }; | |
731 | ||
732 | &core_thermal { | |
733 | coefficients = <0 2000>; | |
734 | }; | |
735 | ||
736 | &dspeve_thermal { | |
737 | coefficients = <0 2000>; | |
738 | }; | |
739 | ||
740 | &iva_thermal { | |
741 | coefficients = <0 2000>; | |
6e58b8f1 | 742 | }; |
ee6c7507 | 743 | |
bca52388 RK |
744 | &cpu_crit { |
745 | temperature = <120000>; /* milli Celsius */ | |
746 | }; | |
747 | ||
64c358b3 RK |
748 | &core_crit { |
749 | temperature = <120000>; /* milli Celsius */ | |
750 | }; | |
751 | ||
752 | &gpu_crit { | |
753 | temperature = <120000>; /* milli Celsius */ | |
754 | }; | |
755 | ||
756 | &dspeve_crit { | |
757 | temperature = <120000>; /* milli Celsius */ | |
758 | }; | |
759 | ||
760 | &iva_crit { | |
761 | temperature = <120000>; /* milli Celsius */ | |
762 | }; | |
4ed0dfe3 TL |
763 | |
764 | #include "dra7-l4.dtsi" | |
765 | #include "dra7xx-clocks.dtsi" |