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6e58b8f1 S |
1 | /* |
2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
11 | #include <dt-bindings/pinctrl/dra.h> | |
12 | ||
13 | #include "skeleton.dtsi" | |
14 | ||
a46631c4 S |
15 | #define MAX_SOURCES 400 |
16 | #define DIRECT_IRQ(irq) (MAX_SOURCES + irq) | |
17 | ||
6e58b8f1 S |
18 | / { |
19 | #address-cells = <1>; | |
20 | #size-cells = <1>; | |
21 | ||
22 | compatible = "ti,dra7xx"; | |
23 | interrupt-parent = <&gic>; | |
24 | ||
25 | aliases { | |
20b80942 NM |
26 | i2c0 = &i2c1; |
27 | i2c1 = &i2c2; | |
28 | i2c2 = &i2c3; | |
29 | i2c3 = &i2c4; | |
30 | i2c4 = &i2c5; | |
6e58b8f1 S |
31 | serial0 = &uart1; |
32 | serial1 = &uart2; | |
33 | serial2 = &uart3; | |
34 | serial3 = &uart4; | |
35 | serial4 = &uart5; | |
36 | serial5 = &uart6; | |
ef9c5b69 M |
37 | ethernet0 = &cpsw_emac0; |
38 | ethernet1 = &cpsw_emac1; | |
6e58b8f1 S |
39 | }; |
40 | ||
6e58b8f1 S |
41 | timer { |
42 | compatible = "arm,armv7-timer"; | |
43 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
44 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
45 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
46 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
47 | }; | |
48 | ||
49 | gic: interrupt-controller@48211000 { | |
50 | compatible = "arm,cortex-a15-gic"; | |
51 | interrupt-controller; | |
52 | #interrupt-cells = <3>; | |
51300633 | 53 | arm,routable-irqs = <192>; |
6e58b8f1 S |
54 | reg = <0x48211000 0x1000>, |
55 | <0x48212000 0x1000>, | |
56 | <0x48214000 0x2000>, | |
57 | <0x48216000 0x2000>; | |
58 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
59 | }; | |
60 | ||
61 | /* | |
5c5be9db | 62 | * The soc node represents the soc top level view. It is used for IPs |
6e58b8f1 S |
63 | * that are not memory mapped in the MPU view or for the MPU itself. |
64 | */ | |
65 | soc { | |
66 | compatible = "ti,omap-infra"; | |
67 | mpu { | |
68 | compatible = "ti,omap5-mpu"; | |
69 | ti,hwmods = "mpu"; | |
70 | }; | |
71 | }; | |
72 | ||
73 | /* | |
74 | * XXX: Use a flat representation of the SOC interconnect. | |
75 | * The real OMAP interconnect network is quite complex. | |
b7ab524b | 76 | * Since it will not bring real advantage to represent that in DT for |
6e58b8f1 S |
77 | * the moment, just use a fake OCP bus entry to represent the whole bus |
78 | * hierarchy. | |
79 | */ | |
80 | ocp { | |
fba387a6 | 81 | compatible = "ti,dra7-l3-noc", "simple-bus"; |
6e58b8f1 S |
82 | #address-cells = <1>; |
83 | #size-cells = <1>; | |
84 | ranges; | |
85 | ti,hwmods = "l3_main_1", "l3_main_2"; | |
fba387a6 RN |
86 | reg = <0x44000000 0x1000000>, |
87 | <0x45000000 0x1000>; | |
a46631c4 S |
88 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
89 | <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; | |
6e58b8f1 | 90 | |
ee6c7507 TK |
91 | prm: prm@4ae06000 { |
92 | compatible = "ti,dra7-prm"; | |
93 | reg = <0x4ae06000 0x3000>; | |
5081ce62 | 94 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
ee6c7507 TK |
95 | |
96 | prm_clocks: clocks { | |
97 | #address-cells = <1>; | |
98 | #size-cells = <0>; | |
99 | }; | |
100 | ||
101 | prm_clockdomains: clockdomains { | |
102 | }; | |
103 | }; | |
104 | ||
18dcd79d KVA |
105 | axi@0 { |
106 | compatible = "simple-bus"; | |
107 | #size-cells = <1>; | |
108 | #address-cells = <1>; | |
109 | ranges = <0x51000000 0x51000000 0x3000 | |
110 | 0x0 0x20000000 0x10000000>; | |
111 | pcie@51000000 { | |
112 | compatible = "ti,dra7-pcie"; | |
113 | reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; | |
114 | reg-names = "rc_dbics", "ti_conf", "config"; | |
115 | interrupts = <0 232 0x4>, <0 233 0x4>; | |
116 | #address-cells = <3>; | |
117 | #size-cells = <2>; | |
118 | device_type = "pci"; | |
119 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
120 | 0x82000000 0 0x20013000 0x13000 0 0xffed000>; | |
121 | #interrupt-cells = <1>; | |
122 | num-lanes = <1>; | |
123 | ti,hwmods = "pcie1"; | |
124 | phys = <&pcie1_phy>; | |
125 | phy-names = "pcie-phy0"; | |
126 | interrupt-map-mask = <0 0 0 7>; | |
127 | interrupt-map = <0 0 0 1 &pcie1_intc 1>, | |
128 | <0 0 0 2 &pcie1_intc 2>, | |
129 | <0 0 0 3 &pcie1_intc 3>, | |
130 | <0 0 0 4 &pcie1_intc 4>; | |
131 | pcie1_intc: interrupt-controller { | |
132 | interrupt-controller; | |
133 | #address-cells = <0>; | |
134 | #interrupt-cells = <1>; | |
135 | }; | |
136 | }; | |
137 | }; | |
138 | ||
139 | axi@1 { | |
140 | compatible = "simple-bus"; | |
141 | #size-cells = <1>; | |
142 | #address-cells = <1>; | |
143 | ranges = <0x51800000 0x51800000 0x3000 | |
144 | 0x0 0x30000000 0x10000000>; | |
145 | status = "disabled"; | |
146 | pcie@51000000 { | |
147 | compatible = "ti,dra7-pcie"; | |
148 | reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; | |
149 | reg-names = "rc_dbics", "ti_conf", "config"; | |
150 | interrupts = <0 355 0x4>, <0 356 0x4>; | |
151 | #address-cells = <3>; | |
152 | #size-cells = <2>; | |
153 | device_type = "pci"; | |
154 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
155 | 0x82000000 0 0x30013000 0x13000 0 0xffed000>; | |
156 | #interrupt-cells = <1>; | |
157 | num-lanes = <1>; | |
158 | ti,hwmods = "pcie2"; | |
159 | phys = <&pcie2_phy>; | |
160 | phy-names = "pcie-phy0"; | |
161 | interrupt-map-mask = <0 0 0 7>; | |
162 | interrupt-map = <0 0 0 1 &pcie2_intc 1>, | |
163 | <0 0 0 2 &pcie2_intc 2>, | |
164 | <0 0 0 3 &pcie2_intc 3>, | |
165 | <0 0 0 4 &pcie2_intc 4>; | |
166 | pcie2_intc: interrupt-controller { | |
167 | interrupt-controller; | |
168 | #address-cells = <0>; | |
169 | #interrupt-cells = <1>; | |
170 | }; | |
171 | }; | |
172 | }; | |
173 | ||
ee6c7507 TK |
174 | cm_core_aon: cm_core_aon@4a005000 { |
175 | compatible = "ti,dra7-cm-core-aon"; | |
176 | reg = <0x4a005000 0x2000>; | |
177 | ||
178 | cm_core_aon_clocks: clocks { | |
179 | #address-cells = <1>; | |
180 | #size-cells = <0>; | |
181 | }; | |
182 | ||
183 | cm_core_aon_clockdomains: clockdomains { | |
184 | }; | |
185 | }; | |
186 | ||
187 | cm_core: cm_core@4a008000 { | |
188 | compatible = "ti,dra7-cm-core"; | |
189 | reg = <0x4a008000 0x3000>; | |
190 | ||
191 | cm_core_clocks: clocks { | |
192 | #address-cells = <1>; | |
193 | #size-cells = <0>; | |
194 | }; | |
195 | ||
196 | cm_core_clockdomains: clockdomains { | |
197 | }; | |
198 | }; | |
199 | ||
6e58b8f1 S |
200 | counter32k: counter@4ae04000 { |
201 | compatible = "ti,omap-counter32k"; | |
202 | reg = <0x4ae04000 0x40>; | |
203 | ti,hwmods = "counter_32k"; | |
204 | }; | |
205 | ||
cd042fe5 B |
206 | dra7_ctrl_general: tisyscon@4a002e00 { |
207 | compatible = "syscon"; | |
208 | reg = <0x4a002e00 0x7c>; | |
209 | }; | |
210 | ||
211 | pbias_regulator: pbias_regulator { | |
212 | compatible = "ti,pbias-omap"; | |
213 | reg = <0 0x4>; | |
214 | syscon = <&dra7_ctrl_general>; | |
215 | pbias_mmc_reg: pbias_mmc_omap5 { | |
216 | regulator-name = "pbias_mmc_omap5"; | |
217 | regulator-min-microvolt = <1800000>; | |
218 | regulator-max-microvolt = <3000000>; | |
219 | }; | |
220 | }; | |
221 | ||
6e58b8f1 | 222 | dra7_pmx_core: pinmux@4a003400 { |
817c0378 | 223 | compatible = "ti,dra7-padconf", "pinctrl-single"; |
6e58b8f1 S |
224 | reg = <0x4a003400 0x0464>; |
225 | #address-cells = <1>; | |
226 | #size-cells = <0>; | |
817c0378 NM |
227 | #interrupt-cells = <1>; |
228 | interrupt-controller; | |
6e58b8f1 S |
229 | pinctrl-single,register-width = <32>; |
230 | pinctrl-single,function-mask = <0x3fffffff>; | |
231 | }; | |
232 | ||
233 | sdma: dma-controller@4a056000 { | |
234 | compatible = "ti,omap4430-sdma"; | |
235 | reg = <0x4a056000 0x1000>; | |
a46631c4 S |
236 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
237 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
238 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
239 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
6e58b8f1 S |
240 | #dma-cells = <1>; |
241 | #dma-channels = <32>; | |
242 | #dma-requests = <127>; | |
243 | }; | |
244 | ||
245 | gpio1: gpio@4ae10000 { | |
246 | compatible = "ti,omap4-gpio"; | |
247 | reg = <0x4ae10000 0x200>; | |
a46631c4 | 248 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
249 | ti,hwmods = "gpio1"; |
250 | gpio-controller; | |
251 | #gpio-cells = <2>; | |
252 | interrupt-controller; | |
e49d519c | 253 | #interrupt-cells = <2>; |
6e58b8f1 S |
254 | }; |
255 | ||
256 | gpio2: gpio@48055000 { | |
257 | compatible = "ti,omap4-gpio"; | |
258 | reg = <0x48055000 0x200>; | |
a46631c4 | 259 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
260 | ti,hwmods = "gpio2"; |
261 | gpio-controller; | |
262 | #gpio-cells = <2>; | |
263 | interrupt-controller; | |
e49d519c | 264 | #interrupt-cells = <2>; |
6e58b8f1 S |
265 | }; |
266 | ||
267 | gpio3: gpio@48057000 { | |
268 | compatible = "ti,omap4-gpio"; | |
269 | reg = <0x48057000 0x200>; | |
a46631c4 | 270 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
271 | ti,hwmods = "gpio3"; |
272 | gpio-controller; | |
273 | #gpio-cells = <2>; | |
274 | interrupt-controller; | |
e49d519c | 275 | #interrupt-cells = <2>; |
6e58b8f1 S |
276 | }; |
277 | ||
278 | gpio4: gpio@48059000 { | |
279 | compatible = "ti,omap4-gpio"; | |
280 | reg = <0x48059000 0x200>; | |
a46631c4 | 281 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
282 | ti,hwmods = "gpio4"; |
283 | gpio-controller; | |
284 | #gpio-cells = <2>; | |
285 | interrupt-controller; | |
e49d519c | 286 | #interrupt-cells = <2>; |
6e58b8f1 S |
287 | }; |
288 | ||
289 | gpio5: gpio@4805b000 { | |
290 | compatible = "ti,omap4-gpio"; | |
291 | reg = <0x4805b000 0x200>; | |
a46631c4 | 292 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
293 | ti,hwmods = "gpio5"; |
294 | gpio-controller; | |
295 | #gpio-cells = <2>; | |
296 | interrupt-controller; | |
e49d519c | 297 | #interrupt-cells = <2>; |
6e58b8f1 S |
298 | }; |
299 | ||
300 | gpio6: gpio@4805d000 { | |
301 | compatible = "ti,omap4-gpio"; | |
302 | reg = <0x4805d000 0x200>; | |
a46631c4 | 303 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
304 | ti,hwmods = "gpio6"; |
305 | gpio-controller; | |
306 | #gpio-cells = <2>; | |
307 | interrupt-controller; | |
e49d519c | 308 | #interrupt-cells = <2>; |
6e58b8f1 S |
309 | }; |
310 | ||
311 | gpio7: gpio@48051000 { | |
312 | compatible = "ti,omap4-gpio"; | |
313 | reg = <0x48051000 0x200>; | |
a46631c4 | 314 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
315 | ti,hwmods = "gpio7"; |
316 | gpio-controller; | |
317 | #gpio-cells = <2>; | |
318 | interrupt-controller; | |
e49d519c | 319 | #interrupt-cells = <2>; |
6e58b8f1 S |
320 | }; |
321 | ||
322 | gpio8: gpio@48053000 { | |
323 | compatible = "ti,omap4-gpio"; | |
324 | reg = <0x48053000 0x200>; | |
a46631c4 | 325 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
326 | ti,hwmods = "gpio8"; |
327 | gpio-controller; | |
328 | #gpio-cells = <2>; | |
329 | interrupt-controller; | |
e49d519c | 330 | #interrupt-cells = <2>; |
6e58b8f1 S |
331 | }; |
332 | ||
333 | uart1: serial@4806a000 { | |
334 | compatible = "ti,omap4-uart"; | |
335 | reg = <0x4806a000 0x100>; | |
e2265abe | 336 | interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
337 | ti,hwmods = "uart1"; |
338 | clock-frequency = <48000000>; | |
339 | status = "disabled"; | |
f0199a29 SAS |
340 | dmas = <&sdma 49>, <&sdma 50>; |
341 | dma-names = "tx", "rx"; | |
6e58b8f1 S |
342 | }; |
343 | ||
344 | uart2: serial@4806c000 { | |
345 | compatible = "ti,omap4-uart"; | |
346 | reg = <0x4806c000 0x100>; | |
e2265abe | 347 | interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
348 | ti,hwmods = "uart2"; |
349 | clock-frequency = <48000000>; | |
350 | status = "disabled"; | |
f0199a29 SAS |
351 | dmas = <&sdma 51>, <&sdma 52>; |
352 | dma-names = "tx", "rx"; | |
6e58b8f1 S |
353 | }; |
354 | ||
355 | uart3: serial@48020000 { | |
356 | compatible = "ti,omap4-uart"; | |
357 | reg = <0x48020000 0x100>; | |
e2265abe | 358 | interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
359 | ti,hwmods = "uart3"; |
360 | clock-frequency = <48000000>; | |
361 | status = "disabled"; | |
f0199a29 SAS |
362 | dmas = <&sdma 53>, <&sdma 54>; |
363 | dma-names = "tx", "rx"; | |
6e58b8f1 S |
364 | }; |
365 | ||
366 | uart4: serial@4806e000 { | |
367 | compatible = "ti,omap4-uart"; | |
368 | reg = <0x4806e000 0x100>; | |
e2265abe | 369 | interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
370 | ti,hwmods = "uart4"; |
371 | clock-frequency = <48000000>; | |
372 | status = "disabled"; | |
f0199a29 SAS |
373 | dmas = <&sdma 55>, <&sdma 56>; |
374 | dma-names = "tx", "rx"; | |
6e58b8f1 S |
375 | }; |
376 | ||
377 | uart5: serial@48066000 { | |
378 | compatible = "ti,omap4-uart"; | |
379 | reg = <0x48066000 0x100>; | |
e2265abe | 380 | interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
381 | ti,hwmods = "uart5"; |
382 | clock-frequency = <48000000>; | |
383 | status = "disabled"; | |
f0199a29 SAS |
384 | dmas = <&sdma 63>, <&sdma 64>; |
385 | dma-names = "tx", "rx"; | |
6e58b8f1 S |
386 | }; |
387 | ||
388 | uart6: serial@48068000 { | |
389 | compatible = "ti,omap4-uart"; | |
390 | reg = <0x48068000 0x100>; | |
e2265abe | 391 | interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
392 | ti,hwmods = "uart6"; |
393 | clock-frequency = <48000000>; | |
394 | status = "disabled"; | |
f0199a29 SAS |
395 | dmas = <&sdma 79>, <&sdma 80>; |
396 | dma-names = "tx", "rx"; | |
6e58b8f1 S |
397 | }; |
398 | ||
399 | uart7: serial@48420000 { | |
400 | compatible = "ti,omap4-uart"; | |
401 | reg = <0x48420000 0x100>; | |
e2265abe | 402 | interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
403 | ti,hwmods = "uart7"; |
404 | clock-frequency = <48000000>; | |
405 | status = "disabled"; | |
406 | }; | |
407 | ||
408 | uart8: serial@48422000 { | |
409 | compatible = "ti,omap4-uart"; | |
410 | reg = <0x48422000 0x100>; | |
e2265abe | 411 | interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
412 | ti,hwmods = "uart8"; |
413 | clock-frequency = <48000000>; | |
414 | status = "disabled"; | |
415 | }; | |
416 | ||
417 | uart9: serial@48424000 { | |
418 | compatible = "ti,omap4-uart"; | |
419 | reg = <0x48424000 0x100>; | |
e2265abe | 420 | interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
421 | ti,hwmods = "uart9"; |
422 | clock-frequency = <48000000>; | |
423 | status = "disabled"; | |
424 | }; | |
425 | ||
426 | uart10: serial@4ae2b000 { | |
427 | compatible = "ti,omap4-uart"; | |
428 | reg = <0x4ae2b000 0x100>; | |
e2265abe | 429 | interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
430 | ti,hwmods = "uart10"; |
431 | clock-frequency = <48000000>; | |
432 | status = "disabled"; | |
433 | }; | |
434 | ||
38baefb3 SA |
435 | mailbox1: mailbox@4a0f4000 { |
436 | compatible = "ti,omap4-mailbox"; | |
437 | reg = <0x4a0f4000 0x200>; | |
b46a6ae6 SA |
438 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
439 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
440 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 441 | ti,hwmods = "mailbox1"; |
24df0453 | 442 | #mbox-cells = <1>; |
38baefb3 SA |
443 | ti,mbox-num-users = <3>; |
444 | ti,mbox-num-fifos = <8>; | |
445 | status = "disabled"; | |
446 | }; | |
447 | ||
448 | mailbox2: mailbox@4883a000 { | |
449 | compatible = "ti,omap4-mailbox"; | |
450 | reg = <0x4883a000 0x200>; | |
b46a6ae6 SA |
451 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
452 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, | |
453 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, | |
454 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 455 | ti,hwmods = "mailbox2"; |
24df0453 | 456 | #mbox-cells = <1>; |
38baefb3 SA |
457 | ti,mbox-num-users = <4>; |
458 | ti,mbox-num-fifos = <12>; | |
459 | status = "disabled"; | |
460 | }; | |
461 | ||
462 | mailbox3: mailbox@4883c000 { | |
463 | compatible = "ti,omap4-mailbox"; | |
464 | reg = <0x4883c000 0x200>; | |
b46a6ae6 SA |
465 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
466 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, | |
467 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, | |
468 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 469 | ti,hwmods = "mailbox3"; |
24df0453 | 470 | #mbox-cells = <1>; |
38baefb3 SA |
471 | ti,mbox-num-users = <4>; |
472 | ti,mbox-num-fifos = <12>; | |
473 | status = "disabled"; | |
474 | }; | |
475 | ||
476 | mailbox4: mailbox@4883e000 { | |
477 | compatible = "ti,omap4-mailbox"; | |
478 | reg = <0x4883e000 0x200>; | |
b46a6ae6 SA |
479 | interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
480 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, | |
481 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, | |
482 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 483 | ti,hwmods = "mailbox4"; |
24df0453 | 484 | #mbox-cells = <1>; |
38baefb3 SA |
485 | ti,mbox-num-users = <4>; |
486 | ti,mbox-num-fifos = <12>; | |
487 | status = "disabled"; | |
488 | }; | |
489 | ||
490 | mailbox5: mailbox@48840000 { | |
491 | compatible = "ti,omap4-mailbox"; | |
492 | reg = <0x48840000 0x200>; | |
b46a6ae6 SA |
493 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
494 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, | |
495 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
496 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 497 | ti,hwmods = "mailbox5"; |
24df0453 | 498 | #mbox-cells = <1>; |
38baefb3 SA |
499 | ti,mbox-num-users = <4>; |
500 | ti,mbox-num-fifos = <12>; | |
501 | status = "disabled"; | |
502 | }; | |
503 | ||
504 | mailbox6: mailbox@48842000 { | |
505 | compatible = "ti,omap4-mailbox"; | |
506 | reg = <0x48842000 0x200>; | |
b46a6ae6 SA |
507 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
508 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | |
509 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, | |
510 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 511 | ti,hwmods = "mailbox6"; |
24df0453 | 512 | #mbox-cells = <1>; |
38baefb3 SA |
513 | ti,mbox-num-users = <4>; |
514 | ti,mbox-num-fifos = <12>; | |
515 | status = "disabled"; | |
516 | }; | |
517 | ||
518 | mailbox7: mailbox@48844000 { | |
519 | compatible = "ti,omap4-mailbox"; | |
520 | reg = <0x48844000 0x200>; | |
b46a6ae6 SA |
521 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
522 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, | |
523 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, | |
524 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 525 | ti,hwmods = "mailbox7"; |
24df0453 | 526 | #mbox-cells = <1>; |
38baefb3 SA |
527 | ti,mbox-num-users = <4>; |
528 | ti,mbox-num-fifos = <12>; | |
529 | status = "disabled"; | |
530 | }; | |
531 | ||
532 | mailbox8: mailbox@48846000 { | |
533 | compatible = "ti,omap4-mailbox"; | |
534 | reg = <0x48846000 0x200>; | |
b46a6ae6 SA |
535 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
536 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, | |
537 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, | |
538 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 539 | ti,hwmods = "mailbox8"; |
24df0453 | 540 | #mbox-cells = <1>; |
38baefb3 SA |
541 | ti,mbox-num-users = <4>; |
542 | ti,mbox-num-fifos = <12>; | |
543 | status = "disabled"; | |
544 | }; | |
545 | ||
546 | mailbox9: mailbox@4885e000 { | |
547 | compatible = "ti,omap4-mailbox"; | |
548 | reg = <0x4885e000 0x200>; | |
b46a6ae6 SA |
549 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
550 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, | |
551 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, | |
552 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 553 | ti,hwmods = "mailbox9"; |
24df0453 | 554 | #mbox-cells = <1>; |
38baefb3 SA |
555 | ti,mbox-num-users = <4>; |
556 | ti,mbox-num-fifos = <12>; | |
557 | status = "disabled"; | |
558 | }; | |
559 | ||
560 | mailbox10: mailbox@48860000 { | |
561 | compatible = "ti,omap4-mailbox"; | |
562 | reg = <0x48860000 0x200>; | |
b46a6ae6 SA |
563 | interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
564 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, | |
565 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, | |
566 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 567 | ti,hwmods = "mailbox10"; |
24df0453 | 568 | #mbox-cells = <1>; |
38baefb3 SA |
569 | ti,mbox-num-users = <4>; |
570 | ti,mbox-num-fifos = <12>; | |
571 | status = "disabled"; | |
572 | }; | |
573 | ||
574 | mailbox11: mailbox@48862000 { | |
575 | compatible = "ti,omap4-mailbox"; | |
576 | reg = <0x48862000 0x200>; | |
b46a6ae6 SA |
577 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, |
578 | <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, | |
579 | <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, | |
580 | <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 581 | ti,hwmods = "mailbox11"; |
24df0453 | 582 | #mbox-cells = <1>; |
38baefb3 SA |
583 | ti,mbox-num-users = <4>; |
584 | ti,mbox-num-fifos = <12>; | |
585 | status = "disabled"; | |
586 | }; | |
587 | ||
588 | mailbox12: mailbox@48864000 { | |
589 | compatible = "ti,omap4-mailbox"; | |
590 | reg = <0x48864000 0x200>; | |
b46a6ae6 SA |
591 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, |
592 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, | |
593 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, | |
594 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 595 | ti,hwmods = "mailbox12"; |
24df0453 | 596 | #mbox-cells = <1>; |
38baefb3 SA |
597 | ti,mbox-num-users = <4>; |
598 | ti,mbox-num-fifos = <12>; | |
599 | status = "disabled"; | |
600 | }; | |
601 | ||
602 | mailbox13: mailbox@48802000 { | |
603 | compatible = "ti,omap4-mailbox"; | |
604 | reg = <0x48802000 0x200>; | |
b46a6ae6 SA |
605 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
606 | <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, | |
607 | <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, | |
608 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; | |
38baefb3 | 609 | ti,hwmods = "mailbox13"; |
24df0453 | 610 | #mbox-cells = <1>; |
38baefb3 SA |
611 | ti,mbox-num-users = <4>; |
612 | ti,mbox-num-fifos = <12>; | |
613 | status = "disabled"; | |
614 | }; | |
615 | ||
6e58b8f1 S |
616 | timer1: timer@4ae18000 { |
617 | compatible = "ti,omap5430-timer"; | |
618 | reg = <0x4ae18000 0x80>; | |
a46631c4 | 619 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
620 | ti,hwmods = "timer1"; |
621 | ti,timer-alwon; | |
622 | }; | |
623 | ||
624 | timer2: timer@48032000 { | |
625 | compatible = "ti,omap5430-timer"; | |
626 | reg = <0x48032000 0x80>; | |
a46631c4 | 627 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
628 | ti,hwmods = "timer2"; |
629 | }; | |
630 | ||
631 | timer3: timer@48034000 { | |
632 | compatible = "ti,omap5430-timer"; | |
633 | reg = <0x48034000 0x80>; | |
a46631c4 | 634 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
635 | ti,hwmods = "timer3"; |
636 | }; | |
637 | ||
638 | timer4: timer@48036000 { | |
639 | compatible = "ti,omap5430-timer"; | |
640 | reg = <0x48036000 0x80>; | |
a46631c4 | 641 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
642 | ti,hwmods = "timer4"; |
643 | }; | |
644 | ||
645 | timer5: timer@48820000 { | |
646 | compatible = "ti,omap5430-timer"; | |
647 | reg = <0x48820000 0x80>; | |
a46631c4 | 648 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
649 | ti,hwmods = "timer5"; |
650 | ti,timer-dsp; | |
651 | }; | |
652 | ||
653 | timer6: timer@48822000 { | |
654 | compatible = "ti,omap5430-timer"; | |
655 | reg = <0x48822000 0x80>; | |
a46631c4 | 656 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
657 | ti,hwmods = "timer6"; |
658 | ti,timer-dsp; | |
659 | ti,timer-pwm; | |
660 | }; | |
661 | ||
662 | timer7: timer@48824000 { | |
663 | compatible = "ti,omap5430-timer"; | |
664 | reg = <0x48824000 0x80>; | |
a46631c4 | 665 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
666 | ti,hwmods = "timer7"; |
667 | ti,timer-dsp; | |
668 | }; | |
669 | ||
670 | timer8: timer@48826000 { | |
671 | compatible = "ti,omap5430-timer"; | |
672 | reg = <0x48826000 0x80>; | |
a46631c4 | 673 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
674 | ti,hwmods = "timer8"; |
675 | ti,timer-dsp; | |
676 | ti,timer-pwm; | |
677 | }; | |
678 | ||
679 | timer9: timer@4803e000 { | |
680 | compatible = "ti,omap5430-timer"; | |
681 | reg = <0x4803e000 0x80>; | |
a46631c4 | 682 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
683 | ti,hwmods = "timer9"; |
684 | }; | |
685 | ||
686 | timer10: timer@48086000 { | |
687 | compatible = "ti,omap5430-timer"; | |
688 | reg = <0x48086000 0x80>; | |
a46631c4 | 689 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
690 | ti,hwmods = "timer10"; |
691 | }; | |
692 | ||
693 | timer11: timer@48088000 { | |
694 | compatible = "ti,omap5430-timer"; | |
695 | reg = <0x48088000 0x80>; | |
a46631c4 | 696 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
697 | ti,hwmods = "timer11"; |
698 | ti,timer-pwm; | |
699 | }; | |
700 | ||
701 | timer13: timer@48828000 { | |
702 | compatible = "ti,omap5430-timer"; | |
703 | reg = <0x48828000 0x80>; | |
a46631c4 | 704 | interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
705 | ti,hwmods = "timer13"; |
706 | status = "disabled"; | |
707 | }; | |
708 | ||
709 | timer14: timer@4882a000 { | |
710 | compatible = "ti,omap5430-timer"; | |
711 | reg = <0x4882a000 0x80>; | |
a46631c4 | 712 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
713 | ti,hwmods = "timer14"; |
714 | status = "disabled"; | |
715 | }; | |
716 | ||
717 | timer15: timer@4882c000 { | |
718 | compatible = "ti,omap5430-timer"; | |
719 | reg = <0x4882c000 0x80>; | |
a46631c4 | 720 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
721 | ti,hwmods = "timer15"; |
722 | status = "disabled"; | |
723 | }; | |
724 | ||
725 | timer16: timer@4882e000 { | |
726 | compatible = "ti,omap5430-timer"; | |
727 | reg = <0x4882e000 0x80>; | |
a46631c4 | 728 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
729 | ti,hwmods = "timer16"; |
730 | status = "disabled"; | |
731 | }; | |
732 | ||
733 | wdt2: wdt@4ae14000 { | |
734 | compatible = "ti,omap4-wdt"; | |
735 | reg = <0x4ae14000 0x80>; | |
a46631c4 | 736 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
737 | ti,hwmods = "wd_timer2"; |
738 | }; | |
739 | ||
dbd7c191 SA |
740 | hwspinlock: spinlock@4a0f6000 { |
741 | compatible = "ti,omap4-hwspinlock"; | |
742 | reg = <0x4a0f6000 0x1000>; | |
743 | ti,hwmods = "spinlock"; | |
744 | #hwlock-cells = <1>; | |
745 | }; | |
746 | ||
1a5fe3ca AT |
747 | dmm@4e000000 { |
748 | compatible = "ti,omap5-dmm"; | |
749 | reg = <0x4e000000 0x800>; | |
a46631c4 | 750 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
1a5fe3ca AT |
751 | ti,hwmods = "dmm"; |
752 | }; | |
753 | ||
6e58b8f1 S |
754 | i2c1: i2c@48070000 { |
755 | compatible = "ti,omap4-i2c"; | |
756 | reg = <0x48070000 0x100>; | |
a46631c4 | 757 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
758 | #address-cells = <1>; |
759 | #size-cells = <0>; | |
760 | ti,hwmods = "i2c1"; | |
761 | status = "disabled"; | |
762 | }; | |
763 | ||
764 | i2c2: i2c@48072000 { | |
765 | compatible = "ti,omap4-i2c"; | |
766 | reg = <0x48072000 0x100>; | |
a46631c4 | 767 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
768 | #address-cells = <1>; |
769 | #size-cells = <0>; | |
770 | ti,hwmods = "i2c2"; | |
771 | status = "disabled"; | |
772 | }; | |
773 | ||
774 | i2c3: i2c@48060000 { | |
775 | compatible = "ti,omap4-i2c"; | |
776 | reg = <0x48060000 0x100>; | |
a46631c4 | 777 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
778 | #address-cells = <1>; |
779 | #size-cells = <0>; | |
780 | ti,hwmods = "i2c3"; | |
781 | status = "disabled"; | |
782 | }; | |
783 | ||
784 | i2c4: i2c@4807a000 { | |
785 | compatible = "ti,omap4-i2c"; | |
786 | reg = <0x4807a000 0x100>; | |
a46631c4 | 787 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
788 | #address-cells = <1>; |
789 | #size-cells = <0>; | |
790 | ti,hwmods = "i2c4"; | |
791 | status = "disabled"; | |
792 | }; | |
793 | ||
794 | i2c5: i2c@4807c000 { | |
795 | compatible = "ti,omap4-i2c"; | |
796 | reg = <0x4807c000 0x100>; | |
a46631c4 | 797 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
798 | #address-cells = <1>; |
799 | #size-cells = <0>; | |
800 | ti,hwmods = "i2c5"; | |
801 | status = "disabled"; | |
802 | }; | |
803 | ||
804 | mmc1: mmc@4809c000 { | |
805 | compatible = "ti,omap4-hsmmc"; | |
806 | reg = <0x4809c000 0x400>; | |
a46631c4 | 807 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
808 | ti,hwmods = "mmc1"; |
809 | ti,dual-volt; | |
810 | ti,needs-special-reset; | |
811 | dmas = <&sdma 61>, <&sdma 62>; | |
812 | dma-names = "tx", "rx"; | |
813 | status = "disabled"; | |
cd042fe5 | 814 | pbias-supply = <&pbias_mmc_reg>; |
6e58b8f1 S |
815 | }; |
816 | ||
817 | mmc2: mmc@480b4000 { | |
818 | compatible = "ti,omap4-hsmmc"; | |
819 | reg = <0x480b4000 0x400>; | |
a46631c4 | 820 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
821 | ti,hwmods = "mmc2"; |
822 | ti,needs-special-reset; | |
823 | dmas = <&sdma 47>, <&sdma 48>; | |
824 | dma-names = "tx", "rx"; | |
825 | status = "disabled"; | |
826 | }; | |
827 | ||
828 | mmc3: mmc@480ad000 { | |
829 | compatible = "ti,omap4-hsmmc"; | |
830 | reg = <0x480ad000 0x400>; | |
a46631c4 | 831 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
832 | ti,hwmods = "mmc3"; |
833 | ti,needs-special-reset; | |
834 | dmas = <&sdma 77>, <&sdma 78>; | |
835 | dma-names = "tx", "rx"; | |
836 | status = "disabled"; | |
837 | }; | |
838 | ||
839 | mmc4: mmc@480d1000 { | |
840 | compatible = "ti,omap4-hsmmc"; | |
841 | reg = <0x480d1000 0x400>; | |
a46631c4 | 842 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
843 | ti,hwmods = "mmc4"; |
844 | ti,needs-special-reset; | |
845 | dmas = <&sdma 57>, <&sdma 58>; | |
846 | dma-names = "tx", "rx"; | |
847 | status = "disabled"; | |
848 | }; | |
849 | ||
a1b8ee10 NM |
850 | abb_mpu: regulator-abb-mpu { |
851 | compatible = "ti,abb-v3"; | |
852 | regulator-name = "abb_mpu"; | |
853 | #address-cells = <0>; | |
854 | #size-cells = <0>; | |
855 | clocks = <&sys_clkin1>; | |
856 | ti,settling-time = <50>; | |
857 | ti,clock-cycles = <16>; | |
858 | ||
859 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, | |
860 | <0x4ae06014 0x4>, <0x4a003b20 0x8>, | |
861 | <0x4ae0c158 0x4>; | |
862 | reg-names = "setup-address", "control-address", | |
863 | "int-address", "efuse-address", | |
864 | "ldo-address"; | |
865 | ti,tranxdone-status-mask = <0x80>; | |
866 | /* LDOVBBMPU_FBB_MUX_CTRL */ | |
867 | ti,ldovbb-override-mask = <0x400>; | |
868 | /* LDOVBBMPU_FBB_VSET_OUT */ | |
869 | ti,ldovbb-vset-mask = <0x1F>; | |
870 | ||
871 | /* | |
872 | * NOTE: only FBB mode used but actual vset will | |
873 | * determine final biasing | |
874 | */ | |
875 | ti,abb_info = < | |
876 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
877 | 1060000 0 0x0 0 0x02000000 0x01F00000 | |
878 | 1160000 0 0x4 0 0x02000000 0x01F00000 | |
879 | 1210000 0 0x8 0 0x02000000 0x01F00000 | |
880 | >; | |
881 | }; | |
882 | ||
883 | abb_ivahd: regulator-abb-ivahd { | |
884 | compatible = "ti,abb-v3"; | |
885 | regulator-name = "abb_ivahd"; | |
886 | #address-cells = <0>; | |
887 | #size-cells = <0>; | |
888 | clocks = <&sys_clkin1>; | |
889 | ti,settling-time = <50>; | |
890 | ti,clock-cycles = <16>; | |
891 | ||
892 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, | |
893 | <0x4ae06010 0x4>, <0x4a0025cc 0x8>, | |
894 | <0x4a002470 0x4>; | |
895 | reg-names = "setup-address", "control-address", | |
896 | "int-address", "efuse-address", | |
897 | "ldo-address"; | |
898 | ti,tranxdone-status-mask = <0x40000000>; | |
899 | /* LDOVBBIVA_FBB_MUX_CTRL */ | |
900 | ti,ldovbb-override-mask = <0x400>; | |
901 | /* LDOVBBIVA_FBB_VSET_OUT */ | |
902 | ti,ldovbb-vset-mask = <0x1F>; | |
903 | ||
904 | /* | |
905 | * NOTE: only FBB mode used but actual vset will | |
906 | * determine final biasing | |
907 | */ | |
908 | ti,abb_info = < | |
909 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
910 | 1055000 0 0x0 0 0x02000000 0x01F00000 | |
911 | 1150000 0 0x4 0 0x02000000 0x01F00000 | |
912 | 1250000 0 0x8 0 0x02000000 0x01F00000 | |
913 | >; | |
914 | }; | |
915 | ||
916 | abb_dspeve: regulator-abb-dspeve { | |
917 | compatible = "ti,abb-v3"; | |
918 | regulator-name = "abb_dspeve"; | |
919 | #address-cells = <0>; | |
920 | #size-cells = <0>; | |
921 | clocks = <&sys_clkin1>; | |
922 | ti,settling-time = <50>; | |
923 | ti,clock-cycles = <16>; | |
924 | ||
925 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, | |
926 | <0x4ae06010 0x4>, <0x4a0025e0 0x8>, | |
927 | <0x4a00246c 0x4>; | |
928 | reg-names = "setup-address", "control-address", | |
929 | "int-address", "efuse-address", | |
930 | "ldo-address"; | |
931 | ti,tranxdone-status-mask = <0x20000000>; | |
932 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ | |
933 | ti,ldovbb-override-mask = <0x400>; | |
934 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ | |
935 | ti,ldovbb-vset-mask = <0x1F>; | |
936 | ||
937 | /* | |
938 | * NOTE: only FBB mode used but actual vset will | |
939 | * determine final biasing | |
940 | */ | |
941 | ti,abb_info = < | |
942 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
943 | 1055000 0 0x0 0 0x02000000 0x01F00000 | |
944 | 1150000 0 0x4 0 0x02000000 0x01F00000 | |
945 | 1250000 0 0x8 0 0x02000000 0x01F00000 | |
946 | >; | |
947 | }; | |
948 | ||
949 | abb_gpu: regulator-abb-gpu { | |
950 | compatible = "ti,abb-v3"; | |
951 | regulator-name = "abb_gpu"; | |
952 | #address-cells = <0>; | |
953 | #size-cells = <0>; | |
954 | clocks = <&sys_clkin1>; | |
955 | ti,settling-time = <50>; | |
956 | ti,clock-cycles = <16>; | |
957 | ||
958 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, | |
959 | <0x4ae06010 0x4>, <0x4a003b08 0x8>, | |
960 | <0x4ae0c154 0x4>; | |
961 | reg-names = "setup-address", "control-address", | |
962 | "int-address", "efuse-address", | |
963 | "ldo-address"; | |
964 | ti,tranxdone-status-mask = <0x10000000>; | |
965 | /* LDOVBBGPU_FBB_MUX_CTRL */ | |
966 | ti,ldovbb-override-mask = <0x400>; | |
967 | /* LDOVBBGPU_FBB_VSET_OUT */ | |
968 | ti,ldovbb-vset-mask = <0x1F>; | |
969 | ||
970 | /* | |
971 | * NOTE: only FBB mode used but actual vset will | |
972 | * determine final biasing | |
973 | */ | |
974 | ti,abb_info = < | |
975 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
976 | 1090000 0 0x0 0 0x02000000 0x01F00000 | |
977 | 1210000 0 0x4 0 0x02000000 0x01F00000 | |
978 | 1280000 0 0x8 0 0x02000000 0x01F00000 | |
979 | >; | |
980 | }; | |
981 | ||
6e58b8f1 S |
982 | mcspi1: spi@48098000 { |
983 | compatible = "ti,omap4-mcspi"; | |
984 | reg = <0x48098000 0x200>; | |
a46631c4 | 985 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
986 | #address-cells = <1>; |
987 | #size-cells = <0>; | |
988 | ti,hwmods = "mcspi1"; | |
989 | ti,spi-num-cs = <4>; | |
990 | dmas = <&sdma 35>, | |
991 | <&sdma 36>, | |
992 | <&sdma 37>, | |
993 | <&sdma 38>, | |
994 | <&sdma 39>, | |
995 | <&sdma 40>, | |
996 | <&sdma 41>, | |
997 | <&sdma 42>; | |
998 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
999 | "tx2", "rx2", "tx3", "rx3"; | |
1000 | status = "disabled"; | |
1001 | }; | |
1002 | ||
1003 | mcspi2: spi@4809a000 { | |
1004 | compatible = "ti,omap4-mcspi"; | |
1005 | reg = <0x4809a000 0x200>; | |
a46631c4 | 1006 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1007 | #address-cells = <1>; |
1008 | #size-cells = <0>; | |
1009 | ti,hwmods = "mcspi2"; | |
1010 | ti,spi-num-cs = <2>; | |
1011 | dmas = <&sdma 43>, | |
1012 | <&sdma 44>, | |
1013 | <&sdma 45>, | |
1014 | <&sdma 46>; | |
1015 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
1016 | status = "disabled"; | |
1017 | }; | |
1018 | ||
1019 | mcspi3: spi@480b8000 { | |
1020 | compatible = "ti,omap4-mcspi"; | |
1021 | reg = <0x480b8000 0x200>; | |
a46631c4 | 1022 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1023 | #address-cells = <1>; |
1024 | #size-cells = <0>; | |
1025 | ti,hwmods = "mcspi3"; | |
1026 | ti,spi-num-cs = <2>; | |
1027 | dmas = <&sdma 15>, <&sdma 16>; | |
1028 | dma-names = "tx0", "rx0"; | |
1029 | status = "disabled"; | |
1030 | }; | |
1031 | ||
1032 | mcspi4: spi@480ba000 { | |
1033 | compatible = "ti,omap4-mcspi"; | |
1034 | reg = <0x480ba000 0x200>; | |
a46631c4 | 1035 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
6e58b8f1 S |
1036 | #address-cells = <1>; |
1037 | #size-cells = <0>; | |
1038 | ti,hwmods = "mcspi4"; | |
1039 | ti,spi-num-cs = <1>; | |
1040 | dmas = <&sdma 70>, <&sdma 71>; | |
1041 | dma-names = "tx0", "rx0"; | |
1042 | status = "disabled"; | |
1043 | }; | |
dc2dd5b8 SP |
1044 | |
1045 | qspi: qspi@4b300000 { | |
1046 | compatible = "ti,dra7xxx-qspi"; | |
1047 | reg = <0x4b300000 0x100>; | |
1048 | reg-names = "qspi_base"; | |
1049 | #address-cells = <1>; | |
1050 | #size-cells = <0>; | |
1051 | ti,hwmods = "qspi"; | |
1052 | clocks = <&qspi_gfclk_div>; | |
1053 | clock-names = "fck"; | |
1054 | num-cs = <4>; | |
a46631c4 | 1055 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
dc2dd5b8 SP |
1056 | status = "disabled"; |
1057 | }; | |
7be80569 B |
1058 | |
1059 | omap_control_sata: control-phy@4a002374 { | |
1060 | compatible = "ti,control-phy-pipe3"; | |
1061 | reg = <0x4a002374 0x4>; | |
1062 | reg-names = "power"; | |
1063 | clocks = <&sys_clkin1>; | |
1064 | clock-names = "sysclk"; | |
1065 | }; | |
1066 | ||
1067 | /* OCP2SCP3 */ | |
1068 | ocp2scp@4a090000 { | |
1069 | compatible = "ti,omap-ocp2scp"; | |
1070 | #address-cells = <1>; | |
1071 | #size-cells = <1>; | |
1072 | ranges; | |
1073 | reg = <0x4a090000 0x20>; | |
1074 | ti,hwmods = "ocp2scp3"; | |
1075 | sata_phy: phy@4A096000 { | |
1076 | compatible = "ti,phy-pipe3-sata"; | |
1077 | reg = <0x4A096000 0x80>, /* phy_rx */ | |
1078 | <0x4A096400 0x64>, /* phy_tx */ | |
1079 | <0x4A096800 0x40>; /* pll_ctrl */ | |
1080 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
1081 | ctrl-module = <&omap_control_sata>; | |
1082 | clocks = <&sys_clkin1>; | |
1083 | clock-names = "sysclk"; | |
1084 | #phy-cells = <0>; | |
1085 | }; | |
692df0ef KVA |
1086 | |
1087 | pcie1_phy: pciephy@4a094000 { | |
1088 | compatible = "ti,phy-pipe3-pcie"; | |
1089 | reg = <0x4a094000 0x80>, /* phy_rx */ | |
1090 | <0x4a094400 0x64>; /* phy_tx */ | |
1091 | reg-names = "phy_rx", "phy_tx"; | |
1092 | ctrl-module = <&omap_control_pcie1phy>; | |
1093 | clocks = <&dpll_pcie_ref_ck>, | |
1094 | <&dpll_pcie_ref_m2ldo_ck>, | |
1095 | <&optfclk_pciephy1_32khz>, | |
1096 | <&optfclk_pciephy1_clk>, | |
1097 | <&optfclk_pciephy1_div_clk>, | |
1098 | <&optfclk_pciephy_div>; | |
1099 | clock-names = "dpll_ref", "dpll_ref_m2", | |
1100 | "wkupclk", "refclk", | |
1101 | "div-clk", "phy-div"; | |
1102 | #phy-cells = <0>; | |
1103 | id = <1>; | |
1104 | ti,hwmods = "pcie1-phy"; | |
1105 | }; | |
1106 | ||
1107 | pcie2_phy: pciephy@4a095000 { | |
1108 | compatible = "ti,phy-pipe3-pcie"; | |
1109 | reg = <0x4a095000 0x80>, /* phy_rx */ | |
1110 | <0x4a095400 0x64>; /* phy_tx */ | |
1111 | reg-names = "phy_rx", "phy_tx"; | |
1112 | ctrl-module = <&omap_control_pcie2phy>; | |
1113 | clocks = <&dpll_pcie_ref_ck>, | |
1114 | <&dpll_pcie_ref_m2ldo_ck>, | |
1115 | <&optfclk_pciephy2_32khz>, | |
1116 | <&optfclk_pciephy2_clk>, | |
1117 | <&optfclk_pciephy2_div_clk>, | |
1118 | <&optfclk_pciephy_div>; | |
1119 | clock-names = "dpll_ref", "dpll_ref_m2", | |
1120 | "wkupclk", "refclk", | |
1121 | "div-clk", "phy-div"; | |
1122 | #phy-cells = <0>; | |
1123 | ti,hwmods = "pcie2-phy"; | |
1124 | id = <2>; | |
1125 | status = "disabled"; | |
1126 | }; | |
7be80569 B |
1127 | }; |
1128 | ||
1129 | sata: sata@4a141100 { | |
1130 | compatible = "snps,dwc-ahci"; | |
1131 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; | |
a46631c4 | 1132 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
7be80569 B |
1133 | phys = <&sata_phy>; |
1134 | phy-names = "sata-phy"; | |
1135 | clocks = <&sata_ref_clk>; | |
1136 | ti,hwmods = "sata"; | |
1137 | }; | |
fbf3e552 | 1138 | |
d1ff66b5 KVA |
1139 | omap_control_pcie1phy: control-phy@0x4a003c40 { |
1140 | compatible = "ti,control-phy-pcie"; | |
1141 | reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; | |
1142 | reg-names = "power", "control_sma", "pcie_pcs"; | |
1143 | clocks = <&sys_clkin1>; | |
1144 | clock-names = "sysclk"; | |
1145 | }; | |
1146 | ||
1147 | omap_control_pcie2phy: control-pcie@0x4a003c44 { | |
1148 | compatible = "ti,control-phy-pcie"; | |
1149 | reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; | |
1150 | reg-names = "power", "control_sma", "pcie_pcs"; | |
1151 | clocks = <&sys_clkin1>; | |
1152 | clock-names = "sysclk"; | |
1153 | status = "disabled"; | |
1154 | }; | |
1155 | ||
fbf3e552 RQ |
1156 | omap_control_usb2phy1: control-phy@4a002300 { |
1157 | compatible = "ti,control-phy-usb2"; | |
1158 | reg = <0x4a002300 0x4>; | |
1159 | reg-names = "power"; | |
1160 | }; | |
1161 | ||
1162 | omap_control_usb3phy1: control-phy@4a002370 { | |
1163 | compatible = "ti,control-phy-pipe3"; | |
1164 | reg = <0x4a002370 0x4>; | |
1165 | reg-names = "power"; | |
1166 | }; | |
1167 | ||
1168 | omap_control_usb2phy2: control-phy@0x4a002e74 { | |
1169 | compatible = "ti,control-phy-usb2-dra7"; | |
1170 | reg = <0x4a002e74 0x4>; | |
1171 | reg-names = "power"; | |
1172 | }; | |
1173 | ||
1174 | /* OCP2SCP1 */ | |
1175 | ocp2scp@4a080000 { | |
1176 | compatible = "ti,omap-ocp2scp"; | |
1177 | #address-cells = <1>; | |
1178 | #size-cells = <1>; | |
1179 | ranges; | |
1180 | reg = <0x4a080000 0x20>; | |
1181 | ti,hwmods = "ocp2scp1"; | |
1182 | ||
1183 | usb2_phy1: phy@4a084000 { | |
1184 | compatible = "ti,omap-usb2"; | |
1185 | reg = <0x4a084000 0x400>; | |
1186 | ctrl-module = <&omap_control_usb2phy1>; | |
1187 | clocks = <&usb_phy1_always_on_clk32k>, | |
1188 | <&usb_otg_ss1_refclk960m>; | |
1189 | clock-names = "wkupclk", | |
1190 | "refclk"; | |
1191 | #phy-cells = <0>; | |
1192 | }; | |
1193 | ||
1194 | usb2_phy2: phy@4a085000 { | |
1195 | compatible = "ti,omap-usb2"; | |
1196 | reg = <0x4a085000 0x400>; | |
1197 | ctrl-module = <&omap_control_usb2phy2>; | |
1198 | clocks = <&usb_phy2_always_on_clk32k>, | |
1199 | <&usb_otg_ss2_refclk960m>; | |
1200 | clock-names = "wkupclk", | |
1201 | "refclk"; | |
1202 | #phy-cells = <0>; | |
1203 | }; | |
1204 | ||
1205 | usb3_phy1: phy@4a084400 { | |
1206 | compatible = "ti,omap-usb3"; | |
1207 | reg = <0x4a084400 0x80>, | |
1208 | <0x4a084800 0x64>, | |
1209 | <0x4a084c00 0x40>; | |
1210 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
1211 | ctrl-module = <&omap_control_usb3phy1>; | |
1212 | clocks = <&usb_phy3_always_on_clk32k>, | |
1213 | <&sys_clkin1>, | |
1214 | <&usb_otg_ss1_refclk960m>; | |
1215 | clock-names = "wkupclk", | |
1216 | "sysclk", | |
1217 | "refclk"; | |
1218 | #phy-cells = <0>; | |
1219 | }; | |
1220 | }; | |
1221 | ||
4f6dec70 | 1222 | omap_dwc3_1: omap_dwc3_1@48880000 { |
fbf3e552 RQ |
1223 | compatible = "ti,dwc3"; |
1224 | ti,hwmods = "usb_otg_ss1"; | |
1225 | reg = <0x48880000 0x10000>; | |
a46631c4 | 1226 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
fbf3e552 RQ |
1227 | #address-cells = <1>; |
1228 | #size-cells = <1>; | |
1229 | utmi-mode = <2>; | |
1230 | ranges; | |
1231 | usb1: usb@48890000 { | |
1232 | compatible = "snps,dwc3"; | |
1233 | reg = <0x48890000 0x17000>; | |
a46631c4 | 1234 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
fbf3e552 RQ |
1235 | phys = <&usb2_phy1>, <&usb3_phy1>; |
1236 | phy-names = "usb2-phy", "usb3-phy"; | |
1237 | tx-fifo-resize; | |
1238 | maximum-speed = "super-speed"; | |
1239 | dr_mode = "otg"; | |
1240 | }; | |
1241 | }; | |
1242 | ||
4f6dec70 | 1243 | omap_dwc3_2: omap_dwc3_2@488c0000 { |
fbf3e552 RQ |
1244 | compatible = "ti,dwc3"; |
1245 | ti,hwmods = "usb_otg_ss2"; | |
1246 | reg = <0x488c0000 0x10000>; | |
a46631c4 | 1247 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
fbf3e552 RQ |
1248 | #address-cells = <1>; |
1249 | #size-cells = <1>; | |
1250 | utmi-mode = <2>; | |
1251 | ranges; | |
1252 | usb2: usb@488d0000 { | |
1253 | compatible = "snps,dwc3"; | |
1254 | reg = <0x488d0000 0x17000>; | |
a46631c4 | 1255 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
fbf3e552 RQ |
1256 | phys = <&usb2_phy2>; |
1257 | phy-names = "usb2-phy"; | |
1258 | tx-fifo-resize; | |
1259 | maximum-speed = "high-speed"; | |
1260 | dr_mode = "otg"; | |
1261 | }; | |
1262 | }; | |
1263 | ||
1264 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ | |
4f6dec70 | 1265 | omap_dwc3_3: omap_dwc3_3@48900000 { |
fbf3e552 RQ |
1266 | compatible = "ti,dwc3"; |
1267 | ti,hwmods = "usb_otg_ss3"; | |
1268 | reg = <0x48900000 0x10000>; | |
a46631c4 | 1269 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
fbf3e552 RQ |
1270 | #address-cells = <1>; |
1271 | #size-cells = <1>; | |
1272 | utmi-mode = <2>; | |
1273 | ranges; | |
1274 | status = "disabled"; | |
1275 | usb3: usb@48910000 { | |
1276 | compatible = "snps,dwc3"; | |
1277 | reg = <0x48910000 0x17000>; | |
a46631c4 | 1278 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
fbf3e552 RQ |
1279 | tx-fifo-resize; |
1280 | maximum-speed = "high-speed"; | |
1281 | dr_mode = "otg"; | |
1282 | }; | |
1283 | }; | |
1284 | ||
ff66a3c8 MS |
1285 | elm: elm@48078000 { |
1286 | compatible = "ti,am3352-elm"; | |
1287 | reg = <0x48078000 0xfc0>; /* device IO registers */ | |
a46631c4 | 1288 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
ff66a3c8 MS |
1289 | ti,hwmods = "elm"; |
1290 | status = "disabled"; | |
1291 | }; | |
1292 | ||
1293 | gpmc: gpmc@50000000 { | |
1294 | compatible = "ti,am3352-gpmc"; | |
1295 | ti,hwmods = "gpmc"; | |
1296 | reg = <0x50000000 0x37c>; /* device IO registers */ | |
a46631c4 | 1297 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
ff66a3c8 MS |
1298 | gpmc,num-cs = <8>; |
1299 | gpmc,num-waitpins = <2>; | |
1300 | #address-cells = <2>; | |
1301 | #size-cells = <1>; | |
1302 | status = "disabled"; | |
1303 | }; | |
2ca0945f PU |
1304 | |
1305 | atl: atl@4843c000 { | |
1306 | compatible = "ti,dra7-atl"; | |
1307 | reg = <0x4843c000 0x3ff>; | |
1308 | ti,hwmods = "atl"; | |
1309 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, | |
1310 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; | |
1311 | clocks = <&atl_gfclk_mux>; | |
1312 | clock-names = "fck"; | |
1313 | status = "disabled"; | |
1314 | }; | |
412a9bbd | 1315 | |
a46631c4 S |
1316 | crossbar_mpu: crossbar@4a020000 { |
1317 | compatible = "ti,irq-crossbar"; | |
1318 | reg = <0x4a002a48 0x130>; | |
1319 | ti,max-irqs = <160>; | |
1320 | ti,max-crossbar-sources = <MAX_SOURCES>; | |
1321 | ti,reg-size = <2>; | |
1322 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; | |
1323 | ti,irqs-skip = <10 133 139 140>; | |
1324 | ti,irqs-safe-map = <0>; | |
1325 | }; | |
ef9c5b69 M |
1326 | |
1327 | mac: ethernet@4a100000 { | |
1328 | compatible = "ti,cpsw"; | |
1329 | ti,hwmods = "gmac"; | |
1330 | clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; | |
1331 | clock-names = "fck", "cpts"; | |
1332 | cpdma_channels = <8>; | |
1333 | ale_entries = <1024>; | |
1334 | bd_ram_size = <0x2000>; | |
1335 | no_bd_ram = <0>; | |
1336 | rx_descs = <64>; | |
1337 | mac_control = <0x20>; | |
1338 | slaves = <2>; | |
1339 | active_slave = <0>; | |
1340 | cpts_clock_mult = <0x80000000>; | |
1341 | cpts_clock_shift = <29>; | |
1342 | reg = <0x48484000 0x1000 | |
1343 | 0x48485200 0x2E00>; | |
1344 | #address-cells = <1>; | |
1345 | #size-cells = <1>; | |
1346 | /* | |
1347 | * rx_thresh_pend | |
1348 | * rx_pend | |
1349 | * tx_pend | |
1350 | * misc_pend | |
1351 | */ | |
1352 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
1353 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
1354 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
1355 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; | |
1356 | ranges; | |
1357 | status = "disabled"; | |
1358 | ||
1359 | davinci_mdio: mdio@48485000 { | |
1360 | compatible = "ti,davinci_mdio"; | |
1361 | #address-cells = <1>; | |
1362 | #size-cells = <0>; | |
1363 | ti,hwmods = "davinci_mdio"; | |
1364 | bus_freq = <1000000>; | |
1365 | reg = <0x48485000 0x100>; | |
1366 | }; | |
1367 | ||
1368 | cpsw_emac0: slave@48480200 { | |
1369 | /* Filled in by U-Boot */ | |
1370 | mac-address = [ 00 00 00 00 00 00 ]; | |
1371 | }; | |
1372 | ||
1373 | cpsw_emac1: slave@48480300 { | |
1374 | /* Filled in by U-Boot */ | |
1375 | mac-address = [ 00 00 00 00 00 00 ]; | |
1376 | }; | |
1377 | ||
1378 | phy_sel: cpsw-phy-sel@4a002554 { | |
1379 | compatible = "ti,dra7xx-cpsw-phy-sel"; | |
1380 | reg= <0x4a002554 0x4>; | |
1381 | reg-names = "gmii-sel"; | |
1382 | }; | |
1383 | }; | |
1384 | ||
6e58b8f1 S |
1385 | }; |
1386 | }; | |
ee6c7507 TK |
1387 | |
1388 | /include/ "dra7xx-clocks.dtsi" |