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ARM: dts: dra7xx: Correct mcasp8_ahclkx_mux name
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / dra7.dtsi
CommitLineData
6e58b8f1
S		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
a46631c4 15#define MAX_SOURCES 400
a46631c4 16
6e58b8f1 17/ {
dae320ec
LV		 18 #address-cells = <2>;
19 #size-cells = <2>;
6e58b8f1
S		 20
21 compatible = "ti,dra7xx";
783d3186 22 interrupt-parent = <&crossbar_mpu>;
6e58b8f1
S		 23
24 aliases {
20b80942
NM		 25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 i2c4 = &i2c5;
6e58b8f1
S		 30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
065bd7fe
NM		 36 serial6 = &uart7;
37 serial7 = &uart8;
38 serial8 = &uart9;
39 serial9 = &uart10;
ef9c5b69
M		 40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
9ec49b9f
RQ		 42 d_can0 = &dcan1;
43 d_can1 = &dcan2;
480b2b32 44 spi0 = &qspi;
6e58b8f1
S		 45 };
46
6e58b8f1
S		 47 timer {
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
783d3186 53 interrupt-parent = <&gic>;
6e58b8f1
S		 54 };
55
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
58 interrupt-controller;
59 #interrupt-cells = <3>;
dae320ec
LV		 60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x1000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
6e58b8f1 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
783d3186 65 interrupt-parent = <&gic>;
6e58b8f1
S		 66 };
67
7136d457
MZ		 68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 interrupt-controller;
71 #interrupt-cells = <3>;
dae320ec 72 reg = <0x0 0x48281000 0x0 0x1000>;
7136d457 73 interrupt-parent = <&gic>;
6e58b8f1
S		 74 };
75
76 /*
5c5be9db 77 * The soc node represents the soc top level view. It is used for IPs
6e58b8f1
S		 78 * that are not memory mapped in the MPU view or for the MPU itself.
79 */
80 soc {
81 compatible = "ti,omap-infra";
82 mpu {
83 compatible = "ti,omap5-mpu";
84 ti,hwmods = "mpu";
85 };
86 };
87
88 /*
89 * XXX: Use a flat representation of the SOC interconnect.
90 * The real OMAP interconnect network is quite complex.
b7ab524b 91 * Since it will not bring real advantage to represent that in DT for
6e58b8f1
S		 92 * the moment, just use a fake OCP bus entry to represent the whole bus
93 * hierarchy.
94 */
95 ocp {
fba387a6 96 compatible = "ti,dra7-l3-noc", "simple-bus";
6e58b8f1
S		 97 #address-cells = <1>;
98 #size-cells = <1>;
dae320ec 99 ranges = <0x0 0x0 0x0 0xc0000000>;
6e58b8f1 100 ti,hwmods = "l3_main_1", "l3_main_2";
dae320ec
LV		 101 reg = <0x0 0x44000000 0x0 0x1000000>,
102 <0x0 0x45000000 0x0 0x1000>;
783d3186 103 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
7136d457 104 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 105
d919501f
TK		 106 l4_cfg: l4@4a000000 {
107 compatible = "ti,dra7-l4-cfg", "simple-bus";
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0 0x4a000000 0x22c000>;
ee6c7507 111
d919501f
TK		 112 scm: scm@2000 {
113 compatible = "ti,dra7-scm-core", "simple-bus";
114 reg = <0x2000 0x2000>;
ee6c7507 115 #address-cells = <1>;
d919501f
TK		 116 #size-cells = <1>;
117 ranges = <0 0x2000 0x2000>;
118
119 scm_conf: scm_conf@0 {
cd455673 120 compatible = "syscon", "simple-bus";
d919501f
TK		 121 reg = <0x0 0x1400>;
122 #address-cells = <1>;
123 #size-cells = <1>;
9a5e3f27 124 ranges = <0 0x0 0x1400>;
d919501f 125
308cfdaf 126 pbias_regulator: pbias_regulator@e00 {
737f146f 127 compatible = "ti,pbias-dra7", "ti,pbias-omap";
d919501f
TK		 128 reg = <0xe00 0x4>;
129 syscon = <&scm_conf>;
130 pbias_mmc_reg: pbias_mmc_omap5 {
131 regulator-name = "pbias_mmc_omap5";
132 regulator-min-microvolt = <1800000>;
133 regulator-max-microvolt = <3000000>;
134 };
135 };
2d5a3c80
TV		 136
137 scm_conf_clocks: clocks {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 };
d919501f
TK		 141 };
142
143 dra7_pmx_core: pinmux@1400 {
144 compatible = "ti,dra7-padconf",
145 "pinctrl-single";
1c5cb6fd 146 reg = <0x1400 0x0468>;
d919501f
TK		 147 #address-cells = <1>;
148 #size-cells = <0>;
149 #interrupt-cells = <1>;
150 interrupt-controller;
151 pinctrl-single,register-width = <32>;
152 pinctrl-single,function-mask = <0x3fffffff>;
153 };
33cb3a13
RQ		 154
155 scm_conf1: scm_conf@1c04 {
156 compatible = "syscon";
157 reg = <0x1c04 0x0020>;
158 };
43acf169
KVA		 159
160 scm_conf_pcie: scm_conf@1c24 {
161 compatible = "syscon";
162 reg = <0x1c24 0x0024>;
163 };
3d2a58bc
PU		 164
165 sdma_xbar: dma-router@b78 {
166 compatible = "ti,dra7-dma-crossbar";
167 reg = <0xb78 0xfc>;
168 #dma-cells = <1>;
169 dma-requests = <205>;
170 ti,dma-safe-map = <0>;
171 dma-masters = <&sdma>;
172 };
248948fb
PU		 173
174 edma_xbar: dma-router@c78 {
175 compatible = "ti,dra7-dma-crossbar";
176 reg = <0xc78 0x7c>;
177 #dma-cells = <2>;
178 dma-requests = <204>;
179 ti,dma-safe-map = <0>;
180 dma-masters = <&edma>;
181 };
d919501f
TK		 182 };
183
184 cm_core_aon: cm_core_aon@5000 {
185 compatible = "ti,dra7-cm-core-aon";
186 reg = <0x5000 0x2000>;
187
188 cm_core_aon_clocks: clocks {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 };
192
193 cm_core_aon_clockdomains: clockdomains {
194 };
ee6c7507
TK		 195 };
196
d919501f
TK		 197 cm_core: cm_core@8000 {
198 compatible = "ti,dra7-cm-core";
199 reg = <0x8000 0x3000>;
200
201 cm_core_clocks: clocks {
202 #address-cells = <1>;
203 #size-cells = <0>;
204 };
205
206 cm_core_clockdomains: clockdomains {
207 };
ee6c7507 208 };
d919501f 209 };
ee6c7507 210
d919501f
TK		 211 l4_wkup: l4@4ae00000 {
212 compatible = "ti,dra7-l4-wkup", "simple-bus";
213 #address-cells = <1>;
214 #size-cells = <1>;
215 ranges = <0 0x4ae00000 0x3f000>;
216
217 counter32k: counter@4000 {
218 compatible = "ti,omap-counter32k";
219 reg = <0x4000 0x40>;
220 ti,hwmods = "counter_32k";
221 };
222
223 prm: prm@6000 {
224 compatible = "ti,dra7-prm";
225 reg = <0x6000 0x3000>;
226 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
227
228 prm_clocks: clocks {
229 #address-cells = <1>;
230 #size-cells = <0>;
231 };
232
233 prm_clockdomains: clockdomains {
234 };
ee6c7507
TK		 235 };
236 };
237
18dcd79d
KVA		 238 axi@0 {
239 compatible = "simple-bus";
240 #size-cells = <1>;
241 #address-cells = <1>;
242 ranges = <0x51000000 0x51000000 0x3000
243 0x0 0x20000000 0x10000000>;
73c8f0cb 244 pcie1: pcie@51000000 {
18dcd79d
KVA		 245 compatible = "ti,dra7-pcie";
246 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
247 reg-names = "rc_dbics", "ti_conf", "config";
248 interrupts = <0 232 0x4>, <0 233 0x4>;
249 #address-cells = <3>;
250 #size-cells = <2>;
251 device_type = "pci";
252 ranges = <0x81000000 0 0 0x03000 0 0x00010000
253 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
254 #interrupt-cells = <1>;
255 num-lanes = <1>;
256 ti,hwmods = "pcie1";
257 phys = <&pcie1_phy>;
258 phy-names = "pcie-phy0";
259 interrupt-map-mask = <0 0 0 7>;
260 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
261 <0 0 0 2 &pcie1_intc 2>,
262 <0 0 0 3 &pcie1_intc 3>,
263 <0 0 0 4 &pcie1_intc 4>;
264 pcie1_intc: interrupt-controller {
265 interrupt-controller;
266 #address-cells = <0>;
267 #interrupt-cells = <1>;
268 };
269 };
270 };
271
272 axi@1 {
273 compatible = "simple-bus";
274 #size-cells = <1>;
275 #address-cells = <1>;
276 ranges = <0x51800000 0x51800000 0x3000
277 0x0 0x30000000 0x10000000>;
278 status = "disabled";
279 pcie@51000000 {
280 compatible = "ti,dra7-pcie";
281 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
282 reg-names = "rc_dbics", "ti_conf", "config";
283 interrupts = <0 355 0x4>, <0 356 0x4>;
284 #address-cells = <3>;
285 #size-cells = <2>;
286 device_type = "pci";
287 ranges = <0x81000000 0 0 0x03000 0 0x00010000
288 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
289 #interrupt-cells = <1>;
290 num-lanes = <1>;
291 ti,hwmods = "pcie2";
292 phys = <&pcie2_phy>;
293 phy-names = "pcie-phy0";
294 interrupt-map-mask = <0 0 0 7>;
295 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
296 <0 0 0 2 &pcie2_intc 2>,
297 <0 0 0 3 &pcie2_intc 3>,
298 <0 0 0 4 &pcie2_intc 4>;
299 pcie2_intc: interrupt-controller {
300 interrupt-controller;
301 #address-cells = <0>;
302 #interrupt-cells = <1>;
303 };
304 };
305 };
306
f7397edf
K		 307 bandgap: bandgap@4a0021e0 {
308 reg = <0x4a0021e0 0xc
309 0x4a00232c 0xc
310 0x4a002380 0x2c
311 0x4a0023C0 0x3c
312 0x4a002564 0x8
313 0x4a002574 0x50>;
314 compatible = "ti,dra752-bandgap";
315 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
316 #thermal-sensor-cells = <1>;
317 };
318
99639ace
SA		 319 dsp1_system: dsp_system@40d00000 {
320 compatible = "syscon";
321 reg = <0x40d00000 0x100>;
322 };
323
6e58b8f1
S		 324 sdma: dma-controller@4a056000 {
325 compatible = "ti,omap4430-sdma";
326 reg = <0x4a056000 0x1000>;
a46631c4
S		 327 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 331 #dma-cells = <1>;
08d9b327
PU		 332 dma-channels = <32>;
333 dma-requests = <127>;
6e58b8f1
S		 334 };
335
248948fb
PU		 336 edma: edma@43300000 {
337 compatible = "ti,edma3-tpcc";
338 ti,hwmods = "tpcc";
339 reg = <0x43300000 0x100000>;
340 reg-names = "edma3_cc";
341 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
344 interrupt-names = "edma3_ccint", "emda3_mperr",
345 "edma3_ccerrint";
346 dma-requests = <64>;
347 #dma-cells = <2>;
348
349 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
350
351 /*
352 * memcpy is disabled, can be enabled with:
353 * ti,edma-memcpy-channels = <20 21>;
354 * for example. Note that these channels need to be
355 * masked in the xbar as well.
356 */
357 };
358
359 edma_tptc0: tptc@43400000 {
360 compatible = "ti,edma3-tptc";
361 ti,hwmods = "tptc0";
362 reg = <0x43400000 0x100000>;
363 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
364 interrupt-names = "edma3_tcerrint";
365 };
366
367 edma_tptc1: tptc@43500000 {
368 compatible = "ti,edma3-tptc";
369 ti,hwmods = "tptc1";
370 reg = <0x43500000 0x100000>;
371 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
372 interrupt-names = "edma3_tcerrint";
373 };
374
6e58b8f1
S		 375 gpio1: gpio@4ae10000 {
376 compatible = "ti,omap4-gpio";
377 reg = <0x4ae10000 0x200>;
a46631c4 378 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 379 ti,hwmods = "gpio1";
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
e49d519c 383 #interrupt-cells = <2>;
6e58b8f1
S		 384 };
385
386 gpio2: gpio@48055000 {
387 compatible = "ti,omap4-gpio";
388 reg = <0x48055000 0x200>;
a46631c4 389 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 390 ti,hwmods = "gpio2";
391 gpio-controller;
392 #gpio-cells = <2>;
393 interrupt-controller;
e49d519c 394 #interrupt-cells = <2>;
6e58b8f1
S		 395 };
396
397 gpio3: gpio@48057000 {
398 compatible = "ti,omap4-gpio";
399 reg = <0x48057000 0x200>;
a46631c4 400 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 401 ti,hwmods = "gpio3";
402 gpio-controller;
403 #gpio-cells = <2>;
404 interrupt-controller;
e49d519c 405 #interrupt-cells = <2>;
6e58b8f1
S		 406 };
407
408 gpio4: gpio@48059000 {
409 compatible = "ti,omap4-gpio";
410 reg = <0x48059000 0x200>;
a46631c4 411 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 412 ti,hwmods = "gpio4";
413 gpio-controller;
414 #gpio-cells = <2>;
415 interrupt-controller;
e49d519c 416 #interrupt-cells = <2>;
6e58b8f1
S		 417 };
418
419 gpio5: gpio@4805b000 {
420 compatible = "ti,omap4-gpio";
421 reg = <0x4805b000 0x200>;
a46631c4 422 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 423 ti,hwmods = "gpio5";
424 gpio-controller;
425 #gpio-cells = <2>;
426 interrupt-controller;
e49d519c 427 #interrupt-cells = <2>;
6e58b8f1
S		 428 };
429
430 gpio6: gpio@4805d000 {
431 compatible = "ti,omap4-gpio";
432 reg = <0x4805d000 0x200>;
a46631c4 433 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 434 ti,hwmods = "gpio6";
435 gpio-controller;
436 #gpio-cells = <2>;
437 interrupt-controller;
e49d519c 438 #interrupt-cells = <2>;
6e58b8f1
S		 439 };
440
441 gpio7: gpio@48051000 {
442 compatible = "ti,omap4-gpio";
443 reg = <0x48051000 0x200>;
a46631c4 444 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 445 ti,hwmods = "gpio7";
446 gpio-controller;
447 #gpio-cells = <2>;
448 interrupt-controller;
e49d519c 449 #interrupt-cells = <2>;
6e58b8f1
S		 450 };
451
452 gpio8: gpio@48053000 {
453 compatible = "ti,omap4-gpio";
454 reg = <0x48053000 0x200>;
a46631c4 455 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 456 ti,hwmods = "gpio8";
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
e49d519c 460 #interrupt-cells = <2>;
6e58b8f1
S		 461 };
462
463 uart1: serial@4806a000 {
2a0e5ef6 464 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 465 reg = <0x4806a000 0x100>;
783d3186 466 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 467 ti,hwmods = "uart1";
468 clock-frequency = <48000000>;
469 status = "disabled";
3a0830de 470 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
f0199a29 471 dma-names = "tx", "rx";
6e58b8f1
S		 472 };
473
474 uart2: serial@4806c000 {
2a0e5ef6 475 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 476 reg = <0x4806c000 0x100>;
783d3186 477 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 478 ti,hwmods = "uart2";
479 clock-frequency = <48000000>;
480 status = "disabled";
3a0830de 481 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
f0199a29 482 dma-names = "tx", "rx";
6e58b8f1
S		 483 };
484
485 uart3: serial@48020000 {
2a0e5ef6 486 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 487 reg = <0x48020000 0x100>;
783d3186 488 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 489 ti,hwmods = "uart3";
490 clock-frequency = <48000000>;
491 status = "disabled";
3a0830de 492 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
f0199a29 493 dma-names = "tx", "rx";
6e58b8f1
S		 494 };
495
496 uart4: serial@4806e000 {
2a0e5ef6 497 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 498 reg = <0x4806e000 0x100>;
783d3186 499 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 500 ti,hwmods = "uart4";
501 clock-frequency = <48000000>;
502 status = "disabled";
3a0830de 503 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
f0199a29 504 dma-names = "tx", "rx";
6e58b8f1
S		 505 };
506
507 uart5: serial@48066000 {
2a0e5ef6 508 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 509 reg = <0x48066000 0x100>;
783d3186 510 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 511 ti,hwmods = "uart5";
512 clock-frequency = <48000000>;
513 status = "disabled";
3a0830de 514 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
f0199a29 515 dma-names = "tx", "rx";
6e58b8f1
S		 516 };
517
518 uart6: serial@48068000 {
2a0e5ef6 519 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 520 reg = <0x48068000 0x100>;
783d3186 521 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 522 ti,hwmods = "uart6";
523 clock-frequency = <48000000>;
524 status = "disabled";
3a0830de 525 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
f0199a29 526 dma-names = "tx", "rx";
6e58b8f1
S		 527 };
528
529 uart7: serial@48420000 {
2a0e5ef6 530 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 531 reg = <0x48420000 0x100>;
783d3186 532 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 533 ti,hwmods = "uart7";
534 clock-frequency = <48000000>;
535 status = "disabled";
536 };
537
538 uart8: serial@48422000 {
2a0e5ef6 539 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 540 reg = <0x48422000 0x100>;
783d3186 541 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 542 ti,hwmods = "uart8";
543 clock-frequency = <48000000>;
544 status = "disabled";
545 };
546
547 uart9: serial@48424000 {
2a0e5ef6 548 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 549 reg = <0x48424000 0x100>;
783d3186 550 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 551 ti,hwmods = "uart9";
552 clock-frequency = <48000000>;
553 status = "disabled";
554 };
555
556 uart10: serial@4ae2b000 {
2a0e5ef6 557 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 558 reg = <0x4ae2b000 0x100>;
783d3186 559 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 560 ti,hwmods = "uart10";
561 clock-frequency = <48000000>;
562 status = "disabled";
563 };
564
38baefb3
SA		 565 mailbox1: mailbox@4a0f4000 {
566 compatible = "ti,omap4-mailbox";
567 reg = <0x4a0f4000 0x200>;
b46a6ae6
SA		 568 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 571 ti,hwmods = "mailbox1";
24df0453 572 #mbox-cells = <1>;
38baefb3
SA		 573 ti,mbox-num-users = <3>;
574 ti,mbox-num-fifos = <8>;
575 status = "disabled";
576 };
577
578 mailbox2: mailbox@4883a000 {
579 compatible = "ti,omap4-mailbox";
580 reg = <0x4883a000 0x200>;
b46a6ae6
SA		 581 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 585 ti,hwmods = "mailbox2";
24df0453 586 #mbox-cells = <1>;
38baefb3
SA		 587 ti,mbox-num-users = <4>;
588 ti,mbox-num-fifos = <12>;
589 status = "disabled";
590 };
591
592 mailbox3: mailbox@4883c000 {
593 compatible = "ti,omap4-mailbox";
594 reg = <0x4883c000 0x200>;
b46a6ae6
SA		 595 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 599 ti,hwmods = "mailbox3";
24df0453 600 #mbox-cells = <1>;
38baefb3
SA		 601 ti,mbox-num-users = <4>;
602 ti,mbox-num-fifos = <12>;
603 status = "disabled";
604 };
605
606 mailbox4: mailbox@4883e000 {
607 compatible = "ti,omap4-mailbox";
608 reg = <0x4883e000 0x200>;
b46a6ae6
SA		 609 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 613 ti,hwmods = "mailbox4";
24df0453 614 #mbox-cells = <1>;
38baefb3
SA		 615 ti,mbox-num-users = <4>;
616 ti,mbox-num-fifos = <12>;
617 status = "disabled";
618 };
619
620 mailbox5: mailbox@48840000 {
621 compatible = "ti,omap4-mailbox";
622 reg = <0x48840000 0x200>;
b46a6ae6
SA		 623 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 627 ti,hwmods = "mailbox5";
24df0453 628 #mbox-cells = <1>;
38baefb3
SA		 629 ti,mbox-num-users = <4>;
630 ti,mbox-num-fifos = <12>;
631 status = "disabled";
632 };
633
634 mailbox6: mailbox@48842000 {
635 compatible = "ti,omap4-mailbox";
636 reg = <0x48842000 0x200>;
b46a6ae6
SA		 637 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 641 ti,hwmods = "mailbox6";
24df0453 642 #mbox-cells = <1>;
38baefb3
SA		 643 ti,mbox-num-users = <4>;
644 ti,mbox-num-fifos = <12>;
645 status = "disabled";
646 };
647
648 mailbox7: mailbox@48844000 {
649 compatible = "ti,omap4-mailbox";
650 reg = <0x48844000 0x200>;
b46a6ae6
SA		 651 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 655 ti,hwmods = "mailbox7";
24df0453 656 #mbox-cells = <1>;
38baefb3
SA		 657 ti,mbox-num-users = <4>;
658 ti,mbox-num-fifos = <12>;
659 status = "disabled";
660 };
661
662 mailbox8: mailbox@48846000 {
663 compatible = "ti,omap4-mailbox";
664 reg = <0x48846000 0x200>;
b46a6ae6
SA		 665 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 669 ti,hwmods = "mailbox8";
24df0453 670 #mbox-cells = <1>;
38baefb3
SA		 671 ti,mbox-num-users = <4>;
672 ti,mbox-num-fifos = <12>;
673 status = "disabled";
674 };
675
676 mailbox9: mailbox@4885e000 {
677 compatible = "ti,omap4-mailbox";
678 reg = <0x4885e000 0x200>;
b46a6ae6
SA		 679 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 683 ti,hwmods = "mailbox9";
24df0453 684 #mbox-cells = <1>;
38baefb3
SA		 685 ti,mbox-num-users = <4>;
686 ti,mbox-num-fifos = <12>;
687 status = "disabled";
688 };
689
690 mailbox10: mailbox@48860000 {
691 compatible = "ti,omap4-mailbox";
692 reg = <0x48860000 0x200>;
b46a6ae6
SA		 693 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 697 ti,hwmods = "mailbox10";
24df0453 698 #mbox-cells = <1>;
38baefb3
SA		 699 ti,mbox-num-users = <4>;
700 ti,mbox-num-fifos = <12>;
701 status = "disabled";
702 };
703
704 mailbox11: mailbox@48862000 {
705 compatible = "ti,omap4-mailbox";
706 reg = <0x48862000 0x200>;
b46a6ae6
SA		 707 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 711 ti,hwmods = "mailbox11";
24df0453 712 #mbox-cells = <1>;
38baefb3
SA		 713 ti,mbox-num-users = <4>;
714 ti,mbox-num-fifos = <12>;
715 status = "disabled";
716 };
717
718 mailbox12: mailbox@48864000 {
719 compatible = "ti,omap4-mailbox";
720 reg = <0x48864000 0x200>;
b46a6ae6
SA		 721 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 725 ti,hwmods = "mailbox12";
24df0453 726 #mbox-cells = <1>;
38baefb3
SA		 727 ti,mbox-num-users = <4>;
728 ti,mbox-num-fifos = <12>;
729 status = "disabled";
730 };
731
732 mailbox13: mailbox@48802000 {
733 compatible = "ti,omap4-mailbox";
734 reg = <0x48802000 0x200>;
b46a6ae6
SA		 735 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 739 ti,hwmods = "mailbox13";
24df0453 740 #mbox-cells = <1>;
38baefb3
SA		 741 ti,mbox-num-users = <4>;
742 ti,mbox-num-fifos = <12>;
743 status = "disabled";
744 };
745
6e58b8f1
S		 746 timer1: timer@4ae18000 {
747 compatible = "ti,omap5430-timer";
748 reg = <0x4ae18000 0x80>;
a46631c4 749 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 750 ti,hwmods = "timer1";
751 ti,timer-alwon;
752 };
753
754 timer2: timer@48032000 {
755 compatible = "ti,omap5430-timer";
756 reg = <0x48032000 0x80>;
a46631c4 757 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 758 ti,hwmods = "timer2";
759 };
760
761 timer3: timer@48034000 {
762 compatible = "ti,omap5430-timer";
763 reg = <0x48034000 0x80>;
a46631c4 764 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 765 ti,hwmods = "timer3";
766 };
767
768 timer4: timer@48036000 {
769 compatible = "ti,omap5430-timer";
770 reg = <0x48036000 0x80>;
a46631c4 771 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 772 ti,hwmods = "timer4";
773 };
774
775 timer5: timer@48820000 {
776 compatible = "ti,omap5430-timer";
777 reg = <0x48820000 0x80>;
a46631c4 778 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 779 ti,hwmods = "timer5";
6e58b8f1
S		 780 };
781
782 timer6: timer@48822000 {
783 compatible = "ti,omap5430-timer";
784 reg = <0x48822000 0x80>;
a46631c4 785 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 786 ti,hwmods = "timer6";
6e58b8f1
S		 787 };
788
789 timer7: timer@48824000 {
790 compatible = "ti,omap5430-timer";
791 reg = <0x48824000 0x80>;
a46631c4 792 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 793 ti,hwmods = "timer7";
6e58b8f1
S		 794 };
795
796 timer8: timer@48826000 {
797 compatible = "ti,omap5430-timer";
798 reg = <0x48826000 0x80>;
a46631c4 799 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 800 ti,hwmods = "timer8";
6e58b8f1
S		 801 };
802
803 timer9: timer@4803e000 {
804 compatible = "ti,omap5430-timer";
805 reg = <0x4803e000 0x80>;
a46631c4 806 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 807 ti,hwmods = "timer9";
808 };
809
810 timer10: timer@48086000 {
811 compatible = "ti,omap5430-timer";
812 reg = <0x48086000 0x80>;
a46631c4 813 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 814 ti,hwmods = "timer10";
815 };
816
817 timer11: timer@48088000 {
818 compatible = "ti,omap5430-timer";
819 reg = <0x48088000 0x80>;
a46631c4 820 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 821 ti,hwmods = "timer11";
6e58b8f1
S		 822 };
823
824 timer13: timer@48828000 {
825 compatible = "ti,omap5430-timer";
826 reg = <0x48828000 0x80>;
a46631c4 827 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 828 ti,hwmods = "timer13";
829 status = "disabled";
830 };
831
832 timer14: timer@4882a000 {
833 compatible = "ti,omap5430-timer";
834 reg = <0x4882a000 0x80>;
a46631c4 835 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 836 ti,hwmods = "timer14";
837 status = "disabled";
838 };
839
840 timer15: timer@4882c000 {
841 compatible = "ti,omap5430-timer";
842 reg = <0x4882c000 0x80>;
a46631c4 843 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 844 ti,hwmods = "timer15";
845 status = "disabled";
846 };
847
848 timer16: timer@4882e000 {
849 compatible = "ti,omap5430-timer";
850 reg = <0x4882e000 0x80>;
a46631c4 851 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 852 ti,hwmods = "timer16";
853 status = "disabled";
854 };
855
856 wdt2: wdt@4ae14000 {
be668835 857 compatible = "ti,omap3-wdt";
6e58b8f1 858 reg = <0x4ae14000 0x80>;
a46631c4 859 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 860 ti,hwmods = "wd_timer2";
861 };
862
dbd7c191
SA		 863 hwspinlock: spinlock@4a0f6000 {
864 compatible = "ti,omap4-hwspinlock";
865 reg = <0x4a0f6000 0x1000>;
866 ti,hwmods = "spinlock";
867 #hwlock-cells = <1>;
868 };
869
1a5fe3ca
AT		 870 dmm@4e000000 {
871 compatible = "ti,omap5-dmm";
872 reg = <0x4e000000 0x800>;
a46631c4 873 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1a5fe3ca
AT		 874 ti,hwmods = "dmm";
875 };
876
6e58b8f1
S		 877 i2c1: i2c@48070000 {
878 compatible = "ti,omap4-i2c";
879 reg = <0x48070000 0x100>;
a46631c4 880 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 881 #address-cells = <1>;
882 #size-cells = <0>;
883 ti,hwmods = "i2c1";
884 status = "disabled";
885 };
886
887 i2c2: i2c@48072000 {
888 compatible = "ti,omap4-i2c";
889 reg = <0x48072000 0x100>;
a46631c4 890 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 891 #address-cells = <1>;
892 #size-cells = <0>;
893 ti,hwmods = "i2c2";
894 status = "disabled";
895 };
896
897 i2c3: i2c@48060000 {
898 compatible = "ti,omap4-i2c";
899 reg = <0x48060000 0x100>;
a46631c4 900 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 901 #address-cells = <1>;
902 #size-cells = <0>;
903 ti,hwmods = "i2c3";
904 status = "disabled";
905 };
906
907 i2c4: i2c@4807a000 {
908 compatible = "ti,omap4-i2c";
909 reg = <0x4807a000 0x100>;
a46631c4 910 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 911 #address-cells = <1>;
912 #size-cells = <0>;
913 ti,hwmods = "i2c4";
914 status = "disabled";
915 };
916
917 i2c5: i2c@4807c000 {
918 compatible = "ti,omap4-i2c";
919 reg = <0x4807c000 0x100>;
a46631c4 920 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 921 #address-cells = <1>;
922 #size-cells = <0>;
923 ti,hwmods = "i2c5";
924 status = "disabled";
925 };
926
927 mmc1: mmc@4809c000 {
928 compatible = "ti,omap4-hsmmc";
929 reg = <0x4809c000 0x400>;
a46631c4 930 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 931 ti,hwmods = "mmc1";
932 ti,dual-volt;
933 ti,needs-special-reset;
3a0830de 934 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
6e58b8f1
S		 935 dma-names = "tx", "rx";
936 status = "disabled";
cd042fe5 937 pbias-supply = <&pbias_mmc_reg>;
6e58b8f1
S		 938 };
939
940 mmc2: mmc@480b4000 {
941 compatible = "ti,omap4-hsmmc";
942 reg = <0x480b4000 0x400>;
a46631c4 943 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 944 ti,hwmods = "mmc2";
945 ti,needs-special-reset;
3a0830de 946 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
6e58b8f1
S		 947 dma-names = "tx", "rx";
948 status = "disabled";
949 };
950
951 mmc3: mmc@480ad000 {
952 compatible = "ti,omap4-hsmmc";
953 reg = <0x480ad000 0x400>;
a46631c4 954 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 955 ti,hwmods = "mmc3";
956 ti,needs-special-reset;
3a0830de 957 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
6e58b8f1
S		 958 dma-names = "tx", "rx";
959 status = "disabled";
960 };
961
962 mmc4: mmc@480d1000 {
963 compatible = "ti,omap4-hsmmc";
964 reg = <0x480d1000 0x400>;
a46631c4 965 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 966 ti,hwmods = "mmc4";
967 ti,needs-special-reset;
3a0830de 968 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
6e58b8f1
S		 969 dma-names = "tx", "rx";
970 status = "disabled";
971 };
972
2c7e07c5
SA		 973 mmu0_dsp1: mmu@40d01000 {
974 compatible = "ti,dra7-dsp-iommu";
975 reg = <0x40d01000 0x100>;
976 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
977 ti,hwmods = "mmu0_dsp1";
978 #iommu-cells = <0>;
979 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
980 status = "disabled";
981 };
982
983 mmu1_dsp1: mmu@40d02000 {
984 compatible = "ti,dra7-dsp-iommu";
985 reg = <0x40d02000 0x100>;
986 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
987 ti,hwmods = "mmu1_dsp1";
988 #iommu-cells = <0>;
989 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
990 status = "disabled";
991 };
992
993 mmu_ipu1: mmu@58882000 {
994 compatible = "ti,dra7-iommu";
995 reg = <0x58882000 0x100>;
996 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
997 ti,hwmods = "mmu_ipu1";
998 #iommu-cells = <0>;
999 ti,iommu-bus-err-back;
1000 status = "disabled";
1001 };
1002
1003 mmu_ipu2: mmu@55082000 {
1004 compatible = "ti,dra7-iommu";
1005 reg = <0x55082000 0x100>;
1006 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1007 ti,hwmods = "mmu_ipu2";
1008 #iommu-cells = <0>;
1009 ti,iommu-bus-err-back;
1010 status = "disabled";
1011 };
1012
a1b8ee10
NM		 1013 abb_mpu: regulator-abb-mpu {
1014 compatible = "ti,abb-v3";
1015 regulator-name = "abb_mpu";
1016 #address-cells = <0>;
1017 #size-cells = <0>;
1018 clocks = <&sys_clkin1>;
1019 ti,settling-time = <50>;
1020 ti,clock-cycles = <16>;
1021
1022 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
18227346 1023 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
a1b8ee10
NM		 1024 <0x4ae0c158 0x4>;
1025 reg-names = "setup-address", "control-address",
1026 "int-address", "efuse-address",
1027 "ldo-address";
1028 ti,tranxdone-status-mask = <0x80>;
1029 /* LDOVBBMPU_FBB_MUX_CTRL */
1030 ti,ldovbb-override-mask = <0x400>;
1031 /* LDOVBBMPU_FBB_VSET_OUT */
1032 ti,ldovbb-vset-mask = <0x1F>;
1033
1034 /*
1035 * NOTE: only FBB mode used but actual vset will
1036 * determine final biasing
1037 */
1038 ti,abb_info = <
1039 /*uV ABB efuse rbb_m fbb_m vset_m*/
1040 1060000 0 0x0 0 0x02000000 0x01F00000
1041 1160000 0 0x4 0 0x02000000 0x01F00000
1042 1210000 0 0x8 0 0x02000000 0x01F00000
1043 >;
1044 };
1045
1046 abb_ivahd: regulator-abb-ivahd {
1047 compatible = "ti,abb-v3";
1048 regulator-name = "abb_ivahd";
1049 #address-cells = <0>;
1050 #size-cells = <0>;
1051 clocks = <&sys_clkin1>;
1052 ti,settling-time = <50>;
1053 ti,clock-cycles = <16>;
1054
1055 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
18227346 1056 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
a1b8ee10
NM		 1057 <0x4a002470 0x4>;
1058 reg-names = "setup-address", "control-address",
1059 "int-address", "efuse-address",
1060 "ldo-address";
1061 ti,tranxdone-status-mask = <0x40000000>;
1062 /* LDOVBBIVA_FBB_MUX_CTRL */
1063 ti,ldovbb-override-mask = <0x400>;
1064 /* LDOVBBIVA_FBB_VSET_OUT */
1065 ti,ldovbb-vset-mask = <0x1F>;
1066
1067 /*
1068 * NOTE: only FBB mode used but actual vset will
1069 * determine final biasing
1070 */
1071 ti,abb_info = <
1072 /*uV ABB efuse rbb_m fbb_m vset_m*/
1073 1055000 0 0x0 0 0x02000000 0x01F00000
1074 1150000 0 0x4 0 0x02000000 0x01F00000
1075 1250000 0 0x8 0 0x02000000 0x01F00000
1076 >;
1077 };
1078
1079 abb_dspeve: regulator-abb-dspeve {
1080 compatible = "ti,abb-v3";
1081 regulator-name = "abb_dspeve";
1082 #address-cells = <0>;
1083 #size-cells = <0>;
1084 clocks = <&sys_clkin1>;
1085 ti,settling-time = <50>;
1086 ti,clock-cycles = <16>;
1087
1088 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
18227346 1089 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
a1b8ee10
NM		 1090 <0x4a00246c 0x4>;
1091 reg-names = "setup-address", "control-address",
1092 "int-address", "efuse-address",
1093 "ldo-address";
1094 ti,tranxdone-status-mask = <0x20000000>;
1095 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1096 ti,ldovbb-override-mask = <0x400>;
1097 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1098 ti,ldovbb-vset-mask = <0x1F>;
1099
1100 /*
1101 * NOTE: only FBB mode used but actual vset will
1102 * determine final biasing
1103 */
1104 ti,abb_info = <
1105 /*uV ABB efuse rbb_m fbb_m vset_m*/
1106 1055000 0 0x0 0 0x02000000 0x01F00000
1107 1150000 0 0x4 0 0x02000000 0x01F00000
1108 1250000 0 0x8 0 0x02000000 0x01F00000
1109 >;
1110 };
1111
1112 abb_gpu: regulator-abb-gpu {
1113 compatible = "ti,abb-v3";
1114 regulator-name = "abb_gpu";
1115 #address-cells = <0>;
1116 #size-cells = <0>;
1117 clocks = <&sys_clkin1>;
1118 ti,settling-time = <50>;
1119 ti,clock-cycles = <16>;
1120
1121 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
18227346 1122 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
a1b8ee10
NM		 1123 <0x4ae0c154 0x4>;
1124 reg-names = "setup-address", "control-address",
1125 "int-address", "efuse-address",
1126 "ldo-address";
1127 ti,tranxdone-status-mask = <0x10000000>;
1128 /* LDOVBBGPU_FBB_MUX_CTRL */
1129 ti,ldovbb-override-mask = <0x400>;
1130 /* LDOVBBGPU_FBB_VSET_OUT */
1131 ti,ldovbb-vset-mask = <0x1F>;
1132
1133 /*
1134 * NOTE: only FBB mode used but actual vset will
1135 * determine final biasing
1136 */
1137 ti,abb_info = <
1138 /*uV ABB efuse rbb_m fbb_m vset_m*/
1139 1090000 0 0x0 0 0x02000000 0x01F00000
1140 1210000 0 0x4 0 0x02000000 0x01F00000
1141 1280000 0 0x8 0 0x02000000 0x01F00000
1142 >;
1143 };
1144
6e58b8f1
S		 1145 mcspi1: spi@48098000 {
1146 compatible = "ti,omap4-mcspi";
1147 reg = <0x48098000 0x200>;
a46631c4 1148 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 1149 #address-cells = <1>;
1150 #size-cells = <0>;
1151 ti,hwmods = "mcspi1";
1152 ti,spi-num-cs = <4>;
3a0830de
PU		 1153 dmas = <&sdma_xbar 35>,
1154 <&sdma_xbar 36>,
1155 <&sdma_xbar 37>,
1156 <&sdma_xbar 38>,
1157 <&sdma_xbar 39>,
1158 <&sdma_xbar 40>,
1159 <&sdma_xbar 41>,
1160 <&sdma_xbar 42>;
6e58b8f1
S		 1161 dma-names = "tx0", "rx0", "tx1", "rx1",
1162 "tx2", "rx2", "tx3", "rx3";
1163 status = "disabled";
1164 };
1165
1166 mcspi2: spi@4809a000 {
1167 compatible = "ti,omap4-mcspi";
1168 reg = <0x4809a000 0x200>;
a46631c4 1169 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 1170 #address-cells = <1>;
1171 #size-cells = <0>;
1172 ti,hwmods = "mcspi2";
1173 ti,spi-num-cs = <2>;
3a0830de
PU		 1174 dmas = <&sdma_xbar 43>,
1175 <&sdma_xbar 44>,
1176 <&sdma_xbar 45>,
1177 <&sdma_xbar 46>;
6e58b8f1
S		 1178 dma-names = "tx0", "rx0", "tx1", "rx1";
1179 status = "disabled";
1180 };
1181
1182 mcspi3: spi@480b8000 {
1183 compatible = "ti,omap4-mcspi";
1184 reg = <0x480b8000 0x200>;
a46631c4 1185 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188 ti,hwmods = "mcspi3";
1189 ti,spi-num-cs = <2>;
3a0830de 1190 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
6e58b8f1
S		 1191 dma-names = "tx0", "rx0";
1192 status = "disabled";
1193 };
1194
1195 mcspi4: spi@480ba000 {
1196 compatible = "ti,omap4-mcspi";
1197 reg = <0x480ba000 0x200>;
a46631c4 1198 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 1199 #address-cells = <1>;
1200 #size-cells = <0>;
1201 ti,hwmods = "mcspi4";
1202 ti,spi-num-cs = <1>;
3a0830de 1203 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
6e58b8f1
S		 1204 dma-names = "tx0", "rx0";
1205 status = "disabled";
1206 };
dc2dd5b8
SP		 1207
1208 qspi: qspi@4b300000 {
1209 compatible = "ti,dra7xxx-qspi";
1929d0b5
V		 1210 reg = <0x4b300000 0x100>,
1211 <0x5c000000 0x4000000>;
1212 reg-names = "qspi_base", "qspi_mmap";
1213 syscon-chipselects = <&scm_conf 0x558>;
dc2dd5b8
SP		 1214 #address-cells = <1>;
1215 #size-cells = <0>;
1216 ti,hwmods = "qspi";
1217 clocks = <&qspi_gfclk_div>;
1218 clock-names = "fck";
1219 num-cs = <4>;
a46631c4 1220 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
dc2dd5b8
SP		 1221 status = "disabled";
1222 };
7be80569 1223
7be80569
B		 1224 /* OCP2SCP3 */
1225 ocp2scp@4a090000 {
1226 compatible = "ti,omap-ocp2scp";
1227 #address-cells = <1>;
1228 #size-cells = <1>;
1229 ranges;
1230 reg = <0x4a090000 0x20>;
1231 ti,hwmods = "ocp2scp3";
1232 sata_phy: phy@4A096000 {
1233 compatible = "ti,phy-pipe3-sata";
1234 reg = <0x4A096000 0x80>, /* phy_rx */
1235 <0x4A096400 0x64>, /* phy_tx */
1236 <0x4A096800 0x40>; /* pll_ctrl */
1237 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
2338c76a 1238 syscon-phy-power = <&scm_conf 0x374>;
773c5a0f
RQ		 1239 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1240 clock-names = "sysclk", "refclk";
257d5d9a 1241 syscon-pllreset = <&scm_conf 0x3fc>;
7be80569
B		 1242 #phy-cells = <0>;
1243 };
692df0ef
KVA		 1244
1245 pcie1_phy: pciephy@4a094000 {
1246 compatible = "ti,phy-pipe3-pcie";
1247 reg = <0x4a094000 0x80>, /* phy_rx */
1248 <0x4a094400 0x64>; /* phy_tx */
1249 reg-names = "phy_rx", "phy_tx";
6921e58b
KVA		 1250 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1251 syscon-pcs = <&scm_conf_pcie 0x10>;
692df0ef
KVA		 1252 clocks = <&dpll_pcie_ref_ck>,
1253 <&dpll_pcie_ref_m2ldo_ck>,
1254 <&optfclk_pciephy1_32khz>,
1255 <&optfclk_pciephy1_clk>,
1256 <&optfclk_pciephy1_div_clk>,
6921e58b
KVA		 1257 <&optfclk_pciephy_div>,
1258 <&sys_clkin1>;
692df0ef
KVA		 1259 clock-names = "dpll_ref", "dpll_ref_m2",
1260 "wkupclk", "refclk",
6921e58b 1261 "div-clk", "phy-div", "sysclk";
692df0ef 1262 #phy-cells = <0>;
692df0ef
KVA		 1263 };
1264
1265 pcie2_phy: pciephy@4a095000 {
1266 compatible = "ti,phy-pipe3-pcie";
1267 reg = <0x4a095000 0x80>, /* phy_rx */
1268 <0x4a095400 0x64>; /* phy_tx */
1269 reg-names = "phy_rx", "phy_tx";
6921e58b
KVA		 1270 syscon-phy-power = <&scm_conf_pcie 0x20>;
1271 syscon-pcs = <&scm_conf_pcie 0x10>;
692df0ef
KVA		 1272 clocks = <&dpll_pcie_ref_ck>,
1273 <&dpll_pcie_ref_m2ldo_ck>,
1274 <&optfclk_pciephy2_32khz>,
1275 <&optfclk_pciephy2_clk>,
1276 <&optfclk_pciephy2_div_clk>,
6921e58b
KVA		 1277 <&optfclk_pciephy_div>,
1278 <&sys_clkin1>;
692df0ef
KVA		 1279 clock-names = "dpll_ref", "dpll_ref_m2",
1280 "wkupclk", "refclk",
6921e58b 1281 "div-clk", "phy-div", "sysclk";
692df0ef 1282 #phy-cells = <0>;
692df0ef
KVA		 1283 status = "disabled";
1284 };
7be80569
B		 1285 };
1286
1287 sata: sata@4a141100 {
1288 compatible = "snps,dwc-ahci";
1289 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
a46631c4 1290 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
7be80569
B		 1291 phys = <&sata_phy>;
1292 phy-names = "sata-phy";
1293 clocks = <&sata_ref_clk>;
1294 ti,hwmods = "sata";
1295 };
fbf3e552 1296
00edd317 1297 rtc: rtc@48838000 {
bc078316
LV		 1298 compatible = "ti,am3352-rtc";
1299 reg = <0x48838000 0x100>;
1300 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1302 ti,hwmods = "rtcss";
1303 clocks = <&sys_32k_ck>;
1304 };
1305
fbf3e552
RQ		 1306 /* OCP2SCP1 */
1307 ocp2scp@4a080000 {
1308 compatible = "ti,omap-ocp2scp";
1309 #address-cells = <1>;
1310 #size-cells = <1>;
1311 ranges;
1312 reg = <0x4a080000 0x20>;
1313 ti,hwmods = "ocp2scp1";
1314
1315 usb2_phy1: phy@4a084000 {
1316 compatible = "ti,omap-usb2";
1317 reg = <0x4a084000 0x400>;
2338c76a 1318 syscon-phy-power = <&scm_conf 0x300>;
fbf3e552
RQ		 1319 clocks = <&usb_phy1_always_on_clk32k>,
1320 <&usb_otg_ss1_refclk960m>;
1321 clock-names = "wkupclk",
1322 "refclk";
1323 #phy-cells = <0>;
1324 };
1325
1326 usb2_phy2: phy@4a085000 {
4b4f52ed
KVA		 1327 compatible = "ti,dra7x-usb2-phy2",
1328 "ti,omap-usb2";
fbf3e552 1329 reg = <0x4a085000 0x400>;
2338c76a 1330 syscon-phy-power = <&scm_conf 0xe74>;
fbf3e552
RQ		 1331 clocks = <&usb_phy2_always_on_clk32k>,
1332 <&usb_otg_ss2_refclk960m>;
1333 clock-names = "wkupclk",
1334 "refclk";
1335 #phy-cells = <0>;
1336 };
1337
1338 usb3_phy1: phy@4a084400 {
1339 compatible = "ti,omap-usb3";
1340 reg = <0x4a084400 0x80>,
1341 <0x4a084800 0x64>,
1342 <0x4a084c00 0x40>;
1343 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
2338c76a 1344 syscon-phy-power = <&scm_conf 0x370>;
fbf3e552
RQ		 1345 clocks = <&usb_phy3_always_on_clk32k>,
1346 <&sys_clkin1>,
1347 <&usb_otg_ss1_refclk960m>;
1348 clock-names = "wkupclk",
1349 "sysclk",
1350 "refclk";
1351 #phy-cells = <0>;
1352 };
1353 };
1354
4f6dec70 1355 omap_dwc3_1: omap_dwc3_1@48880000 {
fbf3e552
RQ		 1356 compatible = "ti,dwc3";
1357 ti,hwmods = "usb_otg_ss1";
1358 reg = <0x48880000 0x10000>;
a46631c4 1359 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1360 #address-cells = <1>;
1361 #size-cells = <1>;
1362 utmi-mode = <2>;
1363 ranges;
1364 usb1: usb@48890000 {
1365 compatible = "snps,dwc3";
1366 reg = <0x48890000 0x17000>;
964927f3
RQ		 1367 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1370 interrupt-names = "peripheral",
1371 "host",
1372 "otg";
fbf3e552
RQ		 1373 phys = <&usb2_phy1>, <&usb3_phy1>;
1374 phy-names = "usb2-phy", "usb3-phy";
fbf3e552
RQ		 1375 maximum-speed = "super-speed";
1376 dr_mode = "otg";
8c606735
FB		 1377 snps,dis_u3_susphy_quirk;
1378 snps,dis_u2_susphy_quirk;
fbf3e552
RQ		 1379 };
1380 };
1381
4f6dec70 1382 omap_dwc3_2: omap_dwc3_2@488c0000 {
fbf3e552
RQ		 1383 compatible = "ti,dwc3";
1384 ti,hwmods = "usb_otg_ss2";
1385 reg = <0x488c0000 0x10000>;
a46631c4 1386 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1387 #address-cells = <1>;
1388 #size-cells = <1>;
1389 utmi-mode = <2>;
1390 ranges;
1391 usb2: usb@488d0000 {
1392 compatible = "snps,dwc3";
1393 reg = <0x488d0000 0x17000>;
964927f3
RQ		 1394 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1397 interrupt-names = "peripheral",
1398 "host",
1399 "otg";
fbf3e552
RQ		 1400 phys = <&usb2_phy2>;
1401 phy-names = "usb2-phy";
fbf3e552
RQ		 1402 maximum-speed = "high-speed";
1403 dr_mode = "otg";
8c606735
FB		 1404 snps,dis_u3_susphy_quirk;
1405 snps,dis_u2_susphy_quirk;
fbf3e552
RQ		 1406 };
1407 };
1408
1409 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
4f6dec70 1410 omap_dwc3_3: omap_dwc3_3@48900000 {
fbf3e552
RQ		 1411 compatible = "ti,dwc3";
1412 ti,hwmods = "usb_otg_ss3";
1413 reg = <0x48900000 0x10000>;
a46631c4 1414 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1415 #address-cells = <1>;
1416 #size-cells = <1>;
1417 utmi-mode = <2>;
1418 ranges;
1419 status = "disabled";
1420 usb3: usb@48910000 {
1421 compatible = "snps,dwc3";
1422 reg = <0x48910000 0x17000>;
964927f3
RQ		 1423 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1425 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1426 interrupt-names = "peripheral",
1427 "host",
1428 "otg";
fbf3e552
RQ		 1429 maximum-speed = "high-speed";
1430 dr_mode = "otg";
8c606735
FB		 1431 snps,dis_u3_susphy_quirk;
1432 snps,dis_u2_susphy_quirk;
fbf3e552
RQ		 1433 };
1434 };
1435
ff66a3c8
MS		 1436 elm: elm@48078000 {
1437 compatible = "ti,am3352-elm";
1438 reg = <0x48078000 0xfc0>; /* device IO registers */
a46631c4 1439 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
ff66a3c8
MS		 1440 ti,hwmods = "elm";
1441 status = "disabled";
1442 };
1443
1444 gpmc: gpmc@50000000 {
1445 compatible = "ti,am3352-gpmc";
1446 ti,hwmods = "gpmc";
1447 reg = <0x50000000 0x37c>; /* device IO registers */
a46631c4 1448 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
ff66a3c8
MS		 1449 gpmc,num-cs = <8>;
1450 gpmc,num-waitpins = <2>;
1451 #address-cells = <2>;
1452 #size-cells = <1>;
488f270d
RQ		 1453 interrupt-controller;
1454 #interrupt-cells = <2>;
ff66a3c8
MS		 1455 status = "disabled";
1456 };
2ca0945f
PU		 1457
1458 atl: atl@4843c000 {
1459 compatible = "ti,dra7-atl";
1460 reg = <0x4843c000 0x3ff>;
1461 ti,hwmods = "atl";
1462 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1463 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1464 clocks = <&atl_gfclk_mux>;
1465 clock-names = "fck";
1466 status = "disabled";
1467 };
412a9bbd 1468
026d4d6d
PU		 1469 mcasp3: mcasp@48468000 {
1470 compatible = "ti,dra7-mcasp-audio";
1471 ti,hwmods = "mcasp3";
0c92de2c
MLC		 1472 reg = <0x48468000 0x2000>,
1473 <0x46000000 0x1000>;
1474 reg-names = "mpu","dat";
026d4d6d
PU		 1475 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1477 interrupt-names = "tx", "rx";
0c92de2c 1478 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
026d4d6d 1479 dma-names = "tx", "rx";
bf05c2c2
PU		 1480 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1481 clock-names = "fck", "ahclkx";
026d4d6d
PU		 1482 status = "disabled";
1483 };
1484
783d3186 1485 crossbar_mpu: crossbar@4a002a48 {
a46631c4
S		 1486 compatible = "ti,irq-crossbar";
1487 reg = <0x4a002a48 0x130>;
783d3186 1488 interrupt-controller;
7136d457 1489 interrupt-parent = <&wakeupgen>;
783d3186 1490 #interrupt-cells = <3>;
a46631c4
S		 1491 ti,max-irqs = <160>;
1492 ti,max-crossbar-sources = <MAX_SOURCES>;
1493 ti,reg-size = <2>;
1494 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1495 ti,irqs-skip = <10 133 139 140>;
1496 ti,irqs-safe-map = <0>;
1497 };
ef9c5b69 1498
c263a5b8 1499 mac: ethernet@48484000 {
e2095318 1500 compatible = "ti,dra7-cpsw","ti,cpsw";
ef9c5b69
M		 1501 ti,hwmods = "gmac";
1502 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1503 clock-names = "fck", "cpts";
1504 cpdma_channels = <8>;
1505 ale_entries = <1024>;
1506 bd_ram_size = <0x2000>;
1507 no_bd_ram = <0>;
1508 rx_descs = <64>;
1509 mac_control = <0x20>;
1510 slaves = <2>;
1511 active_slave = <0>;
1512 cpts_clock_mult = <0x80000000>;
1513 cpts_clock_shift = <29>;
1514 reg = <0x48484000 0x1000
1515 0x48485200 0x2E00>;
1516 #address-cells = <1>;
1517 #size-cells = <1>;
0f514e69
M		 1518
1519 /*
1520 * Do not allow gating of cpsw clock as workaround
1521 * for errata i877. Keeping internal clock disabled
1522 * causes the device switching characteristics
1523 * to degrade over time and eventually fail to meet
1524 * the data manual delay time/skew specs.
1525 */
1526 ti,no-idle;
1527
ef9c5b69
M		 1528 /*
1529 * rx_thresh_pend
1530 * rx_pend
1531 * tx_pend
1532 * misc_pend
1533 */
1534 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1538 ranges;
a084e13e 1539 syscon = <&scm_conf>;
ef9c5b69
M		 1540 status = "disabled";
1541
1542 davinci_mdio: mdio@48485000 {
1543 compatible = "ti,davinci_mdio";
1544 #address-cells = <1>;
1545 #size-cells = <0>;
1546 ti,hwmods = "davinci_mdio";
1547 bus_freq = <1000000>;
1548 reg = <0x48485000 0x100>;
1549 };
1550
1551 cpsw_emac0: slave@48480200 {
1552 /* Filled in by U-Boot */
1553 mac-address = [ 00 00 00 00 00 00 ];
1554 };
1555
1556 cpsw_emac1: slave@48480300 {
1557 /* Filled in by U-Boot */
1558 mac-address = [ 00 00 00 00 00 00 ];
1559 };
1560
1561 phy_sel: cpsw-phy-sel@4a002554 {
1562 compatible = "ti,dra7xx-cpsw-phy-sel";
1563 reg= <0x4a002554 0x4>;
1564 reg-names = "gmii-sel";
1565 };
1566 };
1567
9ec49b9f
RQ		 1568 dcan1: can@481cc000 {
1569 compatible = "ti,dra7-d_can";
1570 ti,hwmods = "dcan1";
1571 reg = <0x4ae3c000 0x2000>;
d919501f 1572 syscon-raminit = <&scm_conf 0x558 0>;
9ec49b9f
RQ		 1573 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1574 clocks = <&dcan1_sys_clk_mux>;
1575 status = "disabled";
1576 };
1577
1578 dcan2: can@481d0000 {
1579 compatible = "ti,dra7-d_can";
1580 ti,hwmods = "dcan2";
1581 reg = <0x48480000 0x2000>;
d919501f 1582 syscon-raminit = <&scm_conf 0x558 1>;
9ec49b9f
RQ		 1583 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1584 clocks = <&sys_clkin1>;
1585 status = "disabled";
1586 };
95c1cd13
TV		 1587
1588 dss: dss@58000000 {
1589 compatible = "ti,dra7-dss";
1590 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1591 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1592 status = "disabled";
1593 ti,hwmods = "dss_core";
1594 /* CTRL_CORE_DSS_PLL_CONTROL */
1595 syscon-pll-ctrl = <&scm_conf 0x538>;
1596 #address-cells = <1>;
1597 #size-cells = <1>;
1598 ranges;
1599
1600 dispc@58001000 {
1601 compatible = "ti,dra7-dispc";
1602 reg = <0x58001000 0x1000>;
1603 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1604 ti,hwmods = "dss_dispc";
1605 clocks = <&dss_dss_clk>;
1606 clock-names = "fck";
1607 /* CTRL_CORE_SMA_SW_1 */
1608 syscon-pol = <&scm_conf 0x534>;
1609 };
1610
1611 hdmi: encoder@58060000 {
1612 compatible = "ti,dra7-hdmi";
1613 reg = <0x58040000 0x200>,
1614 <0x58040200 0x80>,
1615 <0x58040300 0x80>,
1616 <0x58060000 0x19000>;
1617 reg-names = "wp", "pll", "phy", "core";
1618 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1619 status = "disabled";
1620 ti,hwmods = "dss_hdmi";
1621 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1622 clock-names = "fck", "sys_clk";
1623 };
1624 };
6e58b8f1 1625 };
f7397edf
K		 1626
1627 thermal_zones: thermal-zones {
1628 #include "omap4-cpu-thermal.dtsi"
1629 #include "omap5-gpu-thermal.dtsi"
1630 #include "omap5-core-thermal.dtsi"
667f2599
K		 1631 #include "dra7-dspeve-thermal.dtsi"
1632 #include "dra7-iva-thermal.dtsi"
f7397edf
K		 1633 };
1634
1635};
1636
1637&cpu_thermal {
1638 polling-delay = <500>; /* milliseconds */
6e58b8f1 1639};
ee6c7507
TK		 1640
1641/include/ "dra7xx-clocks.dtsi"
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