[mirror_ubuntu-focal-kernel.git] / arch / arm / boot / dts / dra72-evm-revc.dts

/*
 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include "dra72-evm-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>

/ {
	model = "TI DRA722 Rev C EVM";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
	};

	evm_1v8_sw: fixedregulator-evm_1v8 {
		compatible = "regulator-fixed";
		regulator-name = "evm_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&smps4_reg>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&i2c1 {
	tps65917: tps65917@58 {
		reg = <0x58>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
	};
};

#include "dra72-evm-tps65917.dtsi"

&ldo2_reg {
	/* LDO2_OUT --> VDDA_1V8_PHY2 */
	regulator-always-on;
	regulator-boot-on;
};

&hdmi {
	vdda-supply = <&ldo2_reg>;
};

&pcf_gpio_21 {
	interrupt-parent = <&gpio3>;
	interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
};

&mac {
	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
		     <&pcf_hdmi 9 GPIO_ACTIVE_LOW>,	/* P11 */
		     <&pcf_hdmi 10 GPIO_ACTIVE_LOW>;	/* P12 */
	dual_emac;
};

&cpsw_emac0 {
	phy-handle = <&dp83867_0>;
	phy-mode = "rgmii-id";
	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	phy-handle = <&dp83867_1>;
	phy-mode = "rgmii-id";
	dual_emac_res_vlan = <2>;
};

&davinci_mdio {
	dp83867_0: ethernet-phy@2 {
		reg = <2>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
		ti,min-output-impedance;
		interrupt-parent = <&gpio6>;
		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
		ti,dp83867-rxctrl-strap-quirk;
	};

	dp83867_1: ethernet-phy@3 {
		reg = <3>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
		ti,min-output-impedance;
		interrupt-parent = <&gpio6>;
		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
		ti,dp83867-rxctrl-strap-quirk;
	};
};

&mmc1 {
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_sdr50>;
	pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
	vqmmc-supply = <&ldo1_reg>;
};

&mmc2 {
	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
	vmmc-supply = <&evm_1v8_sw>;
};
Commit	Line	Data
a4240d3a NM	1	/*
	2	* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8	#include "dra72-evm-common.dtsi"
17e22528	9	#include "dra72x-mmc-iodelay.dtsi"
a4240d3a NM	10	#include <dt-bindings/net/ti-dp83867.h>
	11
	12	/ {
	13	model = "TI DRA722 Rev C EVM";
	14
5c4d9f0d	15	memory@0 {
a4240d3a NM	16	device_type = "memory";
	17	reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
	18	};
0798af54 KVA	19
	20	evm_1v8_sw: fixedregulator-evm_1v8 {
	21	compatible = "regulator-fixed";
	22	regulator-name = "evm_1v8";
	23	regulator-min-microvolt = <1800000>;
	24	regulator-max-microvolt = <1800000>;
	25	vin-supply = <&smps4_reg>;
	26	regulator-always-on;
	27	regulator-boot-on;
	28	};
a4240d3a NM	29	};
a4240d3a NM	30
5d080aa3 LV	31	&i2c1 {
	32	tps65917: tps65917@58 {
	33	reg = <0x58>;
	34
	35	interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
a4240d3a NM	36	};
	37	};
	38
5d080aa3 LV	39	#include "dra72-evm-tps65917.dtsi"
	40
	41	&ldo2_reg {
	42	/* LDO2_OUT --> VDDA_1V8_PHY2 */
	43	regulator-always-on;
	44	regulator-boot-on;
	45	};
	46
a4240d3a NM	47	&hdmi {
	48	vdda-supply = <&ldo2_reg>;
	49	};
	50
	51	&pcf_gpio_21 {
	52	interrupt-parent = <&gpio3>;
	53	interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
	54	};
	55
	56	&mac {
	57	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
	58	<&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
	59	<&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
	60	dual_emac;
	61	};
	62
	63	&cpsw_emac0 {
f1934c90	64	phy-handle = <&dp83867_0>;
a4240d3a NM	65	phy-mode = "rgmii-id";
	66	dual_emac_res_vlan = <1>;
	67	};
	68
	69	&cpsw_emac1 {
f1934c90	70	phy-handle = <&dp83867_1>;
a4240d3a NM	71	phy-mode = "rgmii-id";
	72	dual_emac_res_vlan = <2>;
	73	};
	74
	75	&davinci_mdio {
	76	dp83867_0: ethernet-phy@2 {
	77	reg = <2>;
1f065544 M	78	ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
1f065544 M	79	ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
a4240d3a	80	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
b76db38c	81	ti,min-output-impedance;
fad51b08 GS	82	interrupt-parent = <&gpio6>;
fad51b08 GS	83	interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
83f51f06	84	ti,dp83867-rxctrl-strap-quirk;
a4240d3a NM	85	};
	86
	87	dp83867_1: ethernet-phy@3 {
	88	reg = <3>;
1f065544 M	89	ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
1f065544 M	90	ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
a4240d3a	91	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
fad51b08 GS	92	ti,min-output-impedance;
	93	interrupt-parent = <&gpio6>;
	94	interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
83f51f06	95	ti,dp83867-rxctrl-strap-quirk;
a4240d3a NM	96	};
a4240d3a NM	97	};
0798af54	98
eb86fb6e	99	&mmc1 {
17e22528 KVA	100	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
	101	pinctrl-0 = <&mmc1_pins_default>;
	102	pinctrl-1 = <&mmc1_pins_hs>;
	103	pinctrl-2 = <&mmc1_pins_sdr12>;
	104	pinctrl-3 = <&mmc1_pins_sdr25>;
	105	pinctrl-4 = <&mmc1_pins_sdr50>;
	106	pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
	107	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
eb86fb6e KVA	108	vqmmc-supply = <&ldo1_reg>;
	109	};
	110
0798af54	111	&mmc2 {
17e22528 KVA	112	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
	113	pinctrl-0 = <&mmc2_pins_default>;
	114	pinctrl-1 = <&mmc2_pins_hs>;
	115	pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
	116	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
0798af54 KVA	117	vmmc-supply = <&evm_1v8_sw>;
0798af54 KVA	118	};