[mirror_ubuntu-focal-kernel.git] / arch / arm / boot / dts / dra72-evm-revc.dts

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
 */
#include "dra72-evm-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>

/ {
	model = "TI DRA722 Rev C EVM";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
	};

	evm_1v8_sw: fixedregulator-evm_1v8 {
		compatible = "regulator-fixed";
		regulator-name = "evm_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&smps4_reg>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&i2c1 {
	tps65917: tps65917@58 {
		reg = <0x58>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
	};
};

#include "dra72-evm-tps65917.dtsi"

&ldo2_reg {
	/* LDO2_OUT --> VDDA_1V8_PHY2 */
	regulator-always-on;
	regulator-boot-on;
};

&hdmi {
	vdda-supply = <&ldo2_reg>;
};

&pcf_gpio_21 {
	interrupt-parent = <&gpio3>;
	interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
};

&mac {
	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
		     <&pcf_hdmi 9 GPIO_ACTIVE_LOW>,	/* P11 */
		     <&pcf_hdmi 10 GPIO_ACTIVE_LOW>;	/* P12 */
	dual_emac;
};

&cpsw_emac0 {
	phy-handle = <&dp83867_0>;
	phy-mode = "rgmii-id";
	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	phy-handle = <&dp83867_1>;
	phy-mode = "rgmii-id";
	dual_emac_res_vlan = <2>;
};

&davinci_mdio {
	dp83867_0: ethernet-phy@2 {
		reg = <2>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
		ti,min-output-impedance;
		interrupt-parent = <&gpio6>;
		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
		ti,dp83867-rxctrl-strap-quirk;
	};

	dp83867_1: ethernet-phy@3 {
		reg = <3>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
		ti,min-output-impedance;
		interrupt-parent = <&gpio6>;
		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
		ti,dp83867-rxctrl-strap-quirk;
	};
};

&mmc1 {
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_sdr50>;
	pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
	vqmmc-supply = <&ldo1_reg>;
};

&mmc2 {
	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
	vmmc-supply = <&evm_1v8_sw>;
};
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
a4240d3a NM	2	/*
a4240d3a NM	3	* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
a4240d3a NM	4	*/
a4240d3a NM	5	#include "dra72-evm-common.dtsi"
17e22528	6	#include "dra72x-mmc-iodelay.dtsi"
a4240d3a NM	7	#include <dt-bindings/net/ti-dp83867.h>
	8
	9	/ {
	10	model = "TI DRA722 Rev C EVM";
	11
5c4d9f0d	12	memory@0 {
a4240d3a NM	13	device_type = "memory";
	14	reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
	15	};
0798af54 KVA	16
	17	evm_1v8_sw: fixedregulator-evm_1v8 {
	18	compatible = "regulator-fixed";
	19	regulator-name = "evm_1v8";
	20	regulator-min-microvolt = <1800000>;
	21	regulator-max-microvolt = <1800000>;
	22	vin-supply = <&smps4_reg>;
	23	regulator-always-on;
	24	regulator-boot-on;
	25	};
a4240d3a NM	26	};
a4240d3a NM	27
5d080aa3 LV	28	&i2c1 {
	29	tps65917: tps65917@58 {
	30	reg = <0x58>;
	31
	32	interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
a4240d3a NM	33	};
	34	};
	35
5d080aa3 LV	36	#include "dra72-evm-tps65917.dtsi"
	37
	38	&ldo2_reg {
	39	/* LDO2_OUT --> VDDA_1V8_PHY2 */
	40	regulator-always-on;
	41	regulator-boot-on;
	42	};
	43
a4240d3a NM	44	&hdmi {
	45	vdda-supply = <&ldo2_reg>;
	46	};
	47
	48	&pcf_gpio_21 {
	49	interrupt-parent = <&gpio3>;
	50	interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
	51	};
	52
	53	&mac {
	54	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
	55	<&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
	56	<&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
	57	dual_emac;
	58	};
	59
	60	&cpsw_emac0 {
f1934c90	61	phy-handle = <&dp83867_0>;
a4240d3a NM	62	phy-mode = "rgmii-id";
	63	dual_emac_res_vlan = <1>;
	64	};
	65
	66	&cpsw_emac1 {
f1934c90	67	phy-handle = <&dp83867_1>;
a4240d3a NM	68	phy-mode = "rgmii-id";
	69	dual_emac_res_vlan = <2>;
	70	};
	71
	72	&davinci_mdio {
	73	dp83867_0: ethernet-phy@2 {
	74	reg = <2>;
1f065544 M	75	ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
1f065544 M	76	ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
a4240d3a	77	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
b76db38c	78	ti,min-output-impedance;
fad51b08 GS	79	interrupt-parent = <&gpio6>;
fad51b08 GS	80	interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
83f51f06	81	ti,dp83867-rxctrl-strap-quirk;
a4240d3a NM	82	};
	83
	84	dp83867_1: ethernet-phy@3 {
	85	reg = <3>;
1f065544 M	86	ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
1f065544 M	87	ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
a4240d3a	88	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
fad51b08 GS	89	ti,min-output-impedance;
	90	interrupt-parent = <&gpio6>;
	91	interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
83f51f06	92	ti,dp83867-rxctrl-strap-quirk;
a4240d3a NM	93	};
a4240d3a NM	94	};
0798af54	95
eb86fb6e	96	&mmc1 {
17e22528 KVA	97	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
	98	pinctrl-0 = <&mmc1_pins_default>;
	99	pinctrl-1 = <&mmc1_pins_hs>;
	100	pinctrl-2 = <&mmc1_pins_sdr12>;
	101	pinctrl-3 = <&mmc1_pins_sdr25>;
	102	pinctrl-4 = <&mmc1_pins_sdr50>;
	103	pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
	104	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
eb86fb6e KVA	105	vqmmc-supply = <&ldo1_reg>;
	106	};
	107
0798af54	108	&mmc2 {
17e22528 KVA	109	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
	110	pinctrl-0 = <&mmc2_pins_default>;
	111	pinctrl-1 = <&mmc2_pins_hs>;
	112	pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
	113	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
0798af54 KVA	114	vmmc-supply = <&evm_1v8_sw>;
0798af54 KVA	115	};