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38b248db RN |
1 | /* |
2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | /dts-v1/; | |
9 | ||
10 | #include "dra72x.dtsi" | |
f56de327 | 11 | #include <dt-bindings/gpio/gpio.h> |
38b248db RN |
12 | |
13 | / { | |
14 | model = "TI DRA722"; | |
15 | compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; | |
16 | ||
17 | memory { | |
18 | device_type = "memory"; | |
19 | reg = <0x80000000 0x40000000>; /* 1024 MB */ | |
20 | }; | |
5b434d7e | 21 | |
fadf0d0b TV |
22 | aliases { |
23 | display0 = &hdmi0; | |
24 | }; | |
25 | ||
5b434d7e NM |
26 | evm_3v3: fixedregulator-evm_3v3 { |
27 | compatible = "regulator-fixed"; | |
28 | regulator-name = "evm_3v3"; | |
29 | regulator-min-microvolt = <3300000>; | |
30 | regulator-max-microvolt = <3300000>; | |
31 | }; | |
f56de327 RQ |
32 | |
33 | extcon_usb1: extcon_usb1 { | |
34 | compatible = "linux,extcon-usb-gpio"; | |
35 | id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; | |
36 | }; | |
37 | ||
38 | extcon_usb2: extcon_usb2 { | |
39 | compatible = "linux,extcon-usb-gpio"; | |
40 | id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; | |
41 | }; | |
fadf0d0b TV |
42 | |
43 | hdmi0: connector { | |
44 | compatible = "hdmi-connector"; | |
45 | label = "hdmi"; | |
46 | ||
47 | type = "a"; | |
48 | ||
49 | port { | |
50 | hdmi_connector_in: endpoint { | |
51 | remote-endpoint = <&tpd12s015_out>; | |
52 | }; | |
53 | }; | |
54 | }; | |
55 | ||
56 | tpd12s015: encoder { | |
57 | compatible = "ti,tpd12s015"; | |
58 | ||
59 | pinctrl-names = "default"; | |
60 | pinctrl-0 = <&tpd12s015_pins>; | |
61 | ||
62 | gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ | |
63 | <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ | |
64 | <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ | |
65 | ||
66 | ports { | |
67 | #address-cells = <1>; | |
68 | #size-cells = <0>; | |
69 | ||
70 | port@0 { | |
71 | reg = <0>; | |
72 | ||
73 | tpd12s015_in: endpoint { | |
74 | remote-endpoint = <&hdmi_out>; | |
75 | }; | |
76 | }; | |
77 | ||
78 | port@1 { | |
79 | reg = <1>; | |
80 | ||
81 | tpd12s015_out: endpoint { | |
82 | remote-endpoint = <&hdmi_connector_in>; | |
83 | }; | |
84 | }; | |
85 | }; | |
86 | }; | |
38b248db RN |
87 | }; |
88 | ||
7e9711aa K |
89 | &dra7_pmx_core { |
90 | i2c1_pins: pinmux_i2c1_pins { | |
91 | pinctrl-single,pins = < | |
92 | 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ | |
93 | 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ | |
94 | >; | |
95 | }; | |
09d4993c | 96 | |
fadf0d0b TV |
97 | i2c5_pins: pinmux_i2c5_pins { |
98 | pinctrl-single,pins = < | |
99 | 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ | |
100 | 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ | |
101 | >; | |
102 | }; | |
103 | ||
09d4993c RQ |
104 | nand_default: nand_default { |
105 | pinctrl-single,pins = < | |
106 | 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ | |
107 | 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ | |
108 | 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ | |
109 | 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ | |
110 | 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ | |
111 | 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ | |
112 | 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ | |
113 | 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ | |
114 | 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ | |
115 | 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ | |
116 | 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ | |
117 | 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ | |
118 | 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ | |
119 | 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ | |
120 | 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ | |
121 | 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ | |
122 | 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ | |
123 | 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ | |
124 | 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ | |
125 | 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ | |
126 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ | |
127 | 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ | |
128 | >; | |
129 | }; | |
95cc6af8 GC |
130 | |
131 | usb1_pins: pinmux_usb1_pins { | |
132 | pinctrl-single,pins = < | |
133 | 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ | |
134 | >; | |
135 | }; | |
136 | ||
137 | usb2_pins: pinmux_usb2_pins { | |
138 | pinctrl-single,pins = < | |
139 | 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ | |
140 | >; | |
141 | }; | |
829acd07 NM |
142 | |
143 | tps65917_pins_default: tps65917_pins_default { | |
144 | pinctrl-single,pins = < | |
145 | 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ | |
146 | >; | |
147 | }; | |
5b434d7e NM |
148 | |
149 | mmc1_pins_default: mmc1_pins_default { | |
150 | pinctrl-single,pins = < | |
151 | 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ | |
152 | 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | |
153 | 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | |
154 | 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | |
155 | 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | |
156 | 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | |
157 | 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | |
158 | >; | |
159 | }; | |
160 | ||
161 | mmc2_pins_default: mmc2_pins_default { | |
162 | pinctrl-single,pins = < | |
163 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | |
164 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | |
165 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | |
166 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | |
167 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | |
168 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | |
169 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | |
170 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | |
171 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | |
172 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | |
173 | >; | |
174 | }; | |
ea95af3c RQ |
175 | |
176 | dcan1_pins_default: dcan1_pins_default { | |
177 | pinctrl-single,pins = < | |
d80d581b RQ |
178 | 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ |
179 | 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ | |
ea95af3c RQ |
180 | >; |
181 | }; | |
182 | ||
183 | dcan1_pins_sleep: dcan1_pins_sleep { | |
184 | pinctrl-single,pins = < | |
d80d581b RQ |
185 | 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ |
186 | 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ | |
ea95af3c RQ |
187 | >; |
188 | }; | |
1f43c45d M |
189 | |
190 | qspi1_pins: pinmux_qspi1_pins { | |
191 | pinctrl-single,pins = < | |
192 | 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ | |
193 | 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ | |
194 | 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ | |
195 | 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ | |
196 | 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ | |
197 | 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ | |
198 | 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ | |
199 | >; | |
200 | }; | |
fadf0d0b TV |
201 | |
202 | hdmi_pins: pinmux_hdmi_pins { | |
203 | pinctrl-single,pins = < | |
204 | 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ | |
205 | 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ | |
206 | >; | |
207 | }; | |
208 | ||
209 | tpd12s015_pins: pinmux_tpd12s015_pins { | |
210 | pinctrl-single,pins = < | |
211 | 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ | |
212 | >; | |
213 | }; | |
7e9711aa K |
214 | }; |
215 | ||
216 | &i2c1 { | |
217 | status = "okay"; | |
218 | pinctrl-names = "default"; | |
219 | pinctrl-0 = <&i2c1_pins>; | |
220 | clock-frequency = <400000>; | |
b359c426 K |
221 | |
222 | tps65917: tps65917@58 { | |
223 | compatible = "ti,tps65917"; | |
224 | reg = <0x58>; | |
225 | ||
829acd07 NM |
226 | pinctrl-names = "default"; |
227 | pinctrl-0 = <&tps65917_pins_default>; | |
228 | ||
b359c426 | 229 | interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ |
b359c426 K |
230 | interrupt-controller; |
231 | #interrupt-cells = <2>; | |
232 | ||
233 | ti,system-power-controller; | |
234 | ||
235 | tps65917_pmic { | |
236 | compatible = "ti,tps65917-pmic"; | |
237 | ||
238 | regulators { | |
239 | smps1_reg: smps1 { | |
240 | /* VDD_MPU */ | |
241 | regulator-name = "smps1"; | |
242 | regulator-min-microvolt = <850000>; | |
243 | regulator-max-microvolt = <1250000>; | |
244 | regulator-always-on; | |
245 | regulator-boot-on; | |
246 | }; | |
247 | ||
248 | smps2_reg: smps2 { | |
249 | /* VDD_CORE */ | |
250 | regulator-name = "smps2"; | |
251 | regulator-min-microvolt = <850000>; | |
70fcaf92 | 252 | regulator-max-microvolt = <1060000>; |
b359c426 K |
253 | regulator-boot-on; |
254 | regulator-always-on; | |
255 | }; | |
256 | ||
257 | smps3_reg: smps3 { | |
258 | /* VDD_GPU IVA DSPEVE */ | |
259 | regulator-name = "smps3"; | |
260 | regulator-min-microvolt = <850000>; | |
261 | regulator-max-microvolt = <1250000>; | |
262 | regulator-boot-on; | |
263 | regulator-always-on; | |
264 | }; | |
265 | ||
266 | smps4_reg: smps4 { | |
267 | /* VDDS1V8 */ | |
268 | regulator-name = "smps4"; | |
269 | regulator-min-microvolt = <1800000>; | |
270 | regulator-max-microvolt = <1800000>; | |
271 | regulator-always-on; | |
272 | regulator-boot-on; | |
273 | }; | |
274 | ||
275 | smps5_reg: smps5 { | |
276 | /* VDD_DDR */ | |
277 | regulator-name = "smps5"; | |
278 | regulator-min-microvolt = <1350000>; | |
279 | regulator-max-microvolt = <1350000>; | |
280 | regulator-boot-on; | |
281 | regulator-always-on; | |
282 | }; | |
283 | ||
284 | ldo1_reg: ldo1 { | |
285 | /* LDO1_OUT --> SDIO */ | |
286 | regulator-name = "ldo1"; | |
287 | regulator-min-microvolt = <1800000>; | |
288 | regulator-max-microvolt = <3300000>; | |
289 | regulator-boot-on; | |
290 | }; | |
291 | ||
292 | ldo2_reg: ldo2 { | |
293 | /* LDO2_OUT --> TP1017 (UNUSED) */ | |
294 | regulator-name = "ldo2"; | |
295 | regulator-min-microvolt = <1800000>; | |
296 | regulator-max-microvolt = <3300000>; | |
297 | }; | |
298 | ||
299 | ldo3_reg: ldo3 { | |
300 | /* VDDA_1V8_PHY */ | |
301 | regulator-name = "ldo3"; | |
302 | regulator-min-microvolt = <1800000>; | |
303 | regulator-max-microvolt = <1800000>; | |
304 | regulator-boot-on; | |
305 | regulator-always-on; | |
306 | }; | |
307 | ||
308 | ldo5_reg: ldo5 { | |
309 | /* VDDA_1V8_PLL */ | |
310 | regulator-name = "ldo5"; | |
311 | regulator-min-microvolt = <1800000>; | |
312 | regulator-max-microvolt = <1800000>; | |
313 | regulator-always-on; | |
314 | regulator-boot-on; | |
315 | }; | |
316 | ||
317 | ldo4_reg: ldo4 { | |
318 | /* VDDA_3V_USB: VDDA_USBHS33 */ | |
319 | regulator-name = "ldo4"; | |
320 | regulator-min-microvolt = <3300000>; | |
321 | regulator-max-microvolt = <3300000>; | |
322 | regulator-boot-on; | |
323 | }; | |
324 | }; | |
325 | }; | |
ab1d3c84 NM |
326 | |
327 | tps65917_power_button { | |
328 | compatible = "ti,palmas-pwrbutton"; | |
329 | interrupt-parent = <&tps65917>; | |
330 | interrupts = <1 IRQ_TYPE_NONE>; | |
331 | wakeup-source; | |
332 | ti,palmas-long-press-seconds = <6>; | |
333 | }; | |
b359c426 | 334 | }; |
f56de327 RQ |
335 | |
336 | pcf_gpio_21: gpio@21 { | |
337 | compatible = "ti,pcf8575"; | |
338 | reg = <0x21>; | |
339 | lines-initial-states = <0x1408>; | |
340 | gpio-controller; | |
341 | #gpio-cells = <2>; | |
342 | interrupt-parent = <&gpio6>; | |
343 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; | |
344 | interrupt-controller; | |
345 | #interrupt-cells = <2>; | |
346 | }; | |
7e9711aa K |
347 | }; |
348 | ||
fadf0d0b TV |
349 | &i2c5 { |
350 | status = "okay"; | |
351 | pinctrl-names = "default"; | |
352 | pinctrl-0 = <&i2c5_pins>; | |
353 | clock-frequency = <400000>; | |
354 | ||
355 | pcf_hdmi: pcf8575@26 { | |
356 | compatible = "nxp,pcf8575"; | |
357 | reg = <0x26>; | |
358 | gpio-controller; | |
359 | #gpio-cells = <2>; | |
360 | /* | |
361 | * initial state is used here to keep the mdio interface | |
362 | * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and | |
363 | * VIN2_S0 driven high otherwise Ethernet stops working | |
364 | * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 | |
365 | */ | |
366 | lines-initial-states = <0x0f2b>; | |
367 | }; | |
368 | }; | |
369 | ||
38b248db RN |
370 | &uart1 { |
371 | status = "okay"; | |
372 | }; | |
09d4993c RQ |
373 | |
374 | &elm { | |
375 | status = "okay"; | |
376 | }; | |
377 | ||
378 | &gpmc { | |
379 | status = "okay"; | |
380 | pinctrl-names = "default"; | |
381 | pinctrl-0 = <&nand_default>; | |
382 | ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ | |
383 | nand@0,0 { | |
384 | /* To use NAND, DIP switch SW5 must be set like so: | |
385 | * SW5.1 (NAND_SELn) = ON (LOW) | |
386 | * SW5.9 (GPMC_WPN) = OFF (HIGH) | |
387 | */ | |
388 | reg = <0 0 4>; /* device IO registers */ | |
389 | ti,nand-ecc-opt = "bch8"; | |
390 | ti,elm-id = <&elm>; | |
391 | nand-bus-width = <16>; | |
392 | gpmc,device-width = <2>; | |
393 | gpmc,sync-clk-ps = <0>; | |
394 | gpmc,cs-on-ns = <0>; | |
395 | gpmc,cs-rd-off-ns = <80>; | |
396 | gpmc,cs-wr-off-ns = <80>; | |
397 | gpmc,adv-on-ns = <0>; | |
398 | gpmc,adv-rd-off-ns = <60>; | |
399 | gpmc,adv-wr-off-ns = <60>; | |
400 | gpmc,we-on-ns = <10>; | |
401 | gpmc,we-off-ns = <50>; | |
402 | gpmc,oe-on-ns = <4>; | |
403 | gpmc,oe-off-ns = <40>; | |
404 | gpmc,access-ns = <40>; | |
405 | gpmc,wr-access-ns = <80>; | |
406 | gpmc,rd-cycle-ns = <80>; | |
407 | gpmc,wr-cycle-ns = <80>; | |
408 | gpmc,bus-turnaround-ns = <0>; | |
409 | gpmc,cycle2cycle-delay-ns = <0>; | |
410 | gpmc,clk-activation-ns = <0>; | |
411 | gpmc,wait-monitoring-ns = <0>; | |
412 | gpmc,wr-data-mux-bus-ns = <0>; | |
413 | /* MTD partition table */ | |
414 | /* All SPL-* partitions are sized to minimal length | |
415 | * which can be independently programmable. For | |
416 | * NAND flash this is equal to size of erase-block */ | |
417 | #address-cells = <1>; | |
418 | #size-cells = <1>; | |
419 | partition@0 { | |
420 | label = "NAND.SPL"; | |
421 | reg = <0x00000000 0x000020000>; | |
422 | }; | |
423 | partition@1 { | |
424 | label = "NAND.SPL.backup1"; | |
425 | reg = <0x00020000 0x00020000>; | |
426 | }; | |
427 | partition@2 { | |
428 | label = "NAND.SPL.backup2"; | |
429 | reg = <0x00040000 0x00020000>; | |
430 | }; | |
431 | partition@3 { | |
432 | label = "NAND.SPL.backup3"; | |
433 | reg = <0x00060000 0x00020000>; | |
434 | }; | |
435 | partition@4 { | |
436 | label = "NAND.u-boot-spl-os"; | |
437 | reg = <0x00080000 0x00040000>; | |
438 | }; | |
439 | partition@5 { | |
440 | label = "NAND.u-boot"; | |
441 | reg = <0x000c0000 0x00100000>; | |
442 | }; | |
443 | partition@6 { | |
444 | label = "NAND.u-boot-env"; | |
445 | reg = <0x001c0000 0x00020000>; | |
446 | }; | |
447 | partition@7 { | |
448 | label = "NAND.u-boot-env.backup1"; | |
449 | reg = <0x001e0000 0x00020000>; | |
450 | }; | |
451 | partition@8 { | |
452 | label = "NAND.kernel"; | |
453 | reg = <0x00200000 0x00800000>; | |
454 | }; | |
455 | partition@9 { | |
456 | label = "NAND.file-system"; | |
457 | reg = <0x00a00000 0x0f600000>; | |
458 | }; | |
459 | }; | |
460 | }; | |
95cc6af8 | 461 | |
7a15c8e7 RQ |
462 | &usb2_phy1 { |
463 | phy-supply = <&ldo4_reg>; | |
464 | }; | |
465 | ||
466 | &usb2_phy2 { | |
467 | phy-supply = <&ldo4_reg>; | |
468 | }; | |
469 | ||
a7b0aa19 RQ |
470 | &omap_dwc3_1 { |
471 | extcon = <&extcon_usb1>; | |
472 | }; | |
473 | ||
474 | &omap_dwc3_2 { | |
475 | extcon = <&extcon_usb2>; | |
476 | }; | |
477 | ||
95cc6af8 GC |
478 | &usb1 { |
479 | dr_mode = "peripheral"; | |
480 | pinctrl-names = "default"; | |
481 | pinctrl-0 = <&usb1_pins>; | |
482 | }; | |
483 | ||
484 | &usb2 { | |
485 | dr_mode = "host"; | |
486 | pinctrl-names = "default"; | |
487 | pinctrl-0 = <&usb2_pins>; | |
488 | }; | |
5b434d7e NM |
489 | |
490 | &mmc1 { | |
491 | status = "okay"; | |
492 | pinctrl-names = "default"; | |
493 | pinctrl-0 = <&mmc1_pins_default>; | |
494 | ||
495 | vmmc-supply = <&ldo1_reg>; | |
496 | bus-width = <4>; | |
497 | /* | |
498 | * SDCD signal is not being used here - using the fact that GPIO mode | |
499 | * is a viable alternative | |
500 | */ | |
501 | cd-gpios = <&gpio6 27 0>; | |
502 | }; | |
503 | ||
504 | &mmc2 { | |
505 | /* SW5-3 in ON position */ | |
506 | status = "okay"; | |
507 | pinctrl-names = "default"; | |
508 | pinctrl-0 = <&mmc2_pins_default>; | |
509 | ||
510 | vmmc-supply = <&evm_3v3>; | |
511 | bus-width = <8>; | |
512 | ti,non-removable; | |
513 | }; | |
d5475152 M |
514 | |
515 | &dra7_pmx_core { | |
516 | cpsw_default: cpsw_default { | |
517 | pinctrl-single,pins = < | |
518 | /* Slave 2 */ | |
519 | 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ | |
520 | 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ | |
521 | 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ | |
522 | 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ | |
523 | 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ | |
524 | 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ | |
525 | 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ | |
526 | 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ | |
527 | 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ | |
528 | 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ | |
529 | 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ | |
530 | 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ | |
531 | >; | |
532 | ||
533 | }; | |
534 | ||
535 | cpsw_sleep: cpsw_sleep { | |
536 | pinctrl-single,pins = < | |
537 | /* Slave 2 */ | |
538 | 0x198 (MUX_MODE15) | |
539 | 0x19c (MUX_MODE15) | |
540 | 0x1a0 (MUX_MODE15) | |
541 | 0x1a4 (MUX_MODE15) | |
542 | 0x1a8 (MUX_MODE15) | |
543 | 0x1ac (MUX_MODE15) | |
544 | 0x1b0 (MUX_MODE15) | |
545 | 0x1b4 (MUX_MODE15) | |
546 | 0x1b8 (MUX_MODE15) | |
547 | 0x1bc (MUX_MODE15) | |
548 | 0x1c0 (MUX_MODE15) | |
549 | 0x1c4 (MUX_MODE15) | |
550 | >; | |
551 | }; | |
552 | ||
553 | davinci_mdio_default: davinci_mdio_default { | |
554 | pinctrl-single,pins = < | |
555 | /* MDIO */ | |
556 | 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ | |
557 | 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
558 | >; | |
559 | }; | |
560 | ||
561 | davinci_mdio_sleep: davinci_mdio_sleep { | |
562 | pinctrl-single,pins = < | |
563 | 0x23c (MUX_MODE15) | |
564 | 0x240 (MUX_MODE15) | |
565 | >; | |
566 | }; | |
567 | }; | |
568 | ||
569 | &mac { | |
570 | status = "okay"; | |
571 | pinctrl-names = "default", "sleep"; | |
572 | pinctrl-0 = <&cpsw_default>; | |
573 | pinctrl-1 = <&cpsw_sleep>; | |
574 | }; | |
575 | ||
576 | &cpsw_emac1 { | |
577 | phy_id = <&davinci_mdio>, <3>; | |
578 | phy-mode = "rgmii"; | |
579 | }; | |
580 | ||
581 | &davinci_mdio { | |
582 | pinctrl-names = "default", "sleep"; | |
583 | pinctrl-0 = <&davinci_mdio_default>; | |
584 | pinctrl-1 = <&davinci_mdio_sleep>; | |
585 | active_slave = <1>; | |
586 | }; | |
ea95af3c RQ |
587 | |
588 | &dcan1 { | |
589 | status = "ok"; | |
2acb5c30 RQ |
590 | pinctrl-names = "default", "sleep", "active"; |
591 | pinctrl-0 = <&dcan1_pins_sleep>; | |
ea95af3c | 592 | pinctrl-1 = <&dcan1_pins_sleep>; |
2acb5c30 | 593 | pinctrl-2 = <&dcan1_pins_default>; |
ea95af3c | 594 | }; |
1f43c45d M |
595 | |
596 | &qspi { | |
597 | status = "okay"; | |
598 | pinctrl-names = "default"; | |
599 | pinctrl-0 = <&qspi1_pins>; | |
600 | ||
601 | spi-max-frequency = <48000000>; | |
602 | m25p80@0 { | |
603 | compatible = "s25fl256s1"; | |
604 | spi-max-frequency = <48000000>; | |
605 | reg = <0>; | |
606 | spi-tx-bus-width = <1>; | |
607 | spi-rx-bus-width = <4>; | |
608 | spi-cpol; | |
609 | spi-cpha; | |
610 | #address-cells = <1>; | |
611 | #size-cells = <1>; | |
612 | ||
613 | /* MTD partition table. | |
614 | * The ROM checks the first four physical blocks | |
615 | * for a valid file to boot and the flash here is | |
616 | * 64KiB block size. | |
617 | */ | |
618 | partition@0 { | |
619 | label = "QSPI.SPL"; | |
620 | reg = <0x00000000 0x000010000>; | |
621 | }; | |
622 | partition@1 { | |
623 | label = "QSPI.SPL.backup1"; | |
624 | reg = <0x00010000 0x00010000>; | |
625 | }; | |
626 | partition@2 { | |
627 | label = "QSPI.SPL.backup2"; | |
628 | reg = <0x00020000 0x00010000>; | |
629 | }; | |
630 | partition@3 { | |
631 | label = "QSPI.SPL.backup3"; | |
632 | reg = <0x00030000 0x00010000>; | |
633 | }; | |
634 | partition@4 { | |
635 | label = "QSPI.u-boot"; | |
636 | reg = <0x00040000 0x00100000>; | |
637 | }; | |
638 | partition@5 { | |
639 | label = "QSPI.u-boot-spl-os"; | |
640 | reg = <0x00140000 0x00080000>; | |
641 | }; | |
642 | partition@6 { | |
643 | label = "QSPI.u-boot-env"; | |
644 | reg = <0x001c0000 0x00010000>; | |
645 | }; | |
646 | partition@7 { | |
647 | label = "QSPI.u-boot-env.backup1"; | |
648 | reg = <0x001d0000 0x0010000>; | |
649 | }; | |
650 | partition@8 { | |
651 | label = "QSPI.kernel"; | |
652 | reg = <0x001e0000 0x0800000>; | |
653 | }; | |
654 | partition@9 { | |
655 | label = "QSPI.file-system"; | |
656 | reg = <0x009e0000 0x01620000>; | |
657 | }; | |
658 | }; | |
659 | }; | |
fadf0d0b TV |
660 | |
661 | &dss { | |
662 | status = "ok"; | |
663 | ||
664 | vdda_video-supply = <&ldo5_reg>; | |
665 | }; | |
666 | ||
667 | &hdmi { | |
668 | status = "ok"; | |
669 | vdda-supply = <&ldo3_reg>; | |
670 | ||
671 | pinctrl-names = "default"; | |
672 | pinctrl-0 = <&hdmi_pins>; | |
673 | ||
674 | port { | |
675 | hdmi_out: endpoint { | |
676 | remote-endpoint = <&tpd12s015_in>; | |
677 | }; | |
678 | }; | |
679 | }; |