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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
148127d3 LV |
2 | /* |
3 | * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ | |
148127d3 LV |
4 | */ |
5 | ||
6 | #include "dra74x.dtsi" | |
7 | ||
8 | / { | |
9 | compatible = "ti,dra762", "ti,dra7"; | |
10 | ||
09a070a3 FA |
11 | ocp { |
12 | target-module@42c01900 { | |
13 | compatible = "ti,sysc-dra7-mcan", "ti,sysc"; | |
14 | ranges = <0x0 0x42c00000 0x2000>; | |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | reg = <0x42c01900 0x4>, | |
18 | <0x42c01904 0x4>, | |
19 | <0x42c01908 0x4>; | |
20 | reg-names = "rev", "sysc", "syss"; | |
21 | ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | | |
22 | SYSC_DRA7_MCAN_ENAWAKEUP)>; | |
23 | ti,syss-mask = <1>; | |
b5f8ffbb | 24 | clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>; |
09a070a3 | 25 | clock-names = "fck"; |
0adbe832 FA |
26 | |
27 | m_can0: mcan@1a00 { | |
28 | compatible = "bosch,m_can"; | |
29 | reg = <0x1a00 0x4000>, <0x0 0x18FC>; | |
30 | reg-names = "m_can", "message_ram"; | |
31 | interrupt-parent = <&gic>; | |
32 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
33 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
34 | interrupt-names = "int0", "int1"; | |
35 | clocks = <&mcan_clk>, <&l3_iclk_div>; | |
36 | clock-names = "cclk", "hclk"; | |
37 | bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; | |
38 | }; | |
09a070a3 FA |
39 | }; |
40 | }; | |
41 | ||
148127d3 LV |
42 | }; |
43 | ||
44 | /* MCAN interrupts are hard-wired to irqs 67, 68 */ | |
45 | &crossbar_mpu { | |
46 | ti,irqs-skip = <10 67 68 133 139 140>; | |
47 | }; | |
6ae8d5c1 LV |
48 | |
49 | &scm_conf_clocks { | |
50 | dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { | |
51 | #clock-cells = <0>; | |
52 | compatible = "ti,divider-clock"; | |
53 | clocks = <&dpll_gmac_x2_ck>; | |
54 | ti,max-div = <63>; | |
55 | reg = <0x03fc>; | |
56 | ti,bit-shift=<20>; | |
57 | ti,latch-bit=<26>; | |
58 | assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; | |
59 | assigned-clock-rates = <80000000>; | |
60 | }; | |
61 | ||
62 | dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { | |
63 | #clock-cells = <0>; | |
64 | compatible = "ti,mux-clock"; | |
65 | clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; | |
66 | reg = <0x3fc>; | |
67 | ti,bit-shift = <29>; | |
68 | ti,latch-bit=<26>; | |
69 | assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; | |
70 | assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; | |
71 | }; | |
72 | ||
73 | mcan_clk: mcan_clk@3fc { | |
74 | #clock-cells = <0>; | |
75 | compatible = "ti,gate-clock"; | |
76 | clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; | |
77 | ti,bit-shift = <27>; | |
78 | reg = <0x3fc>; | |
79 | }; | |
80 | }; | |
f7b9cb94 K |
81 | |
82 | &rtctarget { | |
83 | status = "disabled"; | |
84 | }; | |
b07bd27e K |
85 | |
86 | &usb4_tm { | |
87 | status = "disabled"; | |
88 | }; |