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b004a34b CC |
1 | /* |
2 | * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source | |
3 | * | |
4 | * Copyright (c) 2016 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Device tree source file for Samsung's ARTIK5 evaluation board | |
8 | * which is based on Samsung Exynos3250 SoC. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | /dts-v1/; | |
16 | #include "exynos3250-artik5.dtsi" | |
17 | ||
18 | / { | |
19 | model = "Samsung ARTIK5 evaluation board"; | |
20 | compatible = "samsung,artik5-eval", "samsung,artik5", | |
21 | "samsung,exynos3250", "samsung,exynos3"; | |
22 | }; | |
23 | ||
e70c7ae1 JC |
24 | &mshc_2 { |
25 | num-slots = <1>; | |
26 | cap-sd-highspeed; | |
27 | disable-wp; | |
28 | vqmmc-supply = <&ldo3_reg>; | |
29 | card-detect-delay = <200>; | |
30 | clock-frequency = <100000000>; | |
9adce7a4 | 31 | max-frequency = <100000000>; |
e70c7ae1 JC |
32 | samsung,dw-mshc-ciu-div = <1>; |
33 | samsung,dw-mshc-sdr-timing = <0 1>; | |
34 | samsung,dw-mshc-ddr-timing = <1 2>; | |
35 | pinctrl-names = "default"; | |
36 | pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>; | |
37 | bus-width = <4>; | |
38 | status = "okay"; | |
39 | }; | |
40 | ||
b004a34b CC |
41 | &serial_2 { |
42 | status = "okay"; | |
43 | }; |