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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / exynos3250.dtsi
CommitLineData
cc4637f7 1// SPDX-License-Identifier: GPL-2.0
5a992a9c
TF		 2/*
3 * Samsung's Exynos3250 SoC device tree source
4 *
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
14 * nodes can be added to this file.
5a992a9c
TF		 15 */
16
9843a223 17#include "exynos4-cpu-thermal.dtsi"
5a992a9c 18#include <dt-bindings/clock/exynos3250.h>
9645ab2c 19#include <dt-bindings/interrupt-controller/arm-gic.h>
89be8511 20#include <dt-bindings/interrupt-controller/irq.h>
5a992a9c
TF		 21
22/ {
23 compatible = "samsung,exynos3250";
24 interrupt-parent = <&gic>;
33c3de7e
JMC		 25 #address-cells = <1>;
26 #size-cells = <1>;
5a992a9c
TF		 27
28 aliases {
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 mshc0 = &mshc_0;
32 mshc1 = &mshc_1;
92173e6a 33 mshc2 = &mshc_2;
5a992a9c
TF		 34 spi0 = &spi_0;
35 spi1 = &spi_1;
36 i2c0 = &i2c_0;
37 i2c1 = &i2c_1;
38 i2c2 = &i2c_2;
39 i2c3 = &i2c_3;
40 i2c4 = &i2c_4;
41 i2c5 = &i2c_5;
42 i2c6 = &i2c_6;
43 i2c7 = &i2c_7;
1e64f48e
TF		 44 serial0 = &serial_0;
45 serial1 = &serial_1;
ecaba514 46 serial2 = &serial_2;
5a992a9c
TF		 47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a7";
56 reg = <0>;
57 clock-frequency = <1000000000>;
48816aff
CC		 58 clocks = <&cmu CLK_ARM_CLK>;
59 clock-names = "cpu";
5600f8cc 60 #cooling-cells = <2>;
48816aff
CC		 61
62 operating-points = <
63 1000000 1150000
64 900000 1112500
65 800000 1075000
66 700000 1037500
67 600000 1000000
68 500000 962500
69 400000 925000
70 300000 887500
71 200000 850000
72 100000 850000
73 >;
5a992a9c
TF		 74 };
75
76 cpu1: cpu@1 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a7";
79 reg = <1>;
80 clock-frequency = <1000000000>;
672f3319
VK		 81 clocks = <&cmu CLK_ARM_CLK>;
82 clock-names = "cpu";
83 #cooling-cells = <2>;
84
85 operating-points = <
86 1000000 1150000
87 900000 1112500
88 800000 1075000
89 700000 1037500
90 600000 1000000
91 500000 962500
92 400000 925000
93 300000 887500
94 200000 850000
95 100000 850000
96 >;
5a992a9c
TF		 97 };
98 };
99
100 soc: soc {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges;
105
106 fixed-rate-clocks {
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 xusbxti: clock@0 {
111 compatible = "fixed-clock";
112 #address-cells = <1>;
113 #size-cells = <0>;
114 reg = <0>;
115 clock-frequency = <0>;
116 #clock-cells = <0>;
117 clock-output-names = "xusbxti";
118 };
119
120 xxti: clock@1 {
121 compatible = "fixed-clock";
122 reg = <1>;
123 clock-frequency = <0>;
124 #clock-cells = <0>;
125 clock-output-names = "xxti";
126 };
127
128 xtcxo: clock@2 {
129 compatible = "fixed-clock";
130 reg = <2>;
131 clock-frequency = <0>;
132 #clock-cells = <0>;
133 clock-output-names = "xtcxo";
134 };
135 };
136
8dccafaa 137 sysram@2020000 {
5a992a9c
TF		 138 compatible = "mmio-sram";
139 reg = <0x02020000 0x40000>;
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0 0x02020000 0x40000>;
143
144 smp-sysram@0 {
145 compatible = "samsung,exynos4210-sysram";
146 reg = <0x0 0x1000>;
147 };
148
149 smp-sysram@3f000 {
150 compatible = "samsung,exynos4210-sysram-ns";
151 reg = <0x3f000 0x1000>;
152 };
153 };
154
155 chipid@10000000 {
156 compatible = "samsung,exynos4210-chipid";
157 reg = <0x10000000 0x100>;
158 };
159
160 sys_reg: syscon@10010000 {
161 compatible = "samsung,exynos3-sysreg", "syscon";
162 reg = <0x10010000 0x400>;
163 };
164
25023926
CC		 165 pmu_system_controller: system-controller@10020000 {
166 compatible = "samsung,exynos3250-pmu", "syscon";
167 reg = <0x10020000 0x4000>;
8b283c02
MZ		 168 interrupt-controller;
169 #interrupt-cells = <3>;
170 interrupt-parent = <&gic>;
25023926
CC		 171 };
172
bb72cade 173 mipi_phy: video-phy {
9fab9d6a 174 compatible = "samsung,s5pv210-mipi-video-phy";
9fab9d6a 175 #phy-cells = <1>;
1342ff45 176 syscon = <&pmu_system_controller>;
9fab9d6a
ID		 177 };
178
6891227b 179 pd_cam: power-domain@10023c00 {
5a992a9c
TF		 180 compatible = "samsung,exynos4210-pd";
181 reg = <0x10023C00 0x20>;
0da65870 182 #power-domain-cells = <0>;
6891227b 183 label = "CAM";
5a992a9c
TF		 184 };
185
6891227b 186 pd_mfc: power-domain@10023c40 {
5a992a9c
TF		 187 compatible = "samsung,exynos4210-pd";
188 reg = <0x10023C40 0x20>;
0da65870 189 #power-domain-cells = <0>;
6891227b 190 label = "MFC";
5a992a9c
TF		 191 };
192
6891227b 193 pd_g3d: power-domain@10023c60 {
5a992a9c
TF		 194 compatible = "samsung,exynos4210-pd";
195 reg = <0x10023C60 0x20>;
0da65870 196 #power-domain-cells = <0>;
6891227b 197 label = "G3D";
5a992a9c
TF		 198 };
199
6891227b 200 pd_lcd0: power-domain@10023c80 {
5a992a9c
TF		 201 compatible = "samsung,exynos4210-pd";
202 reg = <0x10023C80 0x20>;
0da65870 203 #power-domain-cells = <0>;
6891227b 204 label = "LCD0";
5a992a9c
TF		 205 };
206
6891227b 207 pd_isp: power-domain@10023ca0 {
5a992a9c
TF		 208 compatible = "samsung,exynos4210-pd";
209 reg = <0x10023CA0 0x20>;
0da65870 210 #power-domain-cells = <0>;
6891227b 211 label = "ISP";
5a992a9c
TF		 212 };
213
214 cmu: clock-controller@10030000 {
215 compatible = "samsung,exynos3250-cmu";
216 reg = <0x10030000 0x20000>;
217 #clock-cells = <1>;
52005dec
BM		 218 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
219 <&cmu CLK_MOUT_ACLK_266_SUB>;
220 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
221 <&cmu CLK_FIN_PLL>;
5a992a9c
TF		 222 };
223
3be1ecf2 224 cmu_dmc: clock-controller@105c0000 {
d0e73eaf
KK		 225 compatible = "samsung,exynos3250-cmu-dmc";
226 reg = <0x105C0000 0x2000>;
227 #clock-cells = <1>;
228 };
229
5a992a9c 230 rtc: rtc@10070000 {
062f49c4 231 compatible = "samsung,s3c6410-rtc";
5a992a9c 232 reg = <0x10070000 0x100>;
9645ab2c
KK		 233 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
8b283c02 235 interrupt-parent = <&pmu_system_controller>;
5a992a9c
TF		 236 status = "disabled";
237 };
238
3be1ecf2 239 tmu: tmu@100c0000 {
9dfb3347
CC		 240 compatible = "samsung,exynos3250-tmu";
241 reg = <0x100C0000 0x100>;
9645ab2c 242 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
9dfb3347
CC		 243 clocks = <&cmu CLK_TMU_APBIF>;
244 clock-names = "tmu_apbif";
c05b799e 245 #thermal-sensor-cells = <0>;
9dfb3347
CC		 246 status = "disabled";
247 };
248
5a992a9c
TF		 249 gic: interrupt-controller@10481000 {
250 compatible = "arm,cortex-a15-gic";
251 #interrupt-cells = <3>;
252 interrupt-controller;
253 reg = <0x10481000 0x1000>,
387720c9 254 <0x10482000 0x2000>,
5a992a9c
TF		 255 <0x10484000 0x2000>,
256 <0x10486000 0x2000>;
9645ab2c
KK		 257 interrupts = <GIC_PPI 9
258 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
5a992a9c
TF		 259 };
260
261 mct@10050000 {
262 compatible = "samsung,exynos4210-mct";
263 reg = <0x10050000 0x800>;
9645ab2c
KK		 264 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 272 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
273 clock-names = "fin_pll", "mct";
274 };
275
276 pinctrl_1: pinctrl@11000000 {
277 compatible = "samsung,exynos3250-pinctrl";
278 reg = <0x11000000 0x1000>;
9645ab2c 279 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 280
281 wakeup-interrupt-controller {
282 compatible = "samsung,exynos4210-wakeup-eint";
9645ab2c 283 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 284 };
285 };
286
287 pinctrl_0: pinctrl@11400000 {
288 compatible = "samsung,exynos3250-pinctrl";
289 reg = <0x11400000 0x1000>;
9645ab2c 290 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 291 };
292
c9c1adfe
JA		 293 jpeg: codec@11830000 {
294 compatible = "samsung,exynos3250-jpeg";
295 reg = <0x11830000 0x1000>;
9645ab2c 296 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
c9c1adfe
JA		 297 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
298 clock-names = "jpeg", "sclk";
299 power-domains = <&pd_cam>;
300 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
301 assigned-clock-rates = <0>, <150000000>;
302 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
f5976ce5 303 iommus = <&sysmmu_jpeg>;
c9c1adfe
JA		 304 status = "disabled";
305 };
306
3be1ecf2 307 sysmmu_jpeg: sysmmu@11a60000 {
f5976ce5
MS		 308 compatible = "samsung,exynos-sysmmu";
309 reg = <0x11a60000 0x1000>;
9645ab2c
KK		 310 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
f5976ce5
MS		 312 clock-names = "sysmmu", "master";
313 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
314 power-domains = <&pd_cam>;
315 #iommu-cells = <0>;
316 };
317
03b86c79
ID		 318 fimd: fimd@11c00000 {
319 compatible = "samsung,exynos3250-fimd";
320 reg = <0x11c00000 0x30000>;
321 interrupt-names = "fifo", "vsync", "lcd_sys";
9645ab2c
KK		 322 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
03b86c79
ID		 325 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
326 clock-names = "sclk_fimd", "fimd";
0da65870 327 power-domains = <&pd_lcd0>;
f5976ce5 328 iommus = <&sysmmu_fimd0>;
03b86c79
ID		 329 samsung,sysreg = <&sys_reg>;
330 status = "disabled";
331 };
332
3be1ecf2 333 dsi_0: dsi@11c80000 {
025d8e13
ID		 334 compatible = "samsung,exynos3250-mipi-dsi";
335 reg = <0x11C80000 0x10000>;
9645ab2c 336 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
025d8e13 337 samsung,phy-type = <0>;
0da65870 338 power-domains = <&pd_lcd0>;
025d8e13
ID		 339 phys = <&mipi_phy 1>;
340 phy-names = "dsim";
341 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
342 clock-names = "bus_clk", "pll_clk";
343 #address-cells = <1>;
344 #size-cells = <0>;
345 status = "disabled";
346 };
347
3be1ecf2 348 sysmmu_fimd0: sysmmu@11e20000 {
f5976ce5
MS		 349 compatible = "samsung,exynos-sysmmu";
350 reg = <0x11e20000 0x1000>;
9645ab2c
KK		 351 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
f5976ce5
MS		 353 clock-names = "sysmmu", "master";
354 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
355 power-domains = <&pd_lcd0>;
356 #iommu-cells = <0>;
357 };
358
e0c6e929
JK		 359 hsotg: hsotg@12480000 {
360 compatible = "snps,dwc2";
361 reg = <0x12480000 0x20000>;
9645ab2c 362 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
e0c6e929
JK		 363 clocks = <&cmu CLK_USBOTG>;
364 clock-names = "otg";
365 phys = <&exynos_usbphy 0>;
366 phy-names = "usb2-phy";
367 status = "disabled";
368 };
369
5a992a9c 370 mshc_0: mshc@12510000 {
b29dd5fa 371 compatible = "samsung,exynos5420-dw-mshc";
5a992a9c 372 reg = <0x12510000 0x1000>;
9645ab2c 373 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 374 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
375 clock-names = "biu", "ciu";
376 fifo-depth = <0x80>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379 status = "disabled";
380 };
381
382 mshc_1: mshc@12520000 {
b29dd5fa 383 compatible = "samsung,exynos5420-dw-mshc";
5a992a9c 384 reg = <0x12520000 0x1000>;
9645ab2c 385 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 386 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
387 clock-names = "biu", "ciu";
388 fifo-depth = <0x80>;
389 #address-cells = <1>;
390 #size-cells = <0>;
391 status = "disabled";
392 };
393
92173e6a
CC		 394 mshc_2: mshc@12530000 {
395 compatible = "samsung,exynos5250-dw-mshc";
396 reg = <0x12530000 0x1000>;
9645ab2c 397 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
92173e6a
CC		 398 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
399 clock-names = "biu", "ciu";
400 fifo-depth = <0x80>;
401 #address-cells = <1>;
402 #size-cells = <0>;
403 status = "disabled";
404 };
405
3be1ecf2 406 exynos_usbphy: exynos-usbphy@125b0000 {
11ab02b8
JK		 407 compatible = "samsung,exynos3250-usb2-phy";
408 reg = <0x125B0000 0x100>;
409 samsung,pmureg-phandle = <&pmu_system_controller>;
410 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
411 clock-names = "phy", "ref";
412 #phy-cells = <1>;
413 status = "disabled";
414 };
415
5a992a9c 416 amba {
2ef7d5f3 417 compatible = "simple-bus";
5a992a9c
TF		 418 #address-cells = <1>;
419 #size-cells = <1>;
5a992a9c
TF		 420 ranges;
421
422 pdma0: pdma@12680000 {
423 compatible = "arm,pl330", "arm,primecell";
424 reg = <0x12680000 0x1000>;
9645ab2c 425 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 426 clocks = <&cmu CLK_PDMA0>;
427 clock-names = "apb_pclk";
428 #dma-cells = <1>;
429 #dma-channels = <8>;
430 #dma-requests = <32>;
431 };
432
433 pdma1: pdma@12690000 {
434 compatible = "arm,pl330", "arm,primecell";
435 reg = <0x12690000 0x1000>;
9645ab2c 436 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 437 clocks = <&cmu CLK_PDMA1>;
438 clock-names = "apb_pclk";
439 #dma-cells = <1>;
440 #dma-channels = <8>;
441 #dma-requests = <32>;
442 };
443 };
444
3be1ecf2 445 adc: adc@126c0000 {
e6ca2d84
CC		 446 compatible = "samsung,exynos3250-adc",
447 "samsung,exynos-adc-v2";
db9bf4d6 448 reg = <0x126C0000 0x100>;
9645ab2c 449 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
e6ca2d84 450 clock-names = "adc", "sclk";
5a992a9c
TF		 451 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
452 #io-channel-cells = <1>;
453 io-channel-ranges;
db9bf4d6 454 samsung,syscon-phandle = <&pmu_system_controller>;
5a992a9c
TF		 455 status = "disabled";
456 };
457
752d3a23
JA		 458 mfc: codec@13400000 {
459 compatible = "samsung,mfc-v7";
460 reg = <0x13400000 0x10000>;
9645ab2c 461 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
752d3a23
JA		 462 clock-names = "mfc", "sclk_mfc";
463 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
0da65870 464 power-domains = <&pd_mfc>;
f5976ce5 465 iommus = <&sysmmu_mfc>;
752d3a23
JA		 466 };
467
f5976ce5
MS		 468 sysmmu_mfc: sysmmu@13620000 {
469 compatible = "samsung,exynos-sysmmu";
470 reg = <0x13620000 0x1000>;
9645ab2c
KK		 471 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
f5976ce5
MS		 473 clock-names = "sysmmu", "master";
474 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
475 power-domains = <&pd_mfc>;
476 #iommu-cells = <0>;
477 };
478
5a992a9c
TF		 479 serial_0: serial@13800000 {
480 compatible = "samsung,exynos4210-uart";
481 reg = <0x13800000 0x100>;
9645ab2c 482 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 483 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
484 clock-names = "uart", "clk_uart_baud0";
a9408a6b
CC		 485 pinctrl-names = "default";
486 pinctrl-0 = <&uart0_data &uart0_fctl>;
5a992a9c
TF		 487 status = "disabled";
488 };
489
490 serial_1: serial@13810000 {
491 compatible = "samsung,exynos4210-uart";
492 reg = <0x13810000 0x100>;
9645ab2c 493 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 494 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
495 clock-names = "uart", "clk_uart_baud0";
a9408a6b
CC		 496 pinctrl-names = "default";
497 pinctrl-0 = <&uart1_data>;
5a992a9c
TF		 498 status = "disabled";
499 };
500
ecaba514
PD		 501 serial_2: serial@13820000 {
502 compatible = "samsung,exynos4210-uart";
503 reg = <0x13820000 0x100>;
9645ab2c 504 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
ecaba514
PD		 505 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
506 clock-names = "uart", "clk_uart_baud0";
507 pinctrl-names = "default";
508 pinctrl-0 = <&uart2_data>;
509 status = "disabled";
510 };
511
5a992a9c
TF		 512 i2c_0: i2c@13860000 {
513 #address-cells = <1>;
514 #size-cells = <0>;
515 compatible = "samsung,s3c2440-i2c";
516 reg = <0x13860000 0x100>;
9645ab2c 517 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 518 clocks = <&cmu CLK_I2C0>;
519 clock-names = "i2c";
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c0_bus>;
522 status = "disabled";
523 };
524
525 i2c_1: i2c@13870000 {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 compatible = "samsung,s3c2440-i2c";
529 reg = <0x13870000 0x100>;
9645ab2c 530 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 531 clocks = <&cmu CLK_I2C1>;
532 clock-names = "i2c";
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c1_bus>;
535 status = "disabled";
536 };
537
538 i2c_2: i2c@13880000 {
539 #address-cells = <1>;
540 #size-cells = <0>;
541 compatible = "samsung,s3c2440-i2c";
542 reg = <0x13880000 0x100>;
9645ab2c 543 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 544 clocks = <&cmu CLK_I2C2>;
545 clock-names = "i2c";
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c2_bus>;
548 status = "disabled";
549 };
550
551 i2c_3: i2c@13890000 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "samsung,s3c2440-i2c";
555 reg = <0x13890000 0x100>;
9645ab2c 556 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 557 clocks = <&cmu CLK_I2C3>;
558 clock-names = "i2c";
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c3_bus>;
561 status = "disabled";
562 };
563
3be1ecf2 564 i2c_4: i2c@138a0000 {
5a992a9c
TF		 565 #address-cells = <1>;
566 #size-cells = <0>;
567 compatible = "samsung,s3c2440-i2c";
568 reg = <0x138A0000 0x100>;
9645ab2c 569 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 570 clocks = <&cmu CLK_I2C4>;
571 clock-names = "i2c";
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c4_bus>;
574 status = "disabled";
575 };
576
3be1ecf2 577 i2c_5: i2c@138b0000 {
5a992a9c
TF		 578 #address-cells = <1>;
579 #size-cells = <0>;
580 compatible = "samsung,s3c2440-i2c";
581 reg = <0x138B0000 0x100>;
9645ab2c 582 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 583 clocks = <&cmu CLK_I2C5>;
584 clock-names = "i2c";
585 pinctrl-names = "default";
586 pinctrl-0 = <&i2c5_bus>;
587 status = "disabled";
588 };
589
3be1ecf2 590 i2c_6: i2c@138c0000 {
5a992a9c
TF		 591 #address-cells = <1>;
592 #size-cells = <0>;
593 compatible = "samsung,s3c2440-i2c";
594 reg = <0x138C0000 0x100>;
9645ab2c 595 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 596 clocks = <&cmu CLK_I2C6>;
597 clock-names = "i2c";
598 pinctrl-names = "default";
599 pinctrl-0 = <&i2c6_bus>;
600 status = "disabled";
601 };
602
3be1ecf2 603 i2c_7: i2c@138d0000 {
5a992a9c
TF		 604 #address-cells = <1>;
605 #size-cells = <0>;
606 compatible = "samsung,s3c2440-i2c";
607 reg = <0x138D0000 0x100>;
9645ab2c 608 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 609 clocks = <&cmu CLK_I2C7>;
610 clock-names = "i2c";
611 pinctrl-names = "default";
612 pinctrl-0 = <&i2c7_bus>;
613 status = "disabled";
614 };
615
616 spi_0: spi@13920000 {
617 compatible = "samsung,exynos4210-spi";
618 reg = <0x13920000 0x100>;
9645ab2c 619 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 620 dmas = <&pdma0 7>, <&pdma0 6>;
621 dma-names = "tx", "rx";
622 #address-cells = <1>;
623 #size-cells = <0>;
624 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
625 clock-names = "spi", "spi_busclk0";
626 samsung,spi-src-clk = <0>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&spi0_bus>;
629 status = "disabled";
630 };
631
632 spi_1: spi@13930000 {
633 compatible = "samsung,exynos4210-spi";
634 reg = <0x13930000 0x100>;
9645ab2c 635 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 636 dmas = <&pdma1 7>, <&pdma1 6>;
637 dma-names = "tx", "rx";
638 #address-cells = <1>;
639 #size-cells = <0>;
640 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
641 clock-names = "spi", "spi_busclk0";
642 samsung,spi-src-clk = <0>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&spi1_bus>;
645 status = "disabled";
646 };
647
ccaba452
TF		 648 i2s2: i2s@13970000 {
649 compatible = "samsung,s3c6410-i2s";
650 reg = <0x13970000 0x100>;
9645ab2c 651 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
ccaba452
TF		 652 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
653 clock-names = "iis", "i2s_opclk0";
654 dmas = <&pdma0 14>, <&pdma0 13>;
655 dma-names = "tx", "rx";
656 pinctrl-0 = <&i2s2_bus>;
657 pinctrl-names = "default";
658 status = "disabled";
659 };
660
3be1ecf2 661 pwm: pwm@139d0000 {
5a992a9c
TF		 662 compatible = "samsung,exynos4210-pwm";
663 reg = <0x139D0000 0x1000>;
9645ab2c
KK		 664 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c
TF		 669 #pwm-cells = <3>;
670 status = "disabled";
671 };
672
673 pmu {
674 compatible = "arm,cortex-a7-pmu";
9645ab2c
KK		 675 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5a992a9c 677 };
e4502367
CC		 678
679 ppmu_dmc0: ppmu_dmc0@106a0000 {
680 compatible = "samsung,exynos-ppmu";
681 reg = <0x106a0000 0x2000>;
682 status = "disabled";
683 };
684
685 ppmu_dmc1: ppmu_dmc1@106b0000 {
686 compatible = "samsung,exynos-ppmu";
687 reg = <0x106b0000 0x2000>;
688 status = "disabled";
689 };
690
691 ppmu_cpu: ppmu_cpu@106c0000 {
692 compatible = "samsung,exynos-ppmu";
693 reg = <0x106c0000 0x2000>;
694 status = "disabled";
695 };
696
697 ppmu_rightbus: ppmu_rightbus@112a0000 {
698 compatible = "samsung,exynos-ppmu";
699 reg = <0x112a0000 0x2000>;
700 clocks = <&cmu CLK_PPMURIGHT>;
701 clock-names = "ppmu";
702 status = "disabled";
703 };
704
705 ppmu_leftbus: ppmu_leftbus0@116a0000 {
706 compatible = "samsung,exynos-ppmu";
707 reg = <0x116a0000 0x2000>;
708 clocks = <&cmu CLK_PPMULEFT>;
709 clock-names = "ppmu";
710 status = "disabled";
711 };
712
713 ppmu_camif: ppmu_camif@11ac0000 {
714 compatible = "samsung,exynos-ppmu";
715 reg = <0x11ac0000 0x2000>;
716 clocks = <&cmu CLK_PPMUCAMIF>;
717 clock-names = "ppmu";
718 status = "disabled";
719 };
720
721 ppmu_lcd0: ppmu_lcd0@11e40000 {
722 compatible = "samsung,exynos-ppmu";
723 reg = <0x11e40000 0x2000>;
724 clocks = <&cmu CLK_PPMULCD0>;
725 clock-names = "ppmu";
726 status = "disabled";
727 };
728
729 ppmu_fsys: ppmu_fsys@12630000 {
730 compatible = "samsung,exynos-ppmu";
731 reg = <0x12630000 0x2000>;
732 clocks = <&cmu CLK_PPMUFILE>;
733 clock-names = "ppmu";
734 status = "disabled";
735 };
736
737 ppmu_g3d: ppmu_g3d@13220000 {
738 compatible = "samsung,exynos-ppmu";
739 reg = <0x13220000 0x2000>;
740 clocks = <&cmu CLK_PPMUG3D>;
741 clock-names = "ppmu";
742 status = "disabled";
743 };
744
745 ppmu_mfc: ppmu_mfc@13660000 {
746 compatible = "samsung,exynos-ppmu";
747 reg = <0x13660000 0x2000>;
748 clocks = <&cmu CLK_PPMUMFC_L>;
749 clock-names = "ppmu";
750 status = "disabled";
751 };
6b088a62
CC		 752
753 bus_dmc: bus_dmc {
754 compatible = "samsung,exynos-bus";
755 clocks = <&cmu_dmc CLK_DIV_DMC>;
756 clock-names = "bus";
757 operating-points-v2 = <&bus_dmc_opp_table>;
758 status = "disabled";
759 };
760
761 bus_dmc_opp_table: opp_table1 {
762 compatible = "operating-points-v2";
763 opp-shared;
764
6a611d14 765 opp-50000000 {
6b088a62
CC		 766 opp-hz = /bits/ 64 <50000000>;
767 opp-microvolt = <800000>;
768 };
6a611d14 769 opp-100000000 {
6b088a62
CC		 770 opp-hz = /bits/ 64 <100000000>;
771 opp-microvolt = <800000>;
772 };
6a611d14 773 opp-134000000 {
6b088a62
CC		 774 opp-hz = /bits/ 64 <134000000>;
775 opp-microvolt = <800000>;
776 };
6a611d14 777 opp-200000000 {
6b088a62
CC		 778 opp-hz = /bits/ 64 <200000000>;
779 opp-microvolt = <825000>;
780 };
6a611d14 781 opp-400000000 {
6b088a62
CC		 782 opp-hz = /bits/ 64 <400000000>;
783 opp-microvolt = <875000>;
784 };
785 };
304d10ab
CC		 786
787 bus_leftbus: bus_leftbus {
788 compatible = "samsung,exynos-bus";
789 clocks = <&cmu CLK_DIV_GDL>;
790 clock-names = "bus";
791 operating-points-v2 = <&bus_leftbus_opp_table>;
792 status = "disabled";
793 };
794
795 bus_rightbus: bus_rightbus {
796 compatible = "samsung,exynos-bus";
797 clocks = <&cmu CLK_DIV_GDR>;
798 clock-names = "bus";
799 operating-points-v2 = <&bus_leftbus_opp_table>;
800 status = "disabled";
801 };
802
803 bus_lcd0: bus_lcd0 {
804 compatible = "samsung,exynos-bus";
805 clocks = <&cmu CLK_DIV_ACLK_160>;
806 clock-names = "bus";
807 operating-points-v2 = <&bus_leftbus_opp_table>;
808 status = "disabled";
809 };
810
811 bus_fsys: bus_fsys {
812 compatible = "samsung,exynos-bus";
813 clocks = <&cmu CLK_DIV_ACLK_200>;
814 clock-names = "bus";
815 operating-points-v2 = <&bus_leftbus_opp_table>;
816 status = "disabled";
817 };
818
819 bus_mcuisp: bus_mcuisp {
820 compatible = "samsung,exynos-bus";
821 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
822 clock-names = "bus";
823 operating-points-v2 = <&bus_mcuisp_opp_table>;
824 status = "disabled";
825 };
826
827 bus_isp: bus_isp {
828 compatible = "samsung,exynos-bus";
829 clocks = <&cmu CLK_DIV_ACLK_266>;
830 clock-names = "bus";
831 operating-points-v2 = <&bus_isp_opp_table>;
832 status = "disabled";
833 };
834
835 bus_peril: bus_peril {
836 compatible = "samsung,exynos-bus";
837 clocks = <&cmu CLK_DIV_ACLK_100>;
838 clock-names = "bus";
839 operating-points-v2 = <&bus_peril_opp_table>;
840 status = "disabled";
841 };
842
843 bus_mfc: bus_mfc {
844 compatible = "samsung,exynos-bus";
845 clocks = <&cmu CLK_SCLK_MFC>;
846 clock-names = "bus";
847 operating-points-v2 = <&bus_leftbus_opp_table>;
848 status = "disabled";
849 };
850
851 bus_leftbus_opp_table: opp_table2 {
852 compatible = "operating-points-v2";
853 opp-shared;
854
6a611d14 855 opp-50000000 {
304d10ab
CC		 856 opp-hz = /bits/ 64 <50000000>;
857 opp-microvolt = <900000>;
858 };
6a611d14 859 opp-80000000 {
304d10ab
CC		 860 opp-hz = /bits/ 64 <80000000>;
861 opp-microvolt = <900000>;
862 };
6a611d14 863 opp-100000000 {
304d10ab
CC		 864 opp-hz = /bits/ 64 <100000000>;
865 opp-microvolt = <1000000>;
866 };
6a611d14 867 opp-134000000 {
304d10ab
CC		 868 opp-hz = /bits/ 64 <134000000>;
869 opp-microvolt = <1000000>;
870 };
6a611d14 871 opp-200000000 {
304d10ab
CC		 872 opp-hz = /bits/ 64 <200000000>;
873 opp-microvolt = <1000000>;
874 };
875 };
876
877 bus_mcuisp_opp_table: opp_table3 {
878 compatible = "operating-points-v2";
879 opp-shared;
880
6a611d14 881 opp-50000000 {
304d10ab
CC		 882 opp-hz = /bits/ 64 <50000000>;
883 };
6a611d14 884 opp-80000000 {
304d10ab
CC		 885 opp-hz = /bits/ 64 <80000000>;
886 };
6a611d14 887 opp-100000000 {
304d10ab
CC		 888 opp-hz = /bits/ 64 <100000000>;
889 };
6a611d14 890 opp-200000000 {
304d10ab
CC		 891 opp-hz = /bits/ 64 <200000000>;
892 };
6a611d14 893 opp-400000000 {
304d10ab
CC		 894 opp-hz = /bits/ 64 <400000000>;
895 };
896 };
897
898 bus_isp_opp_table: opp_table4 {
899 compatible = "operating-points-v2";
900 opp-shared;
901
6a611d14 902 opp-50000000 {
304d10ab
CC		 903 opp-hz = /bits/ 64 <50000000>;
904 };
6a611d14 905 opp-80000000 {
304d10ab
CC		 906 opp-hz = /bits/ 64 <80000000>;
907 };
6a611d14 908 opp-100000000 {
304d10ab
CC		 909 opp-hz = /bits/ 64 <100000000>;
910 };
6a611d14 911 opp-200000000 {
304d10ab
CC		 912 opp-hz = /bits/ 64 <200000000>;
913 };
6a611d14 914 opp-300000000 {
304d10ab
CC		 915 opp-hz = /bits/ 64 <300000000>;
916 };
917 };
918
919 bus_peril_opp_table: opp_table5 {
920 compatible = "operating-points-v2";
921 opp-shared;
922
6a611d14 923 opp-50000000 {
304d10ab
CC		 924 opp-hz = /bits/ 64 <50000000>;
925 };
6a611d14 926 opp-80000000 {
304d10ab
CC		 927 opp-hz = /bits/ 64 <80000000>;
928 };
6a611d14 929 opp-100000000 {
304d10ab
CC		 930 opp-hz = /bits/ 64 <100000000>;
931 };
932 };
5a992a9c
TF		 933 };
934};
935
936#include "exynos3250-pinctrl.dtsi"
a03e9dac 937#include "exynos-syscon-restart.dtsi"
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