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cc4637f7 | 1 | // SPDX-License-Identifier: GPL-2.0 |
5a992a9c TF |
2 | /* |
3 | * Samsung's Exynos3250 SoC device tree source | |
4 | * | |
5 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. | |
6 | * http://www.samsung.com | |
7 | * | |
8 | * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 | |
9 | * based board files can include this file and provide values for board specfic | |
10 | * bindings. | |
11 | * | |
12 | * Note: This file does not include device nodes for all the controllers in | |
13 | * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional | |
14 | * nodes can be added to this file. | |
5a992a9c TF |
15 | */ |
16 | ||
9843a223 | 17 | #include "exynos4-cpu-thermal.dtsi" |
5a992a9c | 18 | #include <dt-bindings/clock/exynos3250.h> |
9645ab2c | 19 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
89be8511 | 20 | #include <dt-bindings/interrupt-controller/irq.h> |
5a992a9c TF |
21 | |
22 | / { | |
23 | compatible = "samsung,exynos3250"; | |
24 | interrupt-parent = <&gic>; | |
33c3de7e JMC |
25 | #address-cells = <1>; |
26 | #size-cells = <1>; | |
5a992a9c TF |
27 | |
28 | aliases { | |
29 | pinctrl0 = &pinctrl_0; | |
30 | pinctrl1 = &pinctrl_1; | |
31 | mshc0 = &mshc_0; | |
32 | mshc1 = &mshc_1; | |
92173e6a | 33 | mshc2 = &mshc_2; |
5a992a9c TF |
34 | spi0 = &spi_0; |
35 | spi1 = &spi_1; | |
36 | i2c0 = &i2c_0; | |
37 | i2c1 = &i2c_1; | |
38 | i2c2 = &i2c_2; | |
39 | i2c3 = &i2c_3; | |
40 | i2c4 = &i2c_4; | |
41 | i2c5 = &i2c_5; | |
42 | i2c6 = &i2c_6; | |
43 | i2c7 = &i2c_7; | |
1e64f48e TF |
44 | serial0 = &serial_0; |
45 | serial1 = &serial_1; | |
ecaba514 | 46 | serial2 = &serial_2; |
5a992a9c TF |
47 | }; |
48 | ||
49 | cpus { | |
50 | #address-cells = <1>; | |
51 | #size-cells = <0>; | |
52 | ||
53 | cpu0: cpu@0 { | |
54 | device_type = "cpu"; | |
55 | compatible = "arm,cortex-a7"; | |
56 | reg = <0>; | |
57 | clock-frequency = <1000000000>; | |
48816aff CC |
58 | clocks = <&cmu CLK_ARM_CLK>; |
59 | clock-names = "cpu"; | |
5600f8cc | 60 | #cooling-cells = <2>; |
48816aff CC |
61 | |
62 | operating-points = < | |
63 | 1000000 1150000 | |
64 | 900000 1112500 | |
65 | 800000 1075000 | |
66 | 700000 1037500 | |
67 | 600000 1000000 | |
68 | 500000 962500 | |
69 | 400000 925000 | |
70 | 300000 887500 | |
71 | 200000 850000 | |
72 | 100000 850000 | |
73 | >; | |
5a992a9c TF |
74 | }; |
75 | ||
76 | cpu1: cpu@1 { | |
77 | device_type = "cpu"; | |
78 | compatible = "arm,cortex-a7"; | |
79 | reg = <1>; | |
80 | clock-frequency = <1000000000>; | |
672f3319 VK |
81 | clocks = <&cmu CLK_ARM_CLK>; |
82 | clock-names = "cpu"; | |
83 | #cooling-cells = <2>; | |
84 | ||
85 | operating-points = < | |
86 | 1000000 1150000 | |
87 | 900000 1112500 | |
88 | 800000 1075000 | |
89 | 700000 1037500 | |
90 | 600000 1000000 | |
91 | 500000 962500 | |
92 | 400000 925000 | |
93 | 300000 887500 | |
94 | 200000 850000 | |
95 | 100000 850000 | |
96 | >; | |
5a992a9c TF |
97 | }; |
98 | }; | |
99 | ||
100 | soc: soc { | |
101 | compatible = "simple-bus"; | |
102 | #address-cells = <1>; | |
103 | #size-cells = <1>; | |
104 | ranges; | |
105 | ||
106 | fixed-rate-clocks { | |
107 | #address-cells = <1>; | |
108 | #size-cells = <0>; | |
109 | ||
110 | xusbxti: clock@0 { | |
111 | compatible = "fixed-clock"; | |
112 | #address-cells = <1>; | |
113 | #size-cells = <0>; | |
114 | reg = <0>; | |
115 | clock-frequency = <0>; | |
116 | #clock-cells = <0>; | |
117 | clock-output-names = "xusbxti"; | |
118 | }; | |
119 | ||
120 | xxti: clock@1 { | |
121 | compatible = "fixed-clock"; | |
122 | reg = <1>; | |
123 | clock-frequency = <0>; | |
124 | #clock-cells = <0>; | |
125 | clock-output-names = "xxti"; | |
126 | }; | |
127 | ||
128 | xtcxo: clock@2 { | |
129 | compatible = "fixed-clock"; | |
130 | reg = <2>; | |
131 | clock-frequency = <0>; | |
132 | #clock-cells = <0>; | |
133 | clock-output-names = "xtcxo"; | |
134 | }; | |
135 | }; | |
136 | ||
8dccafaa | 137 | sysram@2020000 { |
5a992a9c TF |
138 | compatible = "mmio-sram"; |
139 | reg = <0x02020000 0x40000>; | |
140 | #address-cells = <1>; | |
141 | #size-cells = <1>; | |
142 | ranges = <0 0x02020000 0x40000>; | |
143 | ||
144 | smp-sysram@0 { | |
145 | compatible = "samsung,exynos4210-sysram"; | |
146 | reg = <0x0 0x1000>; | |
147 | }; | |
148 | ||
149 | smp-sysram@3f000 { | |
150 | compatible = "samsung,exynos4210-sysram-ns"; | |
151 | reg = <0x3f000 0x1000>; | |
152 | }; | |
153 | }; | |
154 | ||
155 | chipid@10000000 { | |
156 | compatible = "samsung,exynos4210-chipid"; | |
157 | reg = <0x10000000 0x100>; | |
158 | }; | |
159 | ||
160 | sys_reg: syscon@10010000 { | |
161 | compatible = "samsung,exynos3-sysreg", "syscon"; | |
162 | reg = <0x10010000 0x400>; | |
163 | }; | |
164 | ||
25023926 CC |
165 | pmu_system_controller: system-controller@10020000 { |
166 | compatible = "samsung,exynos3250-pmu", "syscon"; | |
167 | reg = <0x10020000 0x4000>; | |
8b283c02 MZ |
168 | interrupt-controller; |
169 | #interrupt-cells = <3>; | |
170 | interrupt-parent = <&gic>; | |
a66352e0 MS |
171 | clock-names = "clkout8"; |
172 | clocks = <&cmu CLK_FIN_PLL>; | |
173 | #clock-cells = <1>; | |
25023926 CC |
174 | }; |
175 | ||
bb72cade | 176 | mipi_phy: video-phy { |
9fab9d6a | 177 | compatible = "samsung,s5pv210-mipi-video-phy"; |
9fab9d6a | 178 | #phy-cells = <1>; |
1342ff45 | 179 | syscon = <&pmu_system_controller>; |
9fab9d6a ID |
180 | }; |
181 | ||
6891227b | 182 | pd_cam: power-domain@10023c00 { |
5a992a9c TF |
183 | compatible = "samsung,exynos4210-pd"; |
184 | reg = <0x10023C00 0x20>; | |
0da65870 | 185 | #power-domain-cells = <0>; |
6891227b | 186 | label = "CAM"; |
5a992a9c TF |
187 | }; |
188 | ||
6891227b | 189 | pd_mfc: power-domain@10023c40 { |
5a992a9c TF |
190 | compatible = "samsung,exynos4210-pd"; |
191 | reg = <0x10023C40 0x20>; | |
0da65870 | 192 | #power-domain-cells = <0>; |
6891227b | 193 | label = "MFC"; |
5a992a9c TF |
194 | }; |
195 | ||
6891227b | 196 | pd_g3d: power-domain@10023c60 { |
5a992a9c TF |
197 | compatible = "samsung,exynos4210-pd"; |
198 | reg = <0x10023C60 0x20>; | |
0da65870 | 199 | #power-domain-cells = <0>; |
6891227b | 200 | label = "G3D"; |
5a992a9c TF |
201 | }; |
202 | ||
6891227b | 203 | pd_lcd0: power-domain@10023c80 { |
5a992a9c TF |
204 | compatible = "samsung,exynos4210-pd"; |
205 | reg = <0x10023C80 0x20>; | |
0da65870 | 206 | #power-domain-cells = <0>; |
6891227b | 207 | label = "LCD0"; |
5a992a9c TF |
208 | }; |
209 | ||
6891227b | 210 | pd_isp: power-domain@10023ca0 { |
5a992a9c TF |
211 | compatible = "samsung,exynos4210-pd"; |
212 | reg = <0x10023CA0 0x20>; | |
0da65870 | 213 | #power-domain-cells = <0>; |
6891227b | 214 | label = "ISP"; |
5a992a9c TF |
215 | }; |
216 | ||
217 | cmu: clock-controller@10030000 { | |
218 | compatible = "samsung,exynos3250-cmu"; | |
219 | reg = <0x10030000 0x20000>; | |
220 | #clock-cells = <1>; | |
52005dec BM |
221 | assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, |
222 | <&cmu CLK_MOUT_ACLK_266_SUB>; | |
223 | assigned-clock-parents = <&cmu CLK_FIN_PLL>, | |
224 | <&cmu CLK_FIN_PLL>; | |
5a992a9c TF |
225 | }; |
226 | ||
3be1ecf2 | 227 | cmu_dmc: clock-controller@105c0000 { |
d0e73eaf KK |
228 | compatible = "samsung,exynos3250-cmu-dmc"; |
229 | reg = <0x105C0000 0x2000>; | |
230 | #clock-cells = <1>; | |
231 | }; | |
232 | ||
5a992a9c | 233 | rtc: rtc@10070000 { |
062f49c4 | 234 | compatible = "samsung,s3c6410-rtc"; |
5a992a9c | 235 | reg = <0x10070000 0x100>; |
9645ab2c KK |
236 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
237 | <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
8b283c02 | 238 | interrupt-parent = <&pmu_system_controller>; |
5a992a9c TF |
239 | status = "disabled"; |
240 | }; | |
241 | ||
3be1ecf2 | 242 | tmu: tmu@100c0000 { |
9dfb3347 CC |
243 | compatible = "samsung,exynos3250-tmu"; |
244 | reg = <0x100C0000 0x100>; | |
9645ab2c | 245 | interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; |
9dfb3347 CC |
246 | clocks = <&cmu CLK_TMU_APBIF>; |
247 | clock-names = "tmu_apbif"; | |
c05b799e | 248 | #thermal-sensor-cells = <0>; |
9dfb3347 CC |
249 | status = "disabled"; |
250 | }; | |
251 | ||
5a992a9c TF |
252 | gic: interrupt-controller@10481000 { |
253 | compatible = "arm,cortex-a15-gic"; | |
254 | #interrupt-cells = <3>; | |
255 | interrupt-controller; | |
256 | reg = <0x10481000 0x1000>, | |
387720c9 | 257 | <0x10482000 0x2000>, |
5a992a9c TF |
258 | <0x10484000 0x2000>, |
259 | <0x10486000 0x2000>; | |
9645ab2c KK |
260 | interrupts = <GIC_PPI 9 |
261 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
5a992a9c TF |
262 | }; |
263 | ||
264 | mct@10050000 { | |
265 | compatible = "samsung,exynos4210-mct"; | |
266 | reg = <0x10050000 0x800>; | |
9645ab2c KK |
267 | interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, |
268 | <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, | |
269 | <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, | |
270 | <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, | |
271 | <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, | |
272 | <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, | |
273 | <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, | |
274 | <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; | |
5a992a9c TF |
275 | clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; |
276 | clock-names = "fin_pll", "mct"; | |
277 | }; | |
278 | ||
279 | pinctrl_1: pinctrl@11000000 { | |
280 | compatible = "samsung,exynos3250-pinctrl"; | |
281 | reg = <0x11000000 0x1000>; | |
9645ab2c | 282 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
283 | |
284 | wakeup-interrupt-controller { | |
285 | compatible = "samsung,exynos4210-wakeup-eint"; | |
9645ab2c | 286 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
287 | }; |
288 | }; | |
289 | ||
290 | pinctrl_0: pinctrl@11400000 { | |
291 | compatible = "samsung,exynos3250-pinctrl"; | |
292 | reg = <0x11400000 0x1000>; | |
9645ab2c | 293 | interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
294 | }; |
295 | ||
c9c1adfe JA |
296 | jpeg: codec@11830000 { |
297 | compatible = "samsung,exynos3250-jpeg"; | |
298 | reg = <0x11830000 0x1000>; | |
9645ab2c | 299 | interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; |
c9c1adfe JA |
300 | clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; |
301 | clock-names = "jpeg", "sclk"; | |
302 | power-domains = <&pd_cam>; | |
303 | assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; | |
304 | assigned-clock-rates = <0>, <150000000>; | |
305 | assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; | |
f5976ce5 | 306 | iommus = <&sysmmu_jpeg>; |
c9c1adfe JA |
307 | status = "disabled"; |
308 | }; | |
309 | ||
3be1ecf2 | 310 | sysmmu_jpeg: sysmmu@11a60000 { |
f5976ce5 MS |
311 | compatible = "samsung,exynos-sysmmu"; |
312 | reg = <0x11a60000 0x1000>; | |
9645ab2c KK |
313 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, |
314 | <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; | |
f5976ce5 MS |
315 | clock-names = "sysmmu", "master"; |
316 | clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; | |
317 | power-domains = <&pd_cam>; | |
318 | #iommu-cells = <0>; | |
319 | }; | |
320 | ||
03b86c79 ID |
321 | fimd: fimd@11c00000 { |
322 | compatible = "samsung,exynos3250-fimd"; | |
323 | reg = <0x11c00000 0x30000>; | |
324 | interrupt-names = "fifo", "vsync", "lcd_sys"; | |
9645ab2c KK |
325 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, |
326 | <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, | |
327 | <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
03b86c79 ID |
328 | clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; |
329 | clock-names = "sclk_fimd", "fimd"; | |
0da65870 | 330 | power-domains = <&pd_lcd0>; |
f5976ce5 | 331 | iommus = <&sysmmu_fimd0>; |
03b86c79 ID |
332 | samsung,sysreg = <&sys_reg>; |
333 | status = "disabled"; | |
334 | }; | |
335 | ||
3be1ecf2 | 336 | dsi_0: dsi@11c80000 { |
025d8e13 ID |
337 | compatible = "samsung,exynos3250-mipi-dsi"; |
338 | reg = <0x11C80000 0x10000>; | |
9645ab2c | 339 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
025d8e13 | 340 | samsung,phy-type = <0>; |
0da65870 | 341 | power-domains = <&pd_lcd0>; |
025d8e13 ID |
342 | phys = <&mipi_phy 1>; |
343 | phy-names = "dsim"; | |
344 | clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; | |
345 | clock-names = "bus_clk", "pll_clk"; | |
346 | #address-cells = <1>; | |
347 | #size-cells = <0>; | |
348 | status = "disabled"; | |
349 | }; | |
350 | ||
3be1ecf2 | 351 | sysmmu_fimd0: sysmmu@11e20000 { |
f5976ce5 MS |
352 | compatible = "samsung,exynos-sysmmu"; |
353 | reg = <0x11e20000 0x1000>; | |
9645ab2c KK |
354 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, |
355 | <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
f5976ce5 MS |
356 | clock-names = "sysmmu", "master"; |
357 | clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; | |
358 | power-domains = <&pd_lcd0>; | |
359 | #iommu-cells = <0>; | |
360 | }; | |
361 | ||
e0c6e929 | 362 | hsotg: hsotg@12480000 { |
6035cbcc | 363 | compatible = "samsung,s3c6400-hsotg", "snps,dwc2"; |
e0c6e929 | 364 | reg = <0x12480000 0x20000>; |
9645ab2c | 365 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
e0c6e929 JK |
366 | clocks = <&cmu CLK_USBOTG>; |
367 | clock-names = "otg"; | |
368 | phys = <&exynos_usbphy 0>; | |
369 | phy-names = "usb2-phy"; | |
370 | status = "disabled"; | |
371 | }; | |
372 | ||
5a992a9c | 373 | mshc_0: mshc@12510000 { |
b29dd5fa | 374 | compatible = "samsung,exynos5420-dw-mshc"; |
5a992a9c | 375 | reg = <0x12510000 0x1000>; |
9645ab2c | 376 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
377 | clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; |
378 | clock-names = "biu", "ciu"; | |
379 | fifo-depth = <0x80>; | |
380 | #address-cells = <1>; | |
381 | #size-cells = <0>; | |
382 | status = "disabled"; | |
383 | }; | |
384 | ||
385 | mshc_1: mshc@12520000 { | |
b29dd5fa | 386 | compatible = "samsung,exynos5420-dw-mshc"; |
5a992a9c | 387 | reg = <0x12520000 0x1000>; |
9645ab2c | 388 | interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
389 | clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; |
390 | clock-names = "biu", "ciu"; | |
391 | fifo-depth = <0x80>; | |
392 | #address-cells = <1>; | |
393 | #size-cells = <0>; | |
394 | status = "disabled"; | |
395 | }; | |
396 | ||
92173e6a CC |
397 | mshc_2: mshc@12530000 { |
398 | compatible = "samsung,exynos5250-dw-mshc"; | |
399 | reg = <0x12530000 0x1000>; | |
9645ab2c | 400 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
92173e6a CC |
401 | clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; |
402 | clock-names = "biu", "ciu"; | |
403 | fifo-depth = <0x80>; | |
404 | #address-cells = <1>; | |
405 | #size-cells = <0>; | |
406 | status = "disabled"; | |
407 | }; | |
408 | ||
3be1ecf2 | 409 | exynos_usbphy: exynos-usbphy@125b0000 { |
11ab02b8 JK |
410 | compatible = "samsung,exynos3250-usb2-phy"; |
411 | reg = <0x125B0000 0x100>; | |
412 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
413 | clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; | |
414 | clock-names = "phy", "ref"; | |
415 | #phy-cells = <1>; | |
416 | status = "disabled"; | |
417 | }; | |
418 | ||
5a992a9c | 419 | amba { |
2ef7d5f3 | 420 | compatible = "simple-bus"; |
5a992a9c TF |
421 | #address-cells = <1>; |
422 | #size-cells = <1>; | |
5a992a9c TF |
423 | ranges; |
424 | ||
425 | pdma0: pdma@12680000 { | |
426 | compatible = "arm,pl330", "arm,primecell"; | |
427 | reg = <0x12680000 0x1000>; | |
9645ab2c | 428 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
429 | clocks = <&cmu CLK_PDMA0>; |
430 | clock-names = "apb_pclk"; | |
431 | #dma-cells = <1>; | |
432 | #dma-channels = <8>; | |
433 | #dma-requests = <32>; | |
434 | }; | |
435 | ||
436 | pdma1: pdma@12690000 { | |
437 | compatible = "arm,pl330", "arm,primecell"; | |
438 | reg = <0x12690000 0x1000>; | |
9645ab2c | 439 | interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
440 | clocks = <&cmu CLK_PDMA1>; |
441 | clock-names = "apb_pclk"; | |
442 | #dma-cells = <1>; | |
443 | #dma-channels = <8>; | |
444 | #dma-requests = <32>; | |
445 | }; | |
446 | }; | |
447 | ||
3be1ecf2 | 448 | adc: adc@126c0000 { |
e6ca2d84 CC |
449 | compatible = "samsung,exynos3250-adc", |
450 | "samsung,exynos-adc-v2"; | |
db9bf4d6 | 451 | reg = <0x126C0000 0x100>; |
9645ab2c | 452 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
e6ca2d84 | 453 | clock-names = "adc", "sclk"; |
5a992a9c TF |
454 | clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; |
455 | #io-channel-cells = <1>; | |
456 | io-channel-ranges; | |
db9bf4d6 | 457 | samsung,syscon-phandle = <&pmu_system_controller>; |
5a992a9c TF |
458 | status = "disabled"; |
459 | }; | |
460 | ||
752d3a23 JA |
461 | mfc: codec@13400000 { |
462 | compatible = "samsung,mfc-v7"; | |
463 | reg = <0x13400000 0x10000>; | |
9645ab2c | 464 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
752d3a23 JA |
465 | clock-names = "mfc", "sclk_mfc"; |
466 | clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; | |
0da65870 | 467 | power-domains = <&pd_mfc>; |
f5976ce5 | 468 | iommus = <&sysmmu_mfc>; |
752d3a23 JA |
469 | }; |
470 | ||
f5976ce5 MS |
471 | sysmmu_mfc: sysmmu@13620000 { |
472 | compatible = "samsung,exynos-sysmmu"; | |
473 | reg = <0x13620000 0x1000>; | |
9645ab2c KK |
474 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, |
475 | <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
f5976ce5 MS |
476 | clock-names = "sysmmu", "master"; |
477 | clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; | |
478 | power-domains = <&pd_mfc>; | |
479 | #iommu-cells = <0>; | |
480 | }; | |
481 | ||
5a992a9c TF |
482 | serial_0: serial@13800000 { |
483 | compatible = "samsung,exynos4210-uart"; | |
484 | reg = <0x13800000 0x100>; | |
9645ab2c | 485 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
486 | clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; |
487 | clock-names = "uart", "clk_uart_baud0"; | |
a9408a6b CC |
488 | pinctrl-names = "default"; |
489 | pinctrl-0 = <&uart0_data &uart0_fctl>; | |
5a992a9c TF |
490 | status = "disabled"; |
491 | }; | |
492 | ||
493 | serial_1: serial@13810000 { | |
494 | compatible = "samsung,exynos4210-uart"; | |
495 | reg = <0x13810000 0x100>; | |
9645ab2c | 496 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
497 | clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; |
498 | clock-names = "uart", "clk_uart_baud0"; | |
a9408a6b CC |
499 | pinctrl-names = "default"; |
500 | pinctrl-0 = <&uart1_data>; | |
5a992a9c TF |
501 | status = "disabled"; |
502 | }; | |
503 | ||
ecaba514 PD |
504 | serial_2: serial@13820000 { |
505 | compatible = "samsung,exynos4210-uart"; | |
506 | reg = <0x13820000 0x100>; | |
9645ab2c | 507 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
ecaba514 PD |
508 | clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; |
509 | clock-names = "uart", "clk_uart_baud0"; | |
510 | pinctrl-names = "default"; | |
511 | pinctrl-0 = <&uart2_data>; | |
512 | status = "disabled"; | |
513 | }; | |
514 | ||
5a992a9c TF |
515 | i2c_0: i2c@13860000 { |
516 | #address-cells = <1>; | |
517 | #size-cells = <0>; | |
518 | compatible = "samsung,s3c2440-i2c"; | |
519 | reg = <0x13860000 0x100>; | |
9645ab2c | 520 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
521 | clocks = <&cmu CLK_I2C0>; |
522 | clock-names = "i2c"; | |
523 | pinctrl-names = "default"; | |
524 | pinctrl-0 = <&i2c0_bus>; | |
525 | status = "disabled"; | |
526 | }; | |
527 | ||
528 | i2c_1: i2c@13870000 { | |
529 | #address-cells = <1>; | |
530 | #size-cells = <0>; | |
531 | compatible = "samsung,s3c2440-i2c"; | |
532 | reg = <0x13870000 0x100>; | |
9645ab2c | 533 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
534 | clocks = <&cmu CLK_I2C1>; |
535 | clock-names = "i2c"; | |
536 | pinctrl-names = "default"; | |
537 | pinctrl-0 = <&i2c1_bus>; | |
538 | status = "disabled"; | |
539 | }; | |
540 | ||
541 | i2c_2: i2c@13880000 { | |
542 | #address-cells = <1>; | |
543 | #size-cells = <0>; | |
544 | compatible = "samsung,s3c2440-i2c"; | |
545 | reg = <0x13880000 0x100>; | |
9645ab2c | 546 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
547 | clocks = <&cmu CLK_I2C2>; |
548 | clock-names = "i2c"; | |
549 | pinctrl-names = "default"; | |
550 | pinctrl-0 = <&i2c2_bus>; | |
551 | status = "disabled"; | |
552 | }; | |
553 | ||
554 | i2c_3: i2c@13890000 { | |
555 | #address-cells = <1>; | |
556 | #size-cells = <0>; | |
557 | compatible = "samsung,s3c2440-i2c"; | |
558 | reg = <0x13890000 0x100>; | |
9645ab2c | 559 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
560 | clocks = <&cmu CLK_I2C3>; |
561 | clock-names = "i2c"; | |
562 | pinctrl-names = "default"; | |
563 | pinctrl-0 = <&i2c3_bus>; | |
564 | status = "disabled"; | |
565 | }; | |
566 | ||
3be1ecf2 | 567 | i2c_4: i2c@138a0000 { |
5a992a9c TF |
568 | #address-cells = <1>; |
569 | #size-cells = <0>; | |
570 | compatible = "samsung,s3c2440-i2c"; | |
571 | reg = <0x138A0000 0x100>; | |
9645ab2c | 572 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
573 | clocks = <&cmu CLK_I2C4>; |
574 | clock-names = "i2c"; | |
575 | pinctrl-names = "default"; | |
576 | pinctrl-0 = <&i2c4_bus>; | |
577 | status = "disabled"; | |
578 | }; | |
579 | ||
3be1ecf2 | 580 | i2c_5: i2c@138b0000 { |
5a992a9c TF |
581 | #address-cells = <1>; |
582 | #size-cells = <0>; | |
583 | compatible = "samsung,s3c2440-i2c"; | |
584 | reg = <0x138B0000 0x100>; | |
9645ab2c | 585 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
586 | clocks = <&cmu CLK_I2C5>; |
587 | clock-names = "i2c"; | |
588 | pinctrl-names = "default"; | |
589 | pinctrl-0 = <&i2c5_bus>; | |
590 | status = "disabled"; | |
591 | }; | |
592 | ||
3be1ecf2 | 593 | i2c_6: i2c@138c0000 { |
5a992a9c TF |
594 | #address-cells = <1>; |
595 | #size-cells = <0>; | |
596 | compatible = "samsung,s3c2440-i2c"; | |
597 | reg = <0x138C0000 0x100>; | |
9645ab2c | 598 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
599 | clocks = <&cmu CLK_I2C6>; |
600 | clock-names = "i2c"; | |
601 | pinctrl-names = "default"; | |
602 | pinctrl-0 = <&i2c6_bus>; | |
603 | status = "disabled"; | |
604 | }; | |
605 | ||
3be1ecf2 | 606 | i2c_7: i2c@138d0000 { |
5a992a9c TF |
607 | #address-cells = <1>; |
608 | #size-cells = <0>; | |
609 | compatible = "samsung,s3c2440-i2c"; | |
610 | reg = <0x138D0000 0x100>; | |
9645ab2c | 611 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
612 | clocks = <&cmu CLK_I2C7>; |
613 | clock-names = "i2c"; | |
614 | pinctrl-names = "default"; | |
615 | pinctrl-0 = <&i2c7_bus>; | |
616 | status = "disabled"; | |
617 | }; | |
618 | ||
619 | spi_0: spi@13920000 { | |
620 | compatible = "samsung,exynos4210-spi"; | |
621 | reg = <0x13920000 0x100>; | |
9645ab2c | 622 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
623 | dmas = <&pdma0 7>, <&pdma0 6>; |
624 | dma-names = "tx", "rx"; | |
625 | #address-cells = <1>; | |
626 | #size-cells = <0>; | |
627 | clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; | |
628 | clock-names = "spi", "spi_busclk0"; | |
629 | samsung,spi-src-clk = <0>; | |
630 | pinctrl-names = "default"; | |
631 | pinctrl-0 = <&spi0_bus>; | |
632 | status = "disabled"; | |
633 | }; | |
634 | ||
635 | spi_1: spi@13930000 { | |
636 | compatible = "samsung,exynos4210-spi"; | |
637 | reg = <0x13930000 0x100>; | |
9645ab2c | 638 | interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
5a992a9c TF |
639 | dmas = <&pdma1 7>, <&pdma1 6>; |
640 | dma-names = "tx", "rx"; | |
641 | #address-cells = <1>; | |
642 | #size-cells = <0>; | |
643 | clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; | |
644 | clock-names = "spi", "spi_busclk0"; | |
645 | samsung,spi-src-clk = <0>; | |
646 | pinctrl-names = "default"; | |
647 | pinctrl-0 = <&spi1_bus>; | |
648 | status = "disabled"; | |
649 | }; | |
650 | ||
ccaba452 TF |
651 | i2s2: i2s@13970000 { |
652 | compatible = "samsung,s3c6410-i2s"; | |
653 | reg = <0x13970000 0x100>; | |
9645ab2c | 654 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
ccaba452 TF |
655 | clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; |
656 | clock-names = "iis", "i2s_opclk0"; | |
657 | dmas = <&pdma0 14>, <&pdma0 13>; | |
658 | dma-names = "tx", "rx"; | |
659 | pinctrl-0 = <&i2s2_bus>; | |
660 | pinctrl-names = "default"; | |
661 | status = "disabled"; | |
662 | }; | |
663 | ||
3be1ecf2 | 664 | pwm: pwm@139d0000 { |
5a992a9c TF |
665 | compatible = "samsung,exynos4210-pwm"; |
666 | reg = <0x139D0000 0x1000>; | |
9645ab2c KK |
667 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
668 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
669 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
670 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
671 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
5a992a9c TF |
672 | #pwm-cells = <3>; |
673 | status = "disabled"; | |
674 | }; | |
675 | ||
676 | pmu { | |
677 | compatible = "arm,cortex-a7-pmu"; | |
9645ab2c KK |
678 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
679 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
5a992a9c | 680 | }; |
e4502367 CC |
681 | |
682 | ppmu_dmc0: ppmu_dmc0@106a0000 { | |
683 | compatible = "samsung,exynos-ppmu"; | |
684 | reg = <0x106a0000 0x2000>; | |
685 | status = "disabled"; | |
686 | }; | |
687 | ||
688 | ppmu_dmc1: ppmu_dmc1@106b0000 { | |
689 | compatible = "samsung,exynos-ppmu"; | |
690 | reg = <0x106b0000 0x2000>; | |
691 | status = "disabled"; | |
692 | }; | |
693 | ||
694 | ppmu_cpu: ppmu_cpu@106c0000 { | |
695 | compatible = "samsung,exynos-ppmu"; | |
696 | reg = <0x106c0000 0x2000>; | |
697 | status = "disabled"; | |
698 | }; | |
699 | ||
700 | ppmu_rightbus: ppmu_rightbus@112a0000 { | |
701 | compatible = "samsung,exynos-ppmu"; | |
702 | reg = <0x112a0000 0x2000>; | |
703 | clocks = <&cmu CLK_PPMURIGHT>; | |
704 | clock-names = "ppmu"; | |
705 | status = "disabled"; | |
706 | }; | |
707 | ||
708 | ppmu_leftbus: ppmu_leftbus0@116a0000 { | |
709 | compatible = "samsung,exynos-ppmu"; | |
710 | reg = <0x116a0000 0x2000>; | |
711 | clocks = <&cmu CLK_PPMULEFT>; | |
712 | clock-names = "ppmu"; | |
713 | status = "disabled"; | |
714 | }; | |
715 | ||
716 | ppmu_camif: ppmu_camif@11ac0000 { | |
717 | compatible = "samsung,exynos-ppmu"; | |
718 | reg = <0x11ac0000 0x2000>; | |
719 | clocks = <&cmu CLK_PPMUCAMIF>; | |
720 | clock-names = "ppmu"; | |
721 | status = "disabled"; | |
722 | }; | |
723 | ||
724 | ppmu_lcd0: ppmu_lcd0@11e40000 { | |
725 | compatible = "samsung,exynos-ppmu"; | |
726 | reg = <0x11e40000 0x2000>; | |
727 | clocks = <&cmu CLK_PPMULCD0>; | |
728 | clock-names = "ppmu"; | |
729 | status = "disabled"; | |
730 | }; | |
731 | ||
732 | ppmu_fsys: ppmu_fsys@12630000 { | |
733 | compatible = "samsung,exynos-ppmu"; | |
734 | reg = <0x12630000 0x2000>; | |
735 | clocks = <&cmu CLK_PPMUFILE>; | |
736 | clock-names = "ppmu"; | |
737 | status = "disabled"; | |
738 | }; | |
739 | ||
740 | ppmu_g3d: ppmu_g3d@13220000 { | |
741 | compatible = "samsung,exynos-ppmu"; | |
742 | reg = <0x13220000 0x2000>; | |
743 | clocks = <&cmu CLK_PPMUG3D>; | |
744 | clock-names = "ppmu"; | |
745 | status = "disabled"; | |
746 | }; | |
747 | ||
748 | ppmu_mfc: ppmu_mfc@13660000 { | |
749 | compatible = "samsung,exynos-ppmu"; | |
750 | reg = <0x13660000 0x2000>; | |
751 | clocks = <&cmu CLK_PPMUMFC_L>; | |
752 | clock-names = "ppmu"; | |
753 | status = "disabled"; | |
754 | }; | |
6b088a62 CC |
755 | |
756 | bus_dmc: bus_dmc { | |
757 | compatible = "samsung,exynos-bus"; | |
758 | clocks = <&cmu_dmc CLK_DIV_DMC>; | |
759 | clock-names = "bus"; | |
760 | operating-points-v2 = <&bus_dmc_opp_table>; | |
761 | status = "disabled"; | |
762 | }; | |
763 | ||
764 | bus_dmc_opp_table: opp_table1 { | |
765 | compatible = "operating-points-v2"; | |
766 | opp-shared; | |
767 | ||
6a611d14 | 768 | opp-50000000 { |
6b088a62 CC |
769 | opp-hz = /bits/ 64 <50000000>; |
770 | opp-microvolt = <800000>; | |
771 | }; | |
6a611d14 | 772 | opp-100000000 { |
6b088a62 CC |
773 | opp-hz = /bits/ 64 <100000000>; |
774 | opp-microvolt = <800000>; | |
775 | }; | |
6a611d14 | 776 | opp-134000000 { |
6b088a62 CC |
777 | opp-hz = /bits/ 64 <134000000>; |
778 | opp-microvolt = <800000>; | |
779 | }; | |
6a611d14 | 780 | opp-200000000 { |
6b088a62 CC |
781 | opp-hz = /bits/ 64 <200000000>; |
782 | opp-microvolt = <825000>; | |
783 | }; | |
6a611d14 | 784 | opp-400000000 { |
6b088a62 CC |
785 | opp-hz = /bits/ 64 <400000000>; |
786 | opp-microvolt = <875000>; | |
787 | }; | |
788 | }; | |
304d10ab CC |
789 | |
790 | bus_leftbus: bus_leftbus { | |
791 | compatible = "samsung,exynos-bus"; | |
792 | clocks = <&cmu CLK_DIV_GDL>; | |
793 | clock-names = "bus"; | |
794 | operating-points-v2 = <&bus_leftbus_opp_table>; | |
795 | status = "disabled"; | |
796 | }; | |
797 | ||
798 | bus_rightbus: bus_rightbus { | |
799 | compatible = "samsung,exynos-bus"; | |
800 | clocks = <&cmu CLK_DIV_GDR>; | |
801 | clock-names = "bus"; | |
802 | operating-points-v2 = <&bus_leftbus_opp_table>; | |
803 | status = "disabled"; | |
804 | }; | |
805 | ||
806 | bus_lcd0: bus_lcd0 { | |
807 | compatible = "samsung,exynos-bus"; | |
808 | clocks = <&cmu CLK_DIV_ACLK_160>; | |
809 | clock-names = "bus"; | |
810 | operating-points-v2 = <&bus_leftbus_opp_table>; | |
811 | status = "disabled"; | |
812 | }; | |
813 | ||
814 | bus_fsys: bus_fsys { | |
815 | compatible = "samsung,exynos-bus"; | |
816 | clocks = <&cmu CLK_DIV_ACLK_200>; | |
817 | clock-names = "bus"; | |
818 | operating-points-v2 = <&bus_leftbus_opp_table>; | |
819 | status = "disabled"; | |
820 | }; | |
821 | ||
822 | bus_mcuisp: bus_mcuisp { | |
823 | compatible = "samsung,exynos-bus"; | |
824 | clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; | |
825 | clock-names = "bus"; | |
826 | operating-points-v2 = <&bus_mcuisp_opp_table>; | |
827 | status = "disabled"; | |
828 | }; | |
829 | ||
830 | bus_isp: bus_isp { | |
831 | compatible = "samsung,exynos-bus"; | |
832 | clocks = <&cmu CLK_DIV_ACLK_266>; | |
833 | clock-names = "bus"; | |
834 | operating-points-v2 = <&bus_isp_opp_table>; | |
835 | status = "disabled"; | |
836 | }; | |
837 | ||
838 | bus_peril: bus_peril { | |
839 | compatible = "samsung,exynos-bus"; | |
840 | clocks = <&cmu CLK_DIV_ACLK_100>; | |
841 | clock-names = "bus"; | |
842 | operating-points-v2 = <&bus_peril_opp_table>; | |
843 | status = "disabled"; | |
844 | }; | |
845 | ||
846 | bus_mfc: bus_mfc { | |
847 | compatible = "samsung,exynos-bus"; | |
848 | clocks = <&cmu CLK_SCLK_MFC>; | |
849 | clock-names = "bus"; | |
850 | operating-points-v2 = <&bus_leftbus_opp_table>; | |
851 | status = "disabled"; | |
852 | }; | |
853 | ||
854 | bus_leftbus_opp_table: opp_table2 { | |
855 | compatible = "operating-points-v2"; | |
856 | opp-shared; | |
857 | ||
6a611d14 | 858 | opp-50000000 { |
304d10ab CC |
859 | opp-hz = /bits/ 64 <50000000>; |
860 | opp-microvolt = <900000>; | |
861 | }; | |
6a611d14 | 862 | opp-80000000 { |
304d10ab CC |
863 | opp-hz = /bits/ 64 <80000000>; |
864 | opp-microvolt = <900000>; | |
865 | }; | |
6a611d14 | 866 | opp-100000000 { |
304d10ab CC |
867 | opp-hz = /bits/ 64 <100000000>; |
868 | opp-microvolt = <1000000>; | |
869 | }; | |
6a611d14 | 870 | opp-134000000 { |
304d10ab CC |
871 | opp-hz = /bits/ 64 <134000000>; |
872 | opp-microvolt = <1000000>; | |
873 | }; | |
6a611d14 | 874 | opp-200000000 { |
304d10ab CC |
875 | opp-hz = /bits/ 64 <200000000>; |
876 | opp-microvolt = <1000000>; | |
877 | }; | |
878 | }; | |
879 | ||
880 | bus_mcuisp_opp_table: opp_table3 { | |
881 | compatible = "operating-points-v2"; | |
882 | opp-shared; | |
883 | ||
6a611d14 | 884 | opp-50000000 { |
304d10ab CC |
885 | opp-hz = /bits/ 64 <50000000>; |
886 | }; | |
6a611d14 | 887 | opp-80000000 { |
304d10ab CC |
888 | opp-hz = /bits/ 64 <80000000>; |
889 | }; | |
6a611d14 | 890 | opp-100000000 { |
304d10ab CC |
891 | opp-hz = /bits/ 64 <100000000>; |
892 | }; | |
6a611d14 | 893 | opp-200000000 { |
304d10ab CC |
894 | opp-hz = /bits/ 64 <200000000>; |
895 | }; | |
6a611d14 | 896 | opp-400000000 { |
304d10ab CC |
897 | opp-hz = /bits/ 64 <400000000>; |
898 | }; | |
899 | }; | |
900 | ||
901 | bus_isp_opp_table: opp_table4 { | |
902 | compatible = "operating-points-v2"; | |
903 | opp-shared; | |
904 | ||
6a611d14 | 905 | opp-50000000 { |
304d10ab CC |
906 | opp-hz = /bits/ 64 <50000000>; |
907 | }; | |
6a611d14 | 908 | opp-80000000 { |
304d10ab CC |
909 | opp-hz = /bits/ 64 <80000000>; |
910 | }; | |
6a611d14 | 911 | opp-100000000 { |
304d10ab CC |
912 | opp-hz = /bits/ 64 <100000000>; |
913 | }; | |
6a611d14 | 914 | opp-200000000 { |
304d10ab CC |
915 | opp-hz = /bits/ 64 <200000000>; |
916 | }; | |
6a611d14 | 917 | opp-300000000 { |
304d10ab CC |
918 | opp-hz = /bits/ 64 <300000000>; |
919 | }; | |
920 | }; | |
921 | ||
922 | bus_peril_opp_table: opp_table5 { | |
923 | compatible = "operating-points-v2"; | |
924 | opp-shared; | |
925 | ||
6a611d14 | 926 | opp-50000000 { |
304d10ab CC |
927 | opp-hz = /bits/ 64 <50000000>; |
928 | }; | |
6a611d14 | 929 | opp-80000000 { |
304d10ab CC |
930 | opp-hz = /bits/ 64 <80000000>; |
931 | }; | |
6a611d14 | 932 | opp-100000000 { |
304d10ab CC |
933 | opp-hz = /bits/ 64 <100000000>; |
934 | }; | |
935 | }; | |
5a992a9c TF |
936 | }; |
937 | }; | |
938 | ||
939 | #include "exynos3250-pinctrl.dtsi" | |
a03e9dac | 940 | #include "exynos-syscon-restart.dtsi" |