[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / exynos3250.dtsi

/*
 * Samsung's Exynos3250 SoC device tree source
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "skeleton.dtsi"
#include <dt-bindings/clock/exynos3250.h>

/ {
	compatible = "samsung,exynos3250";
	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		mshc0 = &mshc_0;
		mshc1 = &mshc_1;
		spi0 = &spi_0;
		spi1 = &spi_1;
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &i2c_4;
		i2c5 = &i2c_5;
		i2c6 = &i2c_6;
		i2c7 = &i2c_7;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clock-frequency = <1000000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clock-frequency = <1000000000>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		fixed-rate-clocks {
			#address-cells = <1>;
			#size-cells = <0>;

			xusbxti: clock@0 {
				compatible = "fixed-clock";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xusbxti";
			};

			xxti: clock@1 {
				compatible = "fixed-clock";
				reg = <1>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xxti";
			};

			xtcxo: clock@2 {
				compatible = "fixed-clock";
				reg = <2>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xtcxo";
			};
		};

		sysram@02020000 {
			compatible = "mmio-sram";
			reg = <0x02020000 0x40000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x02020000 0x40000>;

			smp-sysram@0 {
				compatible = "samsung,exynos4210-sysram";
				reg = <0x0 0x1000>;
			};

			smp-sysram@3f000 {
				compatible = "samsung,exynos4210-sysram-ns";
				reg = <0x3f000 0x1000>;
			};
		};

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		sys_reg: syscon@10010000 {
			compatible = "samsung,exynos3-sysreg", "syscon";
			reg = <0x10010000 0x400>;
		};

		pd_cam: cam-power-domain@10023C00 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C00 0x20>;
		};

		pd_mfc: mfc-power-domain@10023C40 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C40 0x20>;
		};

		pd_g3d: g3d-power-domain@10023C60 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C60 0x20>;
		};

		pd_lcd0: lcd0-power-domain@10023C80 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C80 0x20>;
		};

		pd_isp: isp-power-domain@10023CA0 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023CA0 0x20>;
		};

		cmu: clock-controller@10030000 {
			compatible = "samsung,exynos3250-cmu";
			reg = <0x10030000 0x20000>;
			#clock-cells = <1>;
		};

		rtc: rtc@10070000 {
			compatible = "samsung,s3c6410-rtc";
			reg = <0x10070000 0x100>;
			interrupts = <0 73 0>, <0 74 0>;
			status = "disabled";
		};

		gic: interrupt-controller@10481000 {
			compatible = "arm,cortex-a15-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x10481000 0x1000>,
			      <0x10482000 0x1000>,
			      <0x10484000 0x2000>,
			      <0x10486000 0x2000>;
			interrupts = <1 9 0xf04>;
		};

		mct@10050000 {
			compatible = "samsung,exynos4210-mct";
			reg = <0x10050000 0x800>;
			interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
				     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
			clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
			clock-names = "fin_pll", "mct";
		};

		pinctrl_1: pinctrl@11000000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11000000 0x1000>;
			interrupts = <0 225 0>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos4210-wakeup-eint";
				interrupt-parent = <&gic>;
				interrupts = <0 48 0>;
			};
		};

		pinctrl_0: pinctrl@11400000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11400000 0x1000>;
			interrupts = <0 240 0>;
		};

		mshc_0: mshc@12510000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12510000 0x1000>;
			interrupts = <0 142 0>;
			clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mshc_1: mshc@12520000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12520000 0x1000>;
			interrupts = <0 143 0>;
			clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			interrupt-parent = <&gic>;
			ranges;

			pdma0: pdma@12680000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12680000 0x1000>;
				interrupts = <0 138 0>;
				clocks = <&cmu CLK_PDMA0>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};

			pdma1: pdma@12690000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12690000 0x1000>;
				interrupts = <0 139 0>;
				clocks = <&cmu CLK_PDMA1>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};
		};

		adc: adc@126C0000 {
			compatible = "samsung,exynos-adc-v3";
			reg = <0x126C0000 0x100>, <0x10020718 0x4>;
			interrupts = <0 137 0>;
			clock-names = "adc", "sclk_tsadc";
			clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
			#io-channel-cells = <1>;
			io-channel-ranges;
			status = "disabled";
		};

		serial_0: serial@13800000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13800000 0x100>;
			interrupts = <0 109 0>;
			clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_1: serial@13810000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13810000 0x100>;
			interrupts = <0 110 0>;
			clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		i2c_0: i2c@13860000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13860000 0x100>;
			interrupts = <0 113 0>;
			clocks = <&cmu CLK_I2C0>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_bus>;
			status = "disabled";
		};

		i2c_1: i2c@13870000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13870000 0x100>;
			interrupts = <0 114 0>;
			clocks = <&cmu CLK_I2C1>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_bus>;
			status = "disabled";
		};

		i2c_2: i2c@13880000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13880000 0x100>;
			interrupts = <0 115 0>;
			clocks = <&cmu CLK_I2C2>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_bus>;
			status = "disabled";
		};

		i2c_3: i2c@13890000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13890000 0x100>;
			interrupts = <0 116 0>;
			clocks = <&cmu CLK_I2C3>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_bus>;
			status = "disabled";
		};

		i2c_4: i2c@138A0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138A0000 0x100>;
			interrupts = <0 117 0>;
			clocks = <&cmu CLK_I2C4>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_bus>;
			status = "disabled";
		};

		i2c_5: i2c@138B0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138B0000 0x100>;
			interrupts = <0 118 0>;
			clocks = <&cmu CLK_I2C5>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c5_bus>;
			status = "disabled";
		};

		i2c_6: i2c@138C0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138C0000 0x100>;
			interrupts = <0 119 0>;
			clocks = <&cmu CLK_I2C6>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_bus>;
			status = "disabled";
		};

		i2c_7: i2c@138D0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138D0000 0x100>;
			interrupts = <0 120 0>;
			clocks = <&cmu CLK_I2C7>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_bus>;
			status = "disabled";
		};

		spi_0: spi@13920000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13920000 0x100>;
			interrupts = <0 121 0>;
			dmas = <&pdma0 7>, <&pdma0 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi0_bus>;
			status = "disabled";
		};

		spi_1: spi@13930000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13930000 0x100>;
			interrupts = <0 122 0>;
			dmas = <&pdma1 7>, <&pdma1 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi1_bus>;
			status = "disabled";
		};

		pwm: pwm@139D0000 {
			compatible = "samsung,exynos4210-pwm";
			reg = <0x139D0000 0x1000>;
			interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
				     <0 107 0>, <0 108 0>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		pmu {
			compatible = "arm,cortex-a7-pmu";
			interrupts = <0 18 0>, <0 19 0>;
		};
	};
};

#include "exynos3250-pinctrl.dtsi"
Commit	Line	Data
5a992a9c TF	1	/*
	2	* Samsung's Exynos3250 SoC device tree source
	3	*
	4	* Copyright (c) 2014 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
	8	* based board files can include this file and provide values for board specfic
	9	* bindings.
	10	*
	11	* Note: This file does not include device nodes for all the controllers in
	12	* Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
	13	* nodes can be added to this file.
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include "skeleton.dtsi"
	21	#include <dt-bindings/clock/exynos3250.h>
	22
	23	/ {
	24	compatible = "samsung,exynos3250";
	25	interrupt-parent = <&gic>;
	26
	27	aliases {
	28	pinctrl0 = &pinctrl_0;
	29	pinctrl1 = &pinctrl_1;
	30	mshc0 = &mshc_0;
	31	mshc1 = &mshc_1;
	32	spi0 = &spi_0;
	33	spi1 = &spi_1;
	34	i2c0 = &i2c_0;
	35	i2c1 = &i2c_1;
	36	i2c2 = &i2c_2;
	37	i2c3 = &i2c_3;
	38	i2c4 = &i2c_4;
	39	i2c5 = &i2c_5;
	40	i2c6 = &i2c_6;
	41	i2c7 = &i2c_7;
	42	};
	43
	44	cpus {
	45	#address-cells = <1>;
	46	#size-cells = <0>;
	47
	48	cpu0: cpu@0 {
	49	device_type = "cpu";
	50	compatible = "arm,cortex-a7";
	51	reg = <0>;
	52	clock-frequency = <1000000000>;
	53	};
	54
	55	cpu1: cpu@1 {
	56	device_type = "cpu";
	57	compatible = "arm,cortex-a7";
	58	reg = <1>;
	59	clock-frequency = <1000000000>;
	60	};
	61	};
	62
	63	soc: soc {
	64	compatible = "simple-bus";
65	#address-cells = <1>;
66	#size-cells = <1>;
67	ranges;
68
69	fixed-rate-clocks {
70	#address-cells = <1>;
71	#size-cells = <0>;
72
73	xusbxti: clock@0 {
74	compatible = "fixed-clock";
75	#address-cells = <1>;
76	#size-cells = <0>;
77	reg = <0>;
78	clock-frequency = <0>;
79	#clock-cells = <0>;
80	clock-output-names = "xusbxti";
81	};
82
83	xxti: clock@1 {
84	compatible = "fixed-clock";
85	reg = <1>;
86	clock-frequency = <0>;
87	#clock-cells = <0>;
88	clock-output-names = "xxti";
89	};
90
91	xtcxo: clock@2 {
92	compatible = "fixed-clock";
93	reg = <2>;
94	clock-frequency = <0>;
95	#clock-cells = <0>;
96	clock-output-names = "xtcxo";
97	};
98	};
99
100	sysram@02020000 {
101	compatible = "mmio-sram";
102	reg = <0x02020000 0x40000>;
103	#address-cells = <1>;
104	#size-cells = <1>;
105	ranges = <0 0x02020000 0x40000>;
106
107	smp-sysram@0 {
108	compatible = "samsung,exynos4210-sysram";
109	reg = <0x0 0x1000>;
110	};
111
112	smp-sysram@3f000 {
113	compatible = "samsung,exynos4210-sysram-ns";
114	reg = <0x3f000 0x1000>;
115	};
116	};
117
118	chipid@10000000 {
119	compatible = "samsung,exynos4210-chipid";
120	reg = <0x10000000 0x100>;
121	};
122
123	sys_reg: syscon@10010000 {
124	compatible = "samsung,exynos3-sysreg", "syscon";
125	reg = <0x10010000 0x400>;
126	};
127
128	pd_cam: cam-power-domain@10023C00 {
129	compatible = "samsung,exynos4210-pd";
130	reg = <0x10023C00 0x20>;
131	};
132
133	pd_mfc: mfc-power-domain@10023C40 {
134	compatible = "samsung,exynos4210-pd";
135	reg = <0x10023C40 0x20>;
136	};
137
138	pd_g3d: g3d-power-domain@10023C60 {
139	compatible = "samsung,exynos4210-pd";
140	reg = <0x10023C60 0x20>;
141	};
142
143	pd_lcd0: lcd0-power-domain@10023C80 {
144	compatible = "samsung,exynos4210-pd";
145	reg = <0x10023C80 0x20>;
146	};
147
148	pd_isp: isp-power-domain@10023CA0 {
149	compatible = "samsung,exynos4210-pd";
150	reg = <0x10023CA0 0x20>;
151	};
152
153	cmu: clock-controller@10030000 {
154	compatible = "samsung,exynos3250-cmu";
155	reg = <0x10030000 0x20000>;
156	#clock-cells = <1>;
157	};
158
159	rtc: rtc@10070000 {
160	compatible = "samsung,s3c6410-rtc";
161	reg = <0x10070000 0x100>;
162	interrupts = <0 73 0>, <0 74 0>;
163	status = "disabled";
164	};
165
166	gic: interrupt-controller@10481000 {
167	compatible = "arm,cortex-a15-gic";
168	#interrupt-cells = <3>;
169	interrupt-controller;
170	reg = <0x10481000 0x1000>,
171	<0x10482000 0x1000>,
172	<0x10484000 0x2000>,
173	<0x10486000 0x2000>;
174	interrupts = <1 9 0xf04>;
175	};
176
177	mct@10050000 {
178	compatible = "samsung,exynos4210-mct";
179	reg = <0x10050000 0x800>;
180	interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
181	<0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
182	clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
183	clock-names = "fin_pll", "mct";
184	};
185
186	pinctrl_1: pinctrl@11000000 {
187	compatible = "samsung,exynos3250-pinctrl";
188	reg = <0x11000000 0x1000>;
189	interrupts = <0 225 0>;
190
191	wakeup-interrupt-controller {
192	compatible = "samsung,exynos4210-wakeup-eint";
193	interrupt-parent = <&gic>;
194	interrupts = <0 48 0>;
195	};
196	};
197
198	pinctrl_0: pinctrl@11400000 {
199	compatible = "samsung,exynos3250-pinctrl";
200	reg = <0x11400000 0x1000>;
201	interrupts = <0 240 0>;
202	};
203
204	mshc_0: mshc@12510000 {
205	compatible = "samsung,exynos5250-dw-mshc";
206	reg = <0x12510000 0x1000>;
207	interrupts = <0 142 0>;
208	clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
209	clock-names = "biu", "ciu";
210	fifo-depth = <0x80>;
211	#address-cells = <1>;
212	#size-cells = <0>;
213	status = "disabled";
214	};
215
216	mshc_1: mshc@12520000 {
217	compatible = "samsung,exynos5250-dw-mshc";
218	reg = <0x12520000 0x1000>;
219	interrupts = <0 143 0>;
220	clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
221	clock-names = "biu", "ciu";
222	fifo-depth = <0x80>;
223	#address-cells = <1>;
224	#size-cells = <0>;
225	status = "disabled";
226	};
227
228	amba {
229	compatible = "arm,amba-bus";
230	#address-cells = <1>;
231	#size-cells = <1>;
232	interrupt-parent = <&gic>;
233	ranges;
234
235	pdma0: pdma@12680000 {
236	compatible = "arm,pl330", "arm,primecell";
237	reg = <0x12680000 0x1000>;
238	interrupts = <0 138 0>;
239	clocks = <&cmu CLK_PDMA0>;
240	clock-names = "apb_pclk";
241	#dma-cells = <1>;
242	#dma-channels = <8>;
243	#dma-requests = <32>;
244	};
245
246	pdma1: pdma@12690000 {
247	compatible = "arm,pl330", "arm,primecell";
248	reg = <0x12690000 0x1000>;
249	interrupts = <0 139 0>;
250	clocks = <&cmu CLK_PDMA1>;
251	clock-names = "apb_pclk";
252	#dma-cells = <1>;
253	#dma-channels = <8>;
254	#dma-requests = <32>;
255	};
256	};
257
258	adc: adc@126C0000 {
259	compatible = "samsung,exynos-adc-v3";
260	reg = <0x126C0000 0x100>, <0x10020718 0x4>;
261	interrupts = <0 137 0>;
262	clock-names = "adc", "sclk_tsadc";
263	clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
264	#io-channel-cells = <1>;
265	io-channel-ranges;
266	status = "disabled";
267	};
268
269	serial_0: serial@13800000 {
270	compatible = "samsung,exynos4210-uart";
271	reg = <0x13800000 0x100>;
272	interrupts = <0 109 0>;
273	clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
274	clock-names = "uart", "clk_uart_baud0";
275	status = "disabled";
276	};
277
278	serial_1: serial@13810000 {
279	compatible = "samsung,exynos4210-uart";
280	reg = <0x13810000 0x100>;
281	interrupts = <0 110 0>;
282	clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
283	clock-names = "uart", "clk_uart_baud0";
284	status = "disabled";
285	};
286
287	i2c_0: i2c@13860000 {
288	#address-cells = <1>;
289	#size-cells = <0>;
290	compatible = "samsung,s3c2440-i2c";
291	reg = <0x13860000 0x100>;
292	interrupts = <0 113 0>;
293	clocks = <&cmu CLK_I2C0>;
294	clock-names = "i2c";
295	pinctrl-names = "default";
296	pinctrl-0 = <&i2c0_bus>;
297	status = "disabled";
298	};
299
300	i2c_1: i2c@13870000 {
301	#address-cells = <1>;
302	#size-cells = <0>;
303	compatible = "samsung,s3c2440-i2c";
304	reg = <0x13870000 0x100>;
305	interrupts = <0 114 0>;
306	clocks = <&cmu CLK_I2C1>;
307	clock-names = "i2c";
308	pinctrl-names = "default";
309	pinctrl-0 = <&i2c1_bus>;
310	status = "disabled";
311	};
312
313	i2c_2: i2c@13880000 {
314	#address-cells = <1>;
315	#size-cells = <0>;
316	compatible = "samsung,s3c2440-i2c";
317	reg = <0x13880000 0x100>;
318	interrupts = <0 115 0>;
319	clocks = <&cmu CLK_I2C2>;
320	clock-names = "i2c";
321	pinctrl-names = "default";
322	pinctrl-0 = <&i2c2_bus>;
323	status = "disabled";
324	};
325
326	i2c_3: i2c@13890000 {
327	#address-cells = <1>;
328	#size-cells = <0>;
329	compatible = "samsung,s3c2440-i2c";
330	reg = <0x13890000 0x100>;
331	interrupts = <0 116 0>;
332	clocks = <&cmu CLK_I2C3>;
333	clock-names = "i2c";
334	pinctrl-names = "default";
335	pinctrl-0 = <&i2c3_bus>;
336	status = "disabled";
337	};
338
339	i2c_4: i2c@138A0000 {
340	#address-cells = <1>;
341	#size-cells = <0>;
342	compatible = "samsung,s3c2440-i2c";
343	reg = <0x138A0000 0x100>;
344	interrupts = <0 117 0>;
345	clocks = <&cmu CLK_I2C4>;
346	clock-names = "i2c";
347	pinctrl-names = "default";
348	pinctrl-0 = <&i2c4_bus>;
349	status = "disabled";
350	};
351
352	i2c_5: i2c@138B0000 {
353	#address-cells = <1>;
354	#size-cells = <0>;
355	compatible = "samsung,s3c2440-i2c";
356	reg = <0x138B0000 0x100>;
357	interrupts = <0 118 0>;
358	clocks = <&cmu CLK_I2C5>;
359	clock-names = "i2c";
360	pinctrl-names = "default";
361	pinctrl-0 = <&i2c5_bus>;
362	status = "disabled";
363	};
364
365	i2c_6: i2c@138C0000 {
366	#address-cells = <1>;
367	#size-cells = <0>;
368	compatible = "samsung,s3c2440-i2c";
369	reg = <0x138C0000 0x100>;
370	interrupts = <0 119 0>;
371	clocks = <&cmu CLK_I2C6>;
372	clock-names = "i2c";
373	pinctrl-names = "default";
374	pinctrl-0 = <&i2c6_bus>;
375	status = "disabled";
376	};
377
378	i2c_7: i2c@138D0000 {
379	#address-cells = <1>;
380	#size-cells = <0>;
381	compatible = "samsung,s3c2440-i2c";
382	reg = <0x138D0000 0x100>;
383	interrupts = <0 120 0>;
384	clocks = <&cmu CLK_I2C7>;
385	clock-names = "i2c";
386	pinctrl-names = "default";
387	pinctrl-0 = <&i2c7_bus>;
388	status = "disabled";
389	};
390
391	spi_0: spi@13920000 {
392	compatible = "samsung,exynos4210-spi";
393	reg = <0x13920000 0x100>;
394	interrupts = <0 121 0>;
395	dmas = <&pdma0 7>, <&pdma0 6>;
396	dma-names = "tx", "rx";
397	#address-cells = <1>;
398	#size-cells = <0>;
399	clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
400	clock-names = "spi", "spi_busclk0";
401	samsung,spi-src-clk = <0>;
402	pinctrl-names = "default";
403	pinctrl-0 = <&spi0_bus>;
404	status = "disabled";
405	};
406
407	spi_1: spi@13930000 {
408	compatible = "samsung,exynos4210-spi";
409	reg = <0x13930000 0x100>;
410	interrupts = <0 122 0>;
411	dmas = <&pdma1 7>, <&pdma1 6>;
412	dma-names = "tx", "rx";
413	#address-cells = <1>;
414	#size-cells = <0>;
415	clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
416	clock-names = "spi", "spi_busclk0";
417	samsung,spi-src-clk = <0>;
418	pinctrl-names = "default";
419	pinctrl-0 = <&spi1_bus>;
420	status = "disabled";
421	};
422
423	pwm: pwm@139D0000 {
424	compatible = "samsung,exynos4210-pwm";
425	reg = <0x139D0000 0x1000>;
426	interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
427	<0 107 0>, <0 108 0>;
428	#pwm-cells = <3>;
429	status = "disabled";
430	};
431
432	pmu {
433	compatible = "arm,cortex-a7-pmu";
434	interrupts = <0 18 0>, <0 19 0>;
435	};
436	};
437	};
438
439	#include "exynos3250-pinctrl.dtsi"