[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / exynos4210.dtsi

/*
 * Samsung's Exynos4210 SoC device tree source
 *
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 * Copyright (c) 2010-2011 Linaro Ltd.
 *		www.linaro.org
 *
 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include "exynos4.dtsi"
#include "exynos4210-pinctrl.dtsi"
#include "exynos4-cpu-thermal.dtsi"

/ {
	compatible = "samsung,exynos4210", "samsung,exynos4";

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@900 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x900>;
			cooling-min-level = <4>;
			cooling-max-level = <2>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu@901 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x901>;
		};
	};

	pmu_system_controller: system-controller@10020000 {
		clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
				"clkout4", "clkout8", "clkout9";
		clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
			<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
			<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
			<&clock CLK_XUSBXTI>;
		#clock-cells = <1>;
	};

	sysram@02020000 {
		compatible = "mmio-sram";
		reg = <0x02020000 0x20000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x02020000 0x20000>;

		smp-sysram@0 {
			compatible = "samsung,exynos4210-sysram";
			reg = <0x0 0x1000>;
		};

		smp-sysram@1f000 {
			compatible = "samsung,exynos4210-sysram-ns";
			reg = <0x1f000 0x1000>;
		};
	};

	pd_lcd1: lcd1-power-domain@10023CA0 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10023CA0 0x20>;
		#power-domain-cells = <0>;
	};

	l2c: l2-cache-controller@10502000 {
		compatible = "arm,pl310-cache";
		reg = <0x10502000 0x1000>;
		cache-unified;
		cache-level = <2>;
		arm,tag-latency = <2 2 1>;
		arm,data-latency = <2 2 1>;
	};

	gic: interrupt-controller@10490000 {
		cpu-offset = <0x8000>;
	};

	combiner: interrupt-controller@10440000 {
		samsung,combiner-nr = <16>;
		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
	};

	mct@10050000 {
		compatible = "samsung,exynos4210-mct";
		reg = <0x10050000 0x800>;
		interrupt-parent = <&mct_map>;
		interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
		clock-names = "fin_pll", "mct";

		mct_map: mct-map {
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <0 &gic 0 57 0>,
					<1 &gic 0 69 0>,
					<2 &combiner 12 6>,
					<3 &combiner 12 7>,
					<4 &gic 0 42 0>,
					<5 &gic 0 48 0>;
		};
	};

	clock: clock-controller@10030000 {
		compatible = "samsung,exynos4210-clock";
		reg = <0x10030000 0x20000>;
		#clock-cells = <1>;
	};

	pinctrl_0: pinctrl@11400000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x11400000 0x1000>;
		interrupts = <0 47 0>;
	};

	pinctrl_1: pinctrl@11000000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x11000000 0x1000>;
		interrupts = <0 46 0>;

		wakup_eint: wakeup-interrupt-controller {
			compatible = "samsung,exynos4210-wakeup-eint";
			interrupt-parent = <&gic>;
			interrupts = <0 32 0>;
		};
	};

	pinctrl_2: pinctrl@03860000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x03860000 0x1000>;
	};

	tmu: tmu@100C0000 {
		compatible = "samsung,exynos4210-tmu";
		interrupt-parent = <&combiner>;
		reg = <0x100C0000 0x100>;
		interrupts = <2 4>;
		clocks = <&clock CLK_TMU_APBIF>;
		clock-names = "tmu_apbif";
		samsung,tmu_gain = <15>;
		samsung,tmu_reference_voltage = <7>;
		status = "disabled";
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tmu 0>;

			trips {
			      cpu_alert0: cpu-alert-0 {
				      temperature = <85000>; /* millicelsius */
			      };
			      cpu_alert1: cpu-alert-1 {
				      temperature = <100000>; /* millicelsius */
			      };
			      cpu_alert2: cpu-alert-2 {
				      temperature = <110000>; /* millicelsius */
			      };
			};
		};
	};

	g2d@12800000 {
		compatible = "samsung,s5pv210-g2d";
		reg = <0x12800000 0x1000>;
		interrupts = <0 89 0>;
		clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
		clock-names = "sclk_fimg2d", "fimg2d";
		status = "disabled";
	};

	camera {
		clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
			 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
		clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";

		fimc_0: fimc@11800000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,cam-if;
		};

		fimc_1: fimc@11810000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,cam-if;
		};

		fimc_2: fimc@11820000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,lcd-wb;
		};

		fimc_3: fimc@11830000 {
			samsung,pix-limits = <1920 8192 1366 1920>;
			samsung,rotators = <0>;
			samsung,mainscaler-ext;
			samsung,lcd-wb;
		};
	};

	mixer: mixer@12C10000 {
		clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
			"sclk_mixer";
		clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
			<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
			<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
	};

	ppmu_lcd1: ppmu_lcd1@12240000 {
		compatible = "samsung,exynos-ppmu";
		reg = <0x12240000 0x2000>;
		clocks = <&clock CLK_PPMULCD1>;
		clock-names = "ppmu";
		status = "disabled";
	};
};
Commit	Line	Data
0561ceab TA	1	/*
	2	* Samsung's Exynos4210 SoC device tree source
	3	*
	4	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	* Copyright (c) 2010-2011 Linaro Ltd.
	7	* www.linaro.org
	8	*
	9	* Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
	10	* based board files can include this file and provide values for board specfic
	11	* bindings.
	12	*
	13	* Note: This file does not include device nodes for all the controllers in
	14	* Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
	15	* nodes can be added to this file.
	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License version 2 as
	19	* published by the Free Software Foundation.
	20	*/
	21
3799279f PV	22	#include "exynos4.dtsi"
3799279f PV	23	#include "exynos4210-pinctrl.dtsi"
9843a223	24	#include "exynos4-cpu-thermal.dtsi"
0561ceab TA	25
0561ceab TA	26	/ {
8bdb31b4	27	compatible = "samsung,exynos4210", "samsung,exynos4";
0561ceab	28
4980c39b	29	aliases {
87711d8c TA	30	pinctrl0 = &pinctrl_0;
	31	pinctrl1 = &pinctrl_1;
	32	pinctrl2 = &pinctrl_2;
4980c39b TA	33	};
4980c39b TA	34
e540920c BZ	35	cpus {
	36	#address-cells = <1>;
	37	#size-cells = <0>;
	38
bf4a0bed	39	cpu0: cpu@900 {
e540920c BZ	40	device_type = "cpu";
	41	compatible = "arm,cortex-a9";
	42	reg = <0x900>;
bf4a0bed LM	43	cooling-min-level = <4>;
	44	cooling-max-level = <2>;
	45	#cooling-cells = <2>; /* min followed by max */
e540920c BZ	46	};
	47
	48	cpu@901 {
	49	device_type = "cpu";
	50	compatible = "arm,cortex-a9";
	51	reg = <0x901>;
	52	};
	53	};
	54
d19bb397 TF	55	pmu_system_controller: system-controller@10020000 {
	56	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
	57	"clkout4", "clkout8", "clkout9";
	58	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
	59	<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
	60	<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
	61	<&clock CLK_XUSBXTI>;
	62	#clock-cells = <1>;
	63	};
	64
b3205dea SK	65	sysram@02020000 {
	66	compatible = "mmio-sram";
	67	reg = <0x02020000 0x20000>;
	68	#address-cells = <1>;
	69	#size-cells = <1>;
	70	ranges = <0 0x02020000 0x20000>;
	71
	72	smp-sysram@0 {
	73	compatible = "samsung,exynos4210-sysram";
	74	reg = <0x0 0x1000>;
	75	};
	76
	77	smp-sysram@1f000 {
	78	compatible = "samsung,exynos4210-sysram-ns";
	79	reg = <0x1f000 0x1000>;
	80	};
	81	};
	82
91d88f03 TF	83	pd_lcd1: lcd1-power-domain@10023CA0 {
	84	compatible = "samsung,exynos4210-pd";
	85	reg = <0x10023CA0 0x20>;
0da65870	86	#power-domain-cells = <0>;
91d88f03 TF	87	};
91d88f03 TF	88
56b60b8b TF	89	l2c: l2-cache-controller@10502000 {
	90	compatible = "arm,pl310-cache";
	91	reg = <0x10502000 0x1000>;
	92	cache-unified;
	93	cache-level = <2>;
	94	arm,tag-latency = <2 2 1>;
	95	arm,data-latency = <2 2 1>;
	96	};
	97
0572b725	98	gic: interrupt-controller@10490000 {
da911782	99	cpu-offset = <0x8000>;
0561ceab TA	100	};
0561ceab TA	101
0572b725	102	combiner: interrupt-controller@10440000 {
30269ddf	103	samsung,combiner-nr = <16>;
4922972e TA	104	interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
	105	<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
	106	<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
	107	<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
	108	};
	109
bbd9700a TA	110	mct@10050000 {
	111	compatible = "samsung,exynos4210-mct";
	112	reg = <0x10050000 0x800>;
bbd9700a	113	interrupt-parent = <&mct_map>;
84ee1c15	114	interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
1c75a78a	115	clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
7ad34337	116	clock-names = "fin_pll", "mct";
bbd9700a TA	117
bbd9700a TA	118	mct_map: mct-map {
84ee1c15	119	#interrupt-cells = <1>;
bbd9700a TA	120	#address-cells = <0>;
bbd9700a TA	121	#size-cells = <0>;
84ee1c15 TF	122	interrupt-map = <0 &gic 0 57 0>,
	123	<1 &gic 0 69 0>,
	124	<2 &combiner 12 6>,
	125	<3 &combiner 12 7>,
	126	<4 &gic 0 42 0>,
	127	<5 &gic 0 48 0>;
bbd9700a TA	128	};
	129	};
	130
e7787aed	131	clock: clock-controller@10030000 {
d8bafc87 TA	132	compatible = "samsung,exynos4210-clock";
	133	reg = <0x10030000 0x20000>;
	134	#clock-cells = <1>;
	135	};
	136
87711d8c	137	pinctrl_0: pinctrl@11400000 {
b533c868	138	compatible = "samsung,exynos4210-pinctrl";
87711d8c TA	139	reg = <0x11400000 0x1000>;
87711d8c TA	140	interrupts = <0 47 0>;
87711d8c TA	141	};
	142
	143	pinctrl_1: pinctrl@11000000 {
b533c868	144	compatible = "samsung,exynos4210-pinctrl";
87711d8c TA	145	reg = <0x11000000 0x1000>;
87711d8c TA	146	interrupts = <0 46 0>;
87711d8c TA	147
	148	wakup_eint: wakeup-interrupt-controller {
	149	compatible = "samsung,exynos4210-wakeup-eint";
	150	interrupt-parent = <&gic>;
a04b07c0	151	interrupts = <0 32 0>;
87711d8c TA	152	};
	153	};
	154
	155	pinctrl_2: pinctrl@03860000 {
b533c868	156	compatible = "samsung,exynos4210-pinctrl";
87711d8c TA	157	reg = <0x03860000 0x1000>;
	158	};
	159
9843a223	160	tmu: tmu@100C0000 {
8d4155db ADK	161	compatible = "samsung,exynos4210-tmu";
	162	interrupt-parent = <&combiner>;
	163	reg = <0x100C0000 0x100>;
	164	interrupts = <2 4>;
1c75a78a	165	clocks = <&clock CLK_TMU_APBIF>;
e6199af6	166	clock-names = "tmu_apbif";
9843a223 LM	167	samsung,tmu_gain = <15>;
9843a223 LM	168	samsung,tmu_reference_voltage = <7>;
e6199af6	169	status = "disabled";
8d4155db	170	};
66d302ac	171
9843a223 LM	172	thermal-zones {
	173	cpu_thermal: cpu-thermal {
	174	polling-delay-passive = <0>;
	175	polling-delay = <0>;
	176	thermal-sensors = <&tmu 0>;
	177
	178	trips {
	179	cpu_alert0: cpu-alert-0 {
	180	temperature = <85000>; /* millicelsius */
	181	};
	182	cpu_alert1: cpu-alert-1 {
	183	temperature = <100000>; /* millicelsius */
	184	};
	185	cpu_alert2: cpu-alert-2 {
	186	temperature = <110000>; /* millicelsius */
	187	};
	188	};
	189	};
	190	};
	191
66d302ac SK	192	g2d@12800000 {
	193	compatible = "samsung,s5pv210-g2d";
	194	reg = <0x12800000 0x1000>;
	195	interrupts = <0 89 0>;
1c75a78a	196	clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
37bf5796	197	clock-names = "sclk_fimg2d", "fimg2d";
66d302ac SK	198	status = "disabled";
66d302ac SK	199	};
54a8896a SN	200
54a8896a SN	201	camera {
1c75a78a AH	202	clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
1c75a78a AH	203	<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
54a8896a SN	204	clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
	205
	206	fimc_0: fimc@11800000 {
	207	samsung,pix-limits = <4224 8192 1920 4224>;
	208	samsung,mainscaler-ext;
	209	samsung,cam-if;
	210	};
	211
	212	fimc_1: fimc@11810000 {
	213	samsung,pix-limits = <4224 8192 1920 4224>;
	214	samsung,mainscaler-ext;
	215	samsung,cam-if;
	216	};
	217
	218	fimc_2: fimc@11820000 {
	219	samsung,pix-limits = <4224 8192 1920 4224>;
	220	samsung,mainscaler-ext;
	221	samsung,lcd-wb;
	222	};
	223
	224	fimc_3: fimc@11830000 {
	225	samsung,pix-limits = <1920 8192 1366 1920>;
	226	samsung,rotators = <0>;
	227	samsung,mainscaler-ext;
	228	samsung,lcd-wb;
	229	};
	230	};
30e0e476	231
ed80d4ca MS	232	mixer: mixer@12C10000 {
	233	clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
	234	"sclk_mixer";
	235	clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
	236	<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
	237	<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
	238	};
	239
30e0e476 CC	240	ppmu_lcd1: ppmu_lcd1@12240000 {
	241	compatible = "samsung,exynos-ppmu";
	242	reg = <0x12240000 0x2000>;
	243	clocks = <&clock CLK_PPMULCD1>;
	244	clock-names = "ppmu";
	245	status = "disabled";
	246	};
0561ceab	247	};