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ARM: EXYNOS: Cleanup common.h file
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1/*
2 * Samsung's Exynos4210 SoC device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
11 * bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20*/
21
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22#include "exynos4.dtsi"
23#include "exynos4210-pinctrl.dtsi"
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24
25/ {
26 compatible = "samsung,exynos4210";
0561ceab 27
4980c39b 28 aliases {
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29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
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32 };
33
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34 pd_lcd1: lcd1-power-domain@10023CA0 {
35 compatible = "samsung,exynos4210-pd";
36 reg = <0x10023CA0 0x20>;
37 };
38
0561ceab 39 gic:interrupt-controller@10490000 {
da911782 40 cpu-offset = <0x8000>;
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41 };
42
4922972e 43 combiner:interrupt-controller@10440000 {
30269ddf 44 samsung,combiner-nr = <16>;
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45 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
46 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
47 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
48 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
49 };
50
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51 mct@10050000 {
52 compatible = "samsung,exynos4210-mct";
53 reg = <0x10050000 0x800>;
54 interrupt-controller;
55 #interrups-cells = <2>;
56 interrupt-parent = <&mct_map>;
57 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
58 <4 0>, <5 0>;
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59 clocks = <&clock 3>, <&clock 344>;
60 clock-names = "fin_pll", "mct";
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61
62 mct_map: mct-map {
63 #interrupt-cells = <2>;
64 #address-cells = <0>;
65 #size-cells = <0>;
66 interrupt-map = <0x0 0 &gic 0 57 0>,
67 <0x1 0 &gic 0 69 0>,
68 <0x2 0 &combiner 12 6>,
69 <0x3 0 &combiner 12 7>,
70 <0x4 0 &gic 0 42 0>,
71 <0x5 0 &gic 0 48 0>;
72 };
73 };
74
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75 clock: clock-controller@0x10030000 {
76 compatible = "samsung,exynos4210-clock";
77 reg = <0x10030000 0x20000>;
78 #clock-cells = <1>;
79 };
80
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81 pmu {
82 compatible = "arm,cortex-a9-pmu";
83 interrupt-parent = <&combiner>;
84 interrupts = <2 2>, <3 2>;
85 };
86
87711d8c 87 pinctrl_0: pinctrl@11400000 {
b533c868 88 compatible = "samsung,exynos4210-pinctrl";
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89 reg = <0x11400000 0x1000>;
90 interrupts = <0 47 0>;
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91 };
92
93 pinctrl_1: pinctrl@11000000 {
b533c868 94 compatible = "samsung,exynos4210-pinctrl";
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95 reg = <0x11000000 0x1000>;
96 interrupts = <0 46 0>;
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97
98 wakup_eint: wakeup-interrupt-controller {
99 compatible = "samsung,exynos4210-wakeup-eint";
100 interrupt-parent = <&gic>;
a04b07c0 101 interrupts = <0 32 0>;
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102 };
103 };
104
105 pinctrl_2: pinctrl@03860000 {
b533c868 106 compatible = "samsung,exynos4210-pinctrl";
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107 reg = <0x03860000 0x1000>;
108 };
109
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110 tmu@100C0000 {
111 compatible = "samsung,exynos4210-tmu";
112 interrupt-parent = <&combiner>;
113 reg = <0x100C0000 0x100>;
114 interrupts = <2 4>;
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115 clocks = <&clock 383>;
116 clock-names = "tmu_apbif";
117 status = "disabled";
8d4155db 118 };
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119
120 g2d@12800000 {
121 compatible = "samsung,s5pv210-g2d";
122 reg = <0x12800000 0x1000>;
123 interrupts = <0 89 0>;
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124 clocks = <&clock 177>, <&clock 277>;
125 clock-names = "sclk_fimg2d", "fimg2d";
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126 status = "disabled";
127 };
0561ceab 128};