]>
Commit | Line | Data |
---|---|---|
0561ceab TA |
1 | /* |
2 | * Samsung's Exynos4210 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * Copyright (c) 2010-2011 Linaro Ltd. | |
7 | * www.linaro.org | |
8 | * | |
9 | * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 | |
10 | * based board files can include this file and provide values for board specfic | |
11 | * bindings. | |
12 | * | |
13 | * Note: This file does not include device nodes for all the controllers in | |
14 | * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional | |
15 | * nodes can be added to this file. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
20 | */ | |
21 | ||
b571abb3 | 22 | /include/ "exynos4.dtsi" |
87711d8c | 23 | /include/ "exynos4210-pinctrl.dtsi" |
0561ceab TA |
24 | |
25 | / { | |
26 | compatible = "samsung,exynos4210"; | |
0561ceab | 27 | |
4980c39b | 28 | aliases { |
87711d8c TA |
29 | pinctrl0 = &pinctrl_0; |
30 | pinctrl1 = &pinctrl_1; | |
31 | pinctrl2 = &pinctrl_2; | |
4980c39b TA |
32 | }; |
33 | ||
91d88f03 TF |
34 | pd_lcd1: lcd1-power-domain@10023CA0 { |
35 | compatible = "samsung,exynos4210-pd"; | |
36 | reg = <0x10023CA0 0x20>; | |
37 | }; | |
38 | ||
0561ceab | 39 | gic:interrupt-controller@10490000 { |
da911782 | 40 | cpu-offset = <0x8000>; |
0561ceab TA |
41 | }; |
42 | ||
4922972e | 43 | combiner:interrupt-controller@10440000 { |
4922972e TA |
44 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, |
45 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | |
46 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | |
47 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; | |
48 | }; | |
49 | ||
bbd9700a TA |
50 | mct@10050000 { |
51 | compatible = "samsung,exynos4210-mct"; | |
52 | reg = <0x10050000 0x800>; | |
53 | interrupt-controller; | |
54 | #interrups-cells = <2>; | |
55 | interrupt-parent = <&mct_map>; | |
56 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | |
57 | <4 0>, <5 0>; | |
58 | ||
59 | mct_map: mct-map { | |
60 | #interrupt-cells = <2>; | |
61 | #address-cells = <0>; | |
62 | #size-cells = <0>; | |
63 | interrupt-map = <0x0 0 &gic 0 57 0>, | |
64 | <0x1 0 &gic 0 69 0>, | |
65 | <0x2 0 &combiner 12 6>, | |
66 | <0x3 0 &combiner 12 7>, | |
67 | <0x4 0 &gic 0 42 0>, | |
68 | <0x5 0 &gic 0 48 0>; | |
69 | }; | |
70 | }; | |
71 | ||
d8bafc87 TA |
72 | clock: clock-controller@0x10030000 { |
73 | compatible = "samsung,exynos4210-clock"; | |
74 | reg = <0x10030000 0x20000>; | |
75 | #clock-cells = <1>; | |
76 | }; | |
77 | ||
87711d8c | 78 | pinctrl_0: pinctrl@11400000 { |
b533c868 | 79 | compatible = "samsung,exynos4210-pinctrl"; |
87711d8c TA |
80 | reg = <0x11400000 0x1000>; |
81 | interrupts = <0 47 0>; | |
87711d8c TA |
82 | }; |
83 | ||
84 | pinctrl_1: pinctrl@11000000 { | |
b533c868 | 85 | compatible = "samsung,exynos4210-pinctrl"; |
87711d8c TA |
86 | reg = <0x11000000 0x1000>; |
87 | interrupts = <0 46 0>; | |
87711d8c TA |
88 | |
89 | wakup_eint: wakeup-interrupt-controller { | |
90 | compatible = "samsung,exynos4210-wakeup-eint"; | |
91 | interrupt-parent = <&gic>; | |
a04b07c0 | 92 | interrupts = <0 32 0>; |
87711d8c TA |
93 | }; |
94 | }; | |
95 | ||
96 | pinctrl_2: pinctrl@03860000 { | |
b533c868 | 97 | compatible = "samsung,exynos4210-pinctrl"; |
87711d8c TA |
98 | reg = <0x03860000 0x1000>; |
99 | }; | |
100 | ||
8d4155db ADK |
101 | tmu@100C0000 { |
102 | compatible = "samsung,exynos4210-tmu"; | |
103 | interrupt-parent = <&combiner>; | |
104 | reg = <0x100C0000 0x100>; | |
105 | interrupts = <2 4>; | |
106 | }; | |
0561ceab | 107 | }; |