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0f7238a1 TF |
1 | /* |
2 | * Samsung's Exynos4412 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 | |
8 | * based board files can include this file and provide values for board specfic | |
9 | * bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional | |
13 | * nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
3799279f | 20 | #include "exynos4x12.dtsi" |
0f7238a1 TF |
21 | |
22 | / { | |
8bdb31b4 | 23 | compatible = "samsung,exynos4412", "samsung,exynos4"; |
0f7238a1 | 24 | |
e540920c BZ |
25 | cpus { |
26 | #address-cells = <1>; | |
27 | #size-cells = <0>; | |
28 | ||
bf4a0bed | 29 | cpu0: cpu@A00 { |
e540920c BZ |
30 | device_type = "cpu"; |
31 | compatible = "arm,cortex-a9"; | |
32 | reg = <0xA00>; | |
f4499741 BZ |
33 | clocks = <&clock CLK_ARM_CLK>; |
34 | clock-names = "cpu"; | |
35 | operating-points-v2 = <&cpu0_opp_table>; | |
bf4a0bed LM |
36 | cooling-min-level = <13>; |
37 | cooling-max-level = <7>; | |
38 | #cooling-cells = <2>; /* min followed by max */ | |
e540920c BZ |
39 | }; |
40 | ||
41 | cpu@A01 { | |
42 | device_type = "cpu"; | |
43 | compatible = "arm,cortex-a9"; | |
44 | reg = <0xA01>; | |
f4499741 | 45 | operating-points-v2 = <&cpu0_opp_table>; |
e540920c BZ |
46 | }; |
47 | ||
48 | cpu@A02 { | |
49 | device_type = "cpu"; | |
50 | compatible = "arm,cortex-a9"; | |
51 | reg = <0xA02>; | |
f4499741 | 52 | operating-points-v2 = <&cpu0_opp_table>; |
e540920c BZ |
53 | }; |
54 | ||
55 | cpu@A03 { | |
56 | device_type = "cpu"; | |
57 | compatible = "arm,cortex-a9"; | |
58 | reg = <0xA03>; | |
f4499741 BZ |
59 | operating-points-v2 = <&cpu0_opp_table>; |
60 | }; | |
61 | }; | |
62 | ||
63 | cpu0_opp_table: opp_table0 { | |
64 | compatible = "operating-points-v2"; | |
65 | opp-shared; | |
66 | ||
2aae9915 | 67 | opp@200000000 { |
f4499741 BZ |
68 | opp-hz = /bits/ 64 <200000000>; |
69 | opp-microvolt = <900000>; | |
70 | clock-latency-ns = <200000>; | |
71 | }; | |
2aae9915 | 72 | opp@300000000 { |
f4499741 BZ |
73 | opp-hz = /bits/ 64 <300000000>; |
74 | opp-microvolt = <900000>; | |
75 | clock-latency-ns = <200000>; | |
76 | }; | |
2aae9915 | 77 | opp@400000000 { |
f4499741 BZ |
78 | opp-hz = /bits/ 64 <400000000>; |
79 | opp-microvolt = <925000>; | |
80 | clock-latency-ns = <200000>; | |
81 | }; | |
2aae9915 | 82 | opp@500000000 { |
f4499741 BZ |
83 | opp-hz = /bits/ 64 <500000000>; |
84 | opp-microvolt = <950000>; | |
85 | clock-latency-ns = <200000>; | |
86 | }; | |
2aae9915 | 87 | opp@600000000 { |
f4499741 BZ |
88 | opp-hz = /bits/ 64 <600000000>; |
89 | opp-microvolt = <975000>; | |
90 | clock-latency-ns = <200000>; | |
91 | }; | |
2aae9915 | 92 | opp@700000000 { |
f4499741 BZ |
93 | opp-hz = /bits/ 64 <700000000>; |
94 | opp-microvolt = <987500>; | |
95 | clock-latency-ns = <200000>; | |
96 | }; | |
2aae9915 | 97 | opp@800000000 { |
f4499741 BZ |
98 | opp-hz = /bits/ 64 <800000000>; |
99 | opp-microvolt = <1000000>; | |
100 | clock-latency-ns = <200000>; | |
1605b60a | 101 | opp-suspend; |
f4499741 | 102 | }; |
2aae9915 | 103 | opp@900000000 { |
f4499741 BZ |
104 | opp-hz = /bits/ 64 <900000000>; |
105 | opp-microvolt = <1037500>; | |
106 | clock-latency-ns = <200000>; | |
107 | }; | |
2aae9915 | 108 | opp@1000000000 { |
f4499741 BZ |
109 | opp-hz = /bits/ 64 <1000000000>; |
110 | opp-microvolt = <1087500>; | |
111 | clock-latency-ns = <200000>; | |
112 | }; | |
2aae9915 | 113 | opp@1100000000 { |
f4499741 BZ |
114 | opp-hz = /bits/ 64 <1100000000>; |
115 | opp-microvolt = <1137500>; | |
116 | clock-latency-ns = <200000>; | |
117 | }; | |
2aae9915 | 118 | opp@1200000000 { |
f4499741 BZ |
119 | opp-hz = /bits/ 64 <1200000000>; |
120 | opp-microvolt = <1187500>; | |
121 | clock-latency-ns = <200000>; | |
122 | }; | |
2aae9915 | 123 | opp@1300000000 { |
f4499741 BZ |
124 | opp-hz = /bits/ 64 <1300000000>; |
125 | opp-microvolt = <1250000>; | |
126 | clock-latency-ns = <200000>; | |
127 | }; | |
2aae9915 | 128 | opp@1400000000 { |
f4499741 BZ |
129 | opp-hz = /bits/ 64 <1400000000>; |
130 | opp-microvolt = <1287500>; | |
131 | clock-latency-ns = <200000>; | |
132 | }; | |
2aae9915 | 133 | opp@1500000000 { |
f4499741 BZ |
134 | opp-hz = /bits/ 64 <1500000000>; |
135 | opp-microvolt = <1350000>; | |
136 | clock-latency-ns = <200000>; | |
137 | turbo-mode; | |
e540920c BZ |
138 | }; |
139 | }; | |
140 | ||
6f4b82a3 CP |
141 | pmu { |
142 | interrupts = <2 2>, <3 2>, <18 2>, <19 2>; | |
143 | }; | |
08c4b441 | 144 | }; |
6f4b82a3 | 145 | |
08c4b441 KK |
146 | &pmu_system_controller { |
147 | compatible = "samsung,exynos4412-pmu", "syscon"; | |
148 | }; | |
7b9613ac | 149 | |
08c4b441 KK |
150 | &combiner { |
151 | samsung,combiner-nr = <20>; | |
152 | }; | |
153 | ||
154 | &gic { | |
155 | cpu-offset = <0x4000>; | |
0f7238a1 | 156 | }; |