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Commit | Line | Data |
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0f7238a1 TF |
1 | /* |
2 | * Samsung's Exynos4x12 SoCs device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 | |
8 | * based board files can include this file and provide values for board specfic | |
9 | * bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional | |
13 | * nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
3799279f PV |
20 | #include "exynos4.dtsi" |
21 | #include "exynos4x12-pinctrl.dtsi" | |
0f7238a1 TF |
22 | |
23 | / { | |
64a57434 TF |
24 | aliases { |
25 | pinctrl0 = &pinctrl_0; | |
26 | pinctrl1 = &pinctrl_1; | |
27 | pinctrl2 = &pinctrl_2; | |
28 | pinctrl3 = &pinctrl_3; | |
582435b3 SN |
29 | fimc-lite0 = &fimc_lite_0; |
30 | fimc-lite1 = &fimc_lite_1; | |
56d52bfb | 31 | mshc0 = &mshc_0; |
64a57434 TF |
32 | }; |
33 | ||
be929999 CC |
34 | pmu { |
35 | compatible = "arm,cortex-a9-pmu"; | |
36 | interrupt-parent = <&combiner>; | |
37 | interrupts = <2 2>, <3 2>, <18 2>, <19 2>; | |
38 | }; | |
39 | ||
b3205dea SK |
40 | sysram@02020000 { |
41 | compatible = "mmio-sram"; | |
42 | reg = <0x02020000 0x40000>; | |
43 | #address-cells = <1>; | |
44 | #size-cells = <1>; | |
45 | ranges = <0 0x02020000 0x40000>; | |
46 | ||
47 | smp-sysram@0 { | |
48 | compatible = "samsung,exynos4210-sysram"; | |
49 | reg = <0x0 0x1000>; | |
50 | }; | |
51 | ||
52 | smp-sysram@2f000 { | |
53 | compatible = "samsung,exynos4210-sysram-ns"; | |
54 | reg = <0x2f000 0x1000>; | |
55 | }; | |
56 | }; | |
57 | ||
2ab9f3c0 SN |
58 | pd_isp: isp-power-domain@10023CA0 { |
59 | compatible = "samsung,exynos4210-pd"; | |
60 | reg = <0x10023CA0 0x20>; | |
64a57434 TF |
61 | }; |
62 | ||
1fd9a015 | 63 | clock: clock-controller@10030000 { |
d8bafc87 TA |
64 | compatible = "samsung,exynos4412-clock"; |
65 | reg = <0x10030000 0x20000>; | |
66 | #clock-cells = <1>; | |
67 | }; | |
68 | ||
39e596f0 TF |
69 | mct@10050000 { |
70 | compatible = "samsung,exynos4412-mct"; | |
71 | reg = <0x10050000 0x800>; | |
72 | interrupt-parent = <&mct_map>; | |
84ee1c15 | 73 | interrupts = <0>, <1>, <2>, <3>, <4>; |
1c75a78a | 74 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
39e596f0 TF |
75 | clock-names = "fin_pll", "mct"; |
76 | ||
77 | mct_map: mct-map { | |
84ee1c15 | 78 | #interrupt-cells = <1>; |
39e596f0 TF |
79 | #address-cells = <0>; |
80 | #size-cells = <0>; | |
84ee1c15 TF |
81 | interrupt-map = <0 &gic 0 57 0>, |
82 | <1 &combiner 12 5>, | |
83 | <2 &combiner 12 6>, | |
84 | <3 &combiner 12 7>, | |
85 | <4 &gic 1 12 0>; | |
39e596f0 TF |
86 | }; |
87 | }; | |
88 | ||
8bdfa203 CC |
89 | combiner: interrupt-controller@10440000 { |
90 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | |
91 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | |
92 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | |
93 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, | |
94 | <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; | |
95 | }; | |
96 | ||
64a57434 | 97 | pinctrl_0: pinctrl@11400000 { |
b533c868 | 98 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
99 | reg = <0x11400000 0x1000>; |
100 | interrupts = <0 47 0>; | |
101 | }; | |
102 | ||
103 | pinctrl_1: pinctrl@11000000 { | |
b533c868 | 104 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
105 | reg = <0x11000000 0x1000>; |
106 | interrupts = <0 46 0>; | |
107 | ||
108 | wakup_eint: wakeup-interrupt-controller { | |
109 | compatible = "samsung,exynos4210-wakeup-eint"; | |
110 | interrupt-parent = <&gic>; | |
111 | interrupts = <0 32 0>; | |
112 | }; | |
113 | }; | |
114 | ||
c63c5743 CC |
115 | adc: adc@126C0000 { |
116 | compatible = "samsung,exynos-adc-v1"; | |
117 | reg = <0x126C0000 0x100>, <0x10020718 0x4>; | |
118 | interrupt-parent = <&combiner>; | |
119 | interrupts = <10 3>; | |
120 | clocks = <&clock CLK_TSADC>; | |
121 | clock-names = "adc"; | |
122 | #io-channel-cells = <1>; | |
123 | io-channel-ranges; | |
124 | status = "disabled"; | |
125 | }; | |
126 | ||
64a57434 | 127 | pinctrl_2: pinctrl@03860000 { |
b533c868 | 128 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
129 | reg = <0x03860000 0x1000>; |
130 | interrupt-parent = <&combiner>; | |
131 | interrupts = <10 0>; | |
132 | }; | |
133 | ||
134 | pinctrl_3: pinctrl@106E0000 { | |
b533c868 | 135 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
136 | reg = <0x106E0000 0x1000>; |
137 | interrupts = <0 72 0>; | |
138 | }; | |
3a0d48f6 | 139 | |
7b9613ac CP |
140 | pmu_system_controller: system-controller@10020000 { |
141 | compatible = "samsung,exynos4212-pmu", "syscon"; | |
142 | }; | |
143 | ||
3a0d48f6 SK |
144 | g2d@10800000 { |
145 | compatible = "samsung,exynos4212-g2d"; | |
146 | reg = <0x10800000 0x1000>; | |
147 | interrupts = <0 89 0>; | |
1c75a78a | 148 | clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; |
cfc5652d | 149 | clock-names = "sclk_fimg2d", "fimg2d"; |
3a0d48f6 SK |
150 | status = "disabled"; |
151 | }; | |
582435b3 SN |
152 | |
153 | camera { | |
1c75a78a AH |
154 | clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, |
155 | <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; | |
582435b3 SN |
156 | clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; |
157 | ||
158 | fimc_0: fimc@11800000 { | |
159 | compatible = "samsung,exynos4212-fimc"; | |
160 | samsung,pix-limits = <4224 8192 1920 4224>; | |
161 | samsung,mainscaler-ext; | |
162 | samsung,isp-wb; | |
163 | samsung,cam-if; | |
164 | }; | |
165 | ||
166 | fimc_1: fimc@11810000 { | |
167 | compatible = "samsung,exynos4212-fimc"; | |
168 | samsung,pix-limits = <4224 8192 1920 4224>; | |
169 | samsung,mainscaler-ext; | |
170 | samsung,isp-wb; | |
171 | samsung,cam-if; | |
172 | }; | |
173 | ||
174 | fimc_2: fimc@11820000 { | |
175 | compatible = "samsung,exynos4212-fimc"; | |
176 | samsung,pix-limits = <4224 8192 1920 4224>; | |
177 | samsung,mainscaler-ext; | |
178 | samsung,isp-wb; | |
179 | samsung,lcd-wb; | |
180 | samsung,cam-if; | |
181 | }; | |
182 | ||
183 | fimc_3: fimc@11830000 { | |
184 | compatible = "samsung,exynos4212-fimc"; | |
185 | samsung,pix-limits = <1920 8192 1366 1920>; | |
186 | samsung,rotators = <0>; | |
187 | samsung,mainscaler-ext; | |
188 | samsung,isp-wb; | |
189 | samsung,lcd-wb; | |
190 | }; | |
191 | ||
192 | fimc_lite_0: fimc-lite@12390000 { | |
193 | compatible = "samsung,exynos4212-fimc-lite"; | |
194 | reg = <0x12390000 0x1000>; | |
195 | interrupts = <0 105 0>; | |
196 | samsung,power-domain = <&pd_isp>; | |
1c75a78a | 197 | clocks = <&clock CLK_FIMC_LITE0>; |
582435b3 SN |
198 | clock-names = "flite"; |
199 | status = "disabled"; | |
200 | }; | |
201 | ||
202 | fimc_lite_1: fimc-lite@123A0000 { | |
203 | compatible = "samsung,exynos4212-fimc-lite"; | |
204 | reg = <0x123A0000 0x1000>; | |
205 | interrupts = <0 106 0>; | |
206 | samsung,power-domain = <&pd_isp>; | |
1c75a78a | 207 | clocks = <&clock CLK_FIMC_LITE1>; |
582435b3 SN |
208 | clock-names = "flite"; |
209 | status = "disabled"; | |
210 | }; | |
211 | ||
212 | fimc_is: fimc-is@12000000 { | |
213 | compatible = "samsung,exynos4212-fimc-is", "simple-bus"; | |
214 | reg = <0x12000000 0x260000>; | |
215 | interrupts = <0 90 0>, <0 95 0>; | |
216 | samsung,power-domain = <&pd_isp>; | |
1c75a78a AH |
217 | clocks = <&clock CLK_FIMC_LITE0>, |
218 | <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, | |
219 | <&clock CLK_PPMUISPMX>, | |
220 | <&clock CLK_MOUT_MPLL_USER_T>, | |
221 | <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, | |
222 | <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, | |
223 | <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>, | |
224 | <&clock CLK_DIV_MCUISP0>, | |
225 | <&clock CLK_DIV_MCUISP1>, | |
226 | <&clock CLK_SCLK_UART_ISP>, | |
227 | <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, | |
228 | <&clock CLK_ACLK400_MCUISP>, | |
229 | <&clock CLK_DIV_ACLK400_MCUISP>; | |
582435b3 SN |
230 | clock-names = "lite0", "lite1", "ppmuispx", |
231 | "ppmuispmx", "mpll", "isp", | |
232 | "drc", "fd", "mcuisp", | |
233 | "ispdiv0", "ispdiv1", "mcuispdiv0", | |
234 | "mcuispdiv1", "uart", "aclk200", | |
235 | "div_aclk200", "aclk400mcuisp", | |
236 | "div_aclk400mcuisp"; | |
237 | #address-cells = <1>; | |
238 | #size-cells = <1>; | |
239 | ranges; | |
240 | status = "disabled"; | |
241 | ||
242 | pmu { | |
243 | reg = <0x10020000 0x3000>; | |
244 | }; | |
245 | ||
246 | i2c1_isp: i2c-isp@12140000 { | |
247 | compatible = "samsung,exynos4212-i2c-isp"; | |
248 | reg = <0x12140000 0x100>; | |
1c75a78a | 249 | clocks = <&clock CLK_I2C1_ISP>; |
582435b3 SN |
250 | clock-names = "i2c_isp"; |
251 | #address-cells = <1>; | |
252 | #size-cells = <0>; | |
253 | }; | |
254 | }; | |
255 | }; | |
56d52bfb TF |
256 | |
257 | mshc_0: mmc@12550000 { | |
258 | compatible = "samsung,exynos4412-dw-mshc"; | |
259 | reg = <0x12550000 0x1000>; | |
260 | interrupts = <0 77 0>; | |
261 | #address-cells = <1>; | |
262 | #size-cells = <0>; | |
263 | fifo-depth = <0x80>; | |
1c75a78a | 264 | clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; |
56d52bfb TF |
265 | clock-names = "biu", "ciu"; |
266 | status = "disabled"; | |
267 | }; | |
26bbd41f CP |
268 | |
269 | exynos-usbphy@125B0000 { | |
270 | compatible = "samsung,exynos4x12-usb2-phy"; | |
271 | samsung,sysreg-phandle = <&sys_reg>; | |
272 | }; | |
0f7238a1 | 273 | }; |