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b074abb7 KK |
1 | /* |
2 | * SAMSUNG EXYNOS5250 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. | |
8 | * EXYNOS5250 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, | |
13 | * additional nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
fe273c3e | 20 | #include <dt-bindings/clock/exynos5250.h> |
e6c21cba | 21 | #include "exynos5.dtsi" |
3799279f | 22 | #include "exynos5250-pinctrl.dtsi" |
9843a223 | 23 | #include "exynos4-cpu-thermal.dtsi" |
602408e3 | 24 | #include <dt-bindings/clock/exynos-audss-clk.h> |
b074abb7 KK |
25 | |
26 | / { | |
8bdb31b4 | 27 | compatible = "samsung,exynos5250", "samsung,exynos5"; |
b074abb7 | 28 | |
79989ba3 TA |
29 | aliases { |
30 | spi0 = &spi_0; | |
31 | spi1 = &spi_1; | |
32 | spi2 = &spi_2; | |
1128658a SAB |
33 | gsc0 = &gsc_0; |
34 | gsc1 = &gsc_1; | |
35 | gsc2 = &gsc_2; | |
36 | gsc3 = &gsc_3; | |
c8149df0 YK |
37 | mshc0 = &mmc_0; |
38 | mshc1 = &mmc_1; | |
39 | mshc2 = &mmc_2; | |
40 | mshc3 = &mmc_3; | |
b9fa3e7b AK |
41 | i2c0 = &i2c_0; |
42 | i2c1 = &i2c_1; | |
43 | i2c2 = &i2c_2; | |
44 | i2c3 = &i2c_3; | |
45 | i2c4 = &i2c_4; | |
46 | i2c5 = &i2c_5; | |
47 | i2c6 = &i2c_6; | |
48 | i2c7 = &i2c_7; | |
49 | i2c8 = &i2c_8; | |
ba0d7ed3 | 50 | i2c9 = &i2c_9; |
f8bfe2b0 TA |
51 | pinctrl0 = &pinctrl_0; |
52 | pinctrl1 = &pinctrl_1; | |
53 | pinctrl2 = &pinctrl_2; | |
54 | pinctrl3 = &pinctrl_3; | |
79989ba3 TA |
55 | }; |
56 | ||
1897d2f3 CK |
57 | cpus { |
58 | #address-cells = <1>; | |
59 | #size-cells = <0>; | |
60 | ||
bf4a0bed | 61 | cpu0: cpu@0 { |
1897d2f3 CK |
62 | device_type = "cpu"; |
63 | compatible = "arm,cortex-a15"; | |
64 | reg = <0>; | |
0da80563 | 65 | clock-frequency = <1700000000>; |
bf4a0bed LM |
66 | cooling-min-level = <15>; |
67 | cooling-max-level = <9>; | |
68 | #cooling-cells = <2>; /* min followed by max */ | |
1897d2f3 CK |
69 | }; |
70 | cpu@1 { | |
71 | device_type = "cpu"; | |
72 | compatible = "arm,cortex-a15"; | |
73 | reg = <1>; | |
0da80563 | 74 | clock-frequency = <1700000000>; |
1897d2f3 | 75 | }; |
79989ba3 TA |
76 | }; |
77 | ||
b3205dea SK |
78 | sysram@02020000 { |
79 | compatible = "mmio-sram"; | |
80 | reg = <0x02020000 0x30000>; | |
81 | #address-cells = <1>; | |
82 | #size-cells = <1>; | |
83 | ranges = <0 0x02020000 0x30000>; | |
84 | ||
85 | smp-sysram@0 { | |
86 | compatible = "samsung,exynos4210-sysram"; | |
87 | reg = <0x0 0x1000>; | |
88 | }; | |
89 | ||
90 | smp-sysram@2f000 { | |
91 | compatible = "samsung,exynos4210-sysram-ns"; | |
92 | reg = <0x2f000 0x1000>; | |
93 | }; | |
94 | }; | |
95 | ||
c31f566d | 96 | pd_gsc: gsc-power-domain@10044000 { |
6f9e95e6 PK |
97 | compatible = "samsung,exynos4210-pd"; |
98 | reg = <0x10044000 0x20>; | |
0da65870 | 99 | #power-domain-cells = <0>; |
6f9e95e6 PK |
100 | }; |
101 | ||
c31f566d | 102 | pd_mfc: mfc-power-domain@10044040 { |
6f9e95e6 PK |
103 | compatible = "samsung,exynos4210-pd"; |
104 | reg = <0x10044040 0x20>; | |
0da65870 | 105 | #power-domain-cells = <0>; |
6f9e95e6 PK |
106 | }; |
107 | ||
2d2c9a8d AH |
108 | pd_disp1: disp1-power-domain@100440A0 { |
109 | compatible = "samsung,exynos4210-pd"; | |
110 | reg = <0x100440A0 0x20>; | |
111 | #power-domain-cells = <0>; | |
112 | }; | |
113 | ||
c31f566d | 114 | clock: clock-controller@10010000 { |
d8bafc87 TA |
115 | compatible = "samsung,exynos5250-clock"; |
116 | reg = <0x10010000 0x30000>; | |
117 | #clock-cells = <1>; | |
118 | }; | |
119 | ||
bba23d95 PV |
120 | clock_audss: audss-clock-controller@3810000 { |
121 | compatible = "samsung,exynos5250-audss-clock"; | |
122 | reg = <0x03810000 0x0C>; | |
123 | #clock-cells = <1>; | |
fe273c3e AH |
124 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, |
125 | <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; | |
c08ceea3 | 126 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
bba23d95 PV |
127 | }; |
128 | ||
2b7da988 AG |
129 | timer { |
130 | compatible = "arm,armv7-timer"; | |
131 | interrupts = <1 13 0xf08>, | |
132 | <1 14 0xf08>, | |
133 | <1 11 0xf08>, | |
134 | <1 10 0xf08>; | |
4d594dd3 YK |
135 | /* Unfortunately we need this since some versions of U-Boot |
136 | * on Exynos don't set the CNTFRQ register, so we need the | |
137 | * value from DT. | |
138 | */ | |
139 | clock-frequency = <24000000>; | |
b074abb7 KK |
140 | }; |
141 | ||
bbd9700a TA |
142 | mct@101C0000 { |
143 | compatible = "samsung,exynos4210-mct"; | |
144 | reg = <0x101C0000 0x800>; | |
145 | interrupt-controller; | |
f27b9075 | 146 | #interrupt-cells = <2>; |
bbd9700a TA |
147 | interrupt-parent = <&mct_map>; |
148 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | |
149 | <4 0>, <5 0>; | |
fe273c3e | 150 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
2de6847c | 151 | clock-names = "fin_pll", "mct"; |
bbd9700a TA |
152 | |
153 | mct_map: mct-map { | |
154 | #interrupt-cells = <2>; | |
155 | #address-cells = <0>; | |
156 | #size-cells = <0>; | |
157 | interrupt-map = <0x0 0 &combiner 23 3>, | |
158 | <0x1 0 &combiner 23 4>, | |
159 | <0x2 0 &combiner 25 2>, | |
160 | <0x3 0 &combiner 25 3>, | |
161 | <0x4 0 &gic 0 120 0>, | |
162 | <0x5 0 &gic 0 121 0>; | |
163 | }; | |
164 | }; | |
165 | ||
4f801e59 CP |
166 | pmu { |
167 | compatible = "arm,cortex-a15-pmu"; | |
168 | interrupt-parent = <&combiner>; | |
169 | interrupts = <1 2>, <22 4>; | |
170 | }; | |
171 | ||
f8bfe2b0 TA |
172 | pinctrl_0: pinctrl@11400000 { |
173 | compatible = "samsung,exynos5250-pinctrl"; | |
174 | reg = <0x11400000 0x1000>; | |
175 | interrupts = <0 46 0>; | |
176 | ||
177 | wakup_eint: wakeup-interrupt-controller { | |
178 | compatible = "samsung,exynos4210-wakeup-eint"; | |
179 | interrupt-parent = <&gic>; | |
180 | interrupts = <0 32 0>; | |
181 | }; | |
182 | }; | |
183 | ||
184 | pinctrl_1: pinctrl@13400000 { | |
185 | compatible = "samsung,exynos5250-pinctrl"; | |
186 | reg = <0x13400000 0x1000>; | |
187 | interrupts = <0 45 0>; | |
188 | }; | |
189 | ||
190 | pinctrl_2: pinctrl@10d10000 { | |
191 | compatible = "samsung,exynos5250-pinctrl"; | |
192 | reg = <0x10d10000 0x1000>; | |
193 | interrupts = <0 50 0>; | |
194 | }; | |
195 | ||
0abb6aea | 196 | pinctrl_3: pinctrl@03860000 { |
f8bfe2b0 | 197 | compatible = "samsung,exynos5250-pinctrl"; |
0abb6aea | 198 | reg = <0x03860000 0x1000>; |
f8bfe2b0 TA |
199 | interrupts = <0 47 0>; |
200 | }; | |
201 | ||
c680036a LKA |
202 | pmu_system_controller: system-controller@10040000 { |
203 | compatible = "samsung,exynos5250-pmu", "syscon"; | |
204 | reg = <0x10040000 0x5000>; | |
d19bb397 TF |
205 | clock-names = "clkout16"; |
206 | clocks = <&clock CLK_FIN_PLL>; | |
207 | #clock-cells = <1>; | |
8b283c02 MZ |
208 | interrupt-controller; |
209 | #interrupt-cells = <3>; | |
210 | interrupt-parent = <&gic>; | |
c680036a LKA |
211 | }; |
212 | ||
dfbbdbf4 VG |
213 | sysreg_system_controller: syscon@10050000 { |
214 | compatible = "samsung,exynos5-sysreg", "syscon"; | |
215 | reg = <0x10050000 0x5000>; | |
216 | }; | |
217 | ||
1d287620 LKA |
218 | watchdog@101D0000 { |
219 | compatible = "samsung,exynos5250-wdt"; | |
220 | reg = <0x101D0000 0x100>; | |
221 | interrupts = <0 42 0>; | |
fe273c3e | 222 | clocks = <&clock CLK_WDT>; |
2de6847c | 223 | clock-names = "watchdog"; |
1d287620 | 224 | samsung,syscon-phandle = <&pmu_system_controller>; |
b074abb7 KK |
225 | }; |
226 | ||
21aa5217 SK |
227 | g2d@10850000 { |
228 | compatible = "samsung,exynos5250-g2d"; | |
229 | reg = <0x10850000 0x1000>; | |
230 | interrupts = <0 91 0>; | |
fe273c3e | 231 | clocks = <&clock CLK_G2D>; |
21aa5217 SK |
232 | clock-names = "fimg2d"; |
233 | }; | |
234 | ||
19fd45bf | 235 | mfc: codec@11000000 { |
2eae613b AK |
236 | compatible = "samsung,mfc-v6"; |
237 | reg = <0x11000000 0x10000>; | |
238 | interrupts = <0 96 0>; | |
0da65870 | 239 | power-domains = <&pd_mfc>; |
fe273c3e | 240 | clocks = <&clock CLK_MFC>; |
8b6bea33 | 241 | clock-names = "mfc"; |
2eae613b AK |
242 | }; |
243 | ||
19fd45bf | 244 | rtc: rtc@101E0000 { |
fe273c3e | 245 | clocks = <&clock CLK_RTC>; |
2de6847c | 246 | clock-names = "rtc"; |
8b283c02 | 247 | interrupt-parent = <&pmu_system_controller>; |
65cedf0e | 248 | status = "disabled"; |
b074abb7 KK |
249 | }; |
250 | ||
9843a223 | 251 | tmu: tmu@10060000 { |
ef405e04 ADK |
252 | compatible = "samsung,exynos5250-tmu"; |
253 | reg = <0x10060000 0x100>; | |
254 | interrupts = <0 65 0>; | |
fe273c3e | 255 | clocks = <&clock CLK_TMU>; |
2de6847c | 256 | clock-names = "tmu_apbif"; |
9843a223 | 257 | #include "exynos4412-tmu-sensor-conf.dtsi" |
ef405e04 ADK |
258 | }; |
259 | ||
bf4a0bed LM |
260 | thermal-zones { |
261 | cpu_thermal: cpu-thermal { | |
9843a223 LM |
262 | polling-delay-passive = <0>; |
263 | polling-delay = <0>; | |
264 | thermal-sensors = <&tmu 0>; | |
265 | ||
bf4a0bed LM |
266 | cooling-maps { |
267 | map0 { | |
268 | /* Corresponds to 800MHz at freq_table */ | |
269 | cooling-device = <&cpu0 9 9>; | |
270 | }; | |
271 | map1 { | |
272 | /* Corresponds to 200MHz at freq_table */ | |
273 | cooling-device = <&cpu0 15 15>; | |
274 | }; | |
275 | }; | |
276 | }; | |
277 | }; | |
278 | ||
b074abb7 | 279 | serial@12C00000 { |
fe273c3e | 280 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
2de6847c | 281 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
282 | }; |
283 | ||
284 | serial@12C10000 { | |
fe273c3e | 285 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
2de6847c | 286 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
287 | }; |
288 | ||
289 | serial@12C20000 { | |
fe273c3e | 290 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
2de6847c | 291 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
292 | }; |
293 | ||
294 | serial@12C30000 { | |
fe273c3e | 295 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
2de6847c | 296 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
297 | }; |
298 | ||
19fd45bf | 299 | sata: sata@122F0000 { |
ba0d7ed3 YK |
300 | compatible = "snps,dwc-ahci"; |
301 | samsung,sata-freq = <66>; | |
c47d244a VA |
302 | reg = <0x122F0000 0x1ff>; |
303 | interrupts = <0 115 0>; | |
fe273c3e | 304 | clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; |
2de6847c | 305 | clock-names = "sata", "sclk_sata"; |
ba0d7ed3 YK |
306 | phys = <&sata_phy>; |
307 | phy-names = "sata-phy"; | |
308 | status = "disabled"; | |
c47d244a VA |
309 | }; |
310 | ||
ba0d7ed3 YK |
311 | sata_phy: sata-phy@12170000 { |
312 | compatible = "samsung,exynos5250-sata-phy"; | |
c47d244a | 313 | reg = <0x12170000 0x1ff>; |
e06e1067 | 314 | clocks = <&clock CLK_SATA_PHYCTRL>; |
ba0d7ed3 YK |
315 | clock-names = "sata_phyctrl"; |
316 | #phy-cells = <0>; | |
317 | samsung,syscon-phandle = <&pmu_system_controller>; | |
318 | status = "disabled"; | |
c47d244a VA |
319 | }; |
320 | ||
b9fa3e7b | 321 | i2c_0: i2c@12C60000 { |
b074abb7 KK |
322 | compatible = "samsung,s3c2440-i2c"; |
323 | reg = <0x12C60000 0x100>; | |
324 | interrupts = <0 56 0>; | |
009f7c9f TA |
325 | #address-cells = <1>; |
326 | #size-cells = <0>; | |
fe273c3e | 327 | clocks = <&clock CLK_I2C0>; |
2de6847c | 328 | clock-names = "i2c"; |
f8bfe2b0 TA |
329 | pinctrl-names = "default"; |
330 | pinctrl-0 = <&i2c0_bus>; | |
1888eb75 | 331 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 332 | status = "disabled"; |
b074abb7 KK |
333 | }; |
334 | ||
b9fa3e7b | 335 | i2c_1: i2c@12C70000 { |
b074abb7 KK |
336 | compatible = "samsung,s3c2440-i2c"; |
337 | reg = <0x12C70000 0x100>; | |
338 | interrupts = <0 57 0>; | |
009f7c9f TA |
339 | #address-cells = <1>; |
340 | #size-cells = <0>; | |
fe273c3e | 341 | clocks = <&clock CLK_I2C1>; |
2de6847c | 342 | clock-names = "i2c"; |
f8bfe2b0 TA |
343 | pinctrl-names = "default"; |
344 | pinctrl-0 = <&i2c1_bus>; | |
1888eb75 | 345 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 346 | status = "disabled"; |
b074abb7 KK |
347 | }; |
348 | ||
b9fa3e7b | 349 | i2c_2: i2c@12C80000 { |
b074abb7 KK |
350 | compatible = "samsung,s3c2440-i2c"; |
351 | reg = <0x12C80000 0x100>; | |
352 | interrupts = <0 58 0>; | |
009f7c9f TA |
353 | #address-cells = <1>; |
354 | #size-cells = <0>; | |
fe273c3e | 355 | clocks = <&clock CLK_I2C2>; |
2de6847c | 356 | clock-names = "i2c"; |
f8bfe2b0 TA |
357 | pinctrl-names = "default"; |
358 | pinctrl-0 = <&i2c2_bus>; | |
1888eb75 | 359 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 360 | status = "disabled"; |
b074abb7 KK |
361 | }; |
362 | ||
b9fa3e7b | 363 | i2c_3: i2c@12C90000 { |
b074abb7 KK |
364 | compatible = "samsung,s3c2440-i2c"; |
365 | reg = <0x12C90000 0x100>; | |
366 | interrupts = <0 59 0>; | |
009f7c9f TA |
367 | #address-cells = <1>; |
368 | #size-cells = <0>; | |
fe273c3e | 369 | clocks = <&clock CLK_I2C3>; |
2de6847c | 370 | clock-names = "i2c"; |
f8bfe2b0 TA |
371 | pinctrl-names = "default"; |
372 | pinctrl-0 = <&i2c3_bus>; | |
1888eb75 | 373 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 374 | status = "disabled"; |
b074abb7 KK |
375 | }; |
376 | ||
b9fa3e7b | 377 | i2c_4: i2c@12CA0000 { |
b074abb7 KK |
378 | compatible = "samsung,s3c2440-i2c"; |
379 | reg = <0x12CA0000 0x100>; | |
380 | interrupts = <0 60 0>; | |
009f7c9f TA |
381 | #address-cells = <1>; |
382 | #size-cells = <0>; | |
fe273c3e | 383 | clocks = <&clock CLK_I2C4>; |
2de6847c | 384 | clock-names = "i2c"; |
f8bfe2b0 TA |
385 | pinctrl-names = "default"; |
386 | pinctrl-0 = <&i2c4_bus>; | |
6ad8ebff | 387 | status = "disabled"; |
b074abb7 KK |
388 | }; |
389 | ||
b9fa3e7b | 390 | i2c_5: i2c@12CB0000 { |
b074abb7 KK |
391 | compatible = "samsung,s3c2440-i2c"; |
392 | reg = <0x12CB0000 0x100>; | |
393 | interrupts = <0 61 0>; | |
009f7c9f TA |
394 | #address-cells = <1>; |
395 | #size-cells = <0>; | |
fe273c3e | 396 | clocks = <&clock CLK_I2C5>; |
2de6847c | 397 | clock-names = "i2c"; |
f8bfe2b0 TA |
398 | pinctrl-names = "default"; |
399 | pinctrl-0 = <&i2c5_bus>; | |
6ad8ebff | 400 | status = "disabled"; |
b074abb7 KK |
401 | }; |
402 | ||
b9fa3e7b | 403 | i2c_6: i2c@12CC0000 { |
b074abb7 KK |
404 | compatible = "samsung,s3c2440-i2c"; |
405 | reg = <0x12CC0000 0x100>; | |
406 | interrupts = <0 62 0>; | |
009f7c9f TA |
407 | #address-cells = <1>; |
408 | #size-cells = <0>; | |
fe273c3e | 409 | clocks = <&clock CLK_I2C6>; |
2de6847c | 410 | clock-names = "i2c"; |
f8bfe2b0 TA |
411 | pinctrl-names = "default"; |
412 | pinctrl-0 = <&i2c6_bus>; | |
6ad8ebff | 413 | status = "disabled"; |
b074abb7 KK |
414 | }; |
415 | ||
b9fa3e7b | 416 | i2c_7: i2c@12CD0000 { |
b074abb7 KK |
417 | compatible = "samsung,s3c2440-i2c"; |
418 | reg = <0x12CD0000 0x100>; | |
419 | interrupts = <0 63 0>; | |
009f7c9f TA |
420 | #address-cells = <1>; |
421 | #size-cells = <0>; | |
fe273c3e | 422 | clocks = <&clock CLK_I2C7>; |
2de6847c | 423 | clock-names = "i2c"; |
f8bfe2b0 TA |
424 | pinctrl-names = "default"; |
425 | pinctrl-0 = <&i2c7_bus>; | |
6ad8ebff | 426 | status = "disabled"; |
3e3e9ce4 RS |
427 | }; |
428 | ||
b9fa3e7b | 429 | i2c_8: i2c@12CE0000 { |
3e3e9ce4 RS |
430 | compatible = "samsung,s3c2440-hdmiphy-i2c"; |
431 | reg = <0x12CE0000 0x1000>; | |
432 | interrupts = <0 64 0>; | |
433 | #address-cells = <1>; | |
434 | #size-cells = <0>; | |
fe273c3e | 435 | clocks = <&clock CLK_I2C_HDMI>; |
2de6847c | 436 | clock-names = "i2c"; |
6ad8ebff | 437 | status = "disabled"; |
24025f6f OJ |
438 | }; |
439 | ||
ba0d7ed3 | 440 | i2c_9: i2c@121D0000 { |
c47d244a VA |
441 | compatible = "samsung,exynos5-sata-phy-i2c"; |
442 | reg = <0x121D0000 0x100>; | |
443 | #address-cells = <1>; | |
444 | #size-cells = <0>; | |
fe273c3e | 445 | clocks = <&clock CLK_SATA_PHYI2C>; |
2de6847c | 446 | clock-names = "i2c"; |
6ad8ebff | 447 | status = "disabled"; |
b074abb7 KK |
448 | }; |
449 | ||
79989ba3 TA |
450 | spi_0: spi@12d20000 { |
451 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 452 | status = "disabled"; |
79989ba3 TA |
453 | reg = <0x12d20000 0x100>; |
454 | interrupts = <0 66 0>; | |
a4a8a9d3 PV |
455 | dmas = <&pdma0 5 |
456 | &pdma0 4>; | |
457 | dma-names = "tx", "rx"; | |
79989ba3 TA |
458 | #address-cells = <1>; |
459 | #size-cells = <0>; | |
fe273c3e | 460 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
2de6847c | 461 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
462 | pinctrl-names = "default"; |
463 | pinctrl-0 = <&spi0_bus>; | |
79989ba3 TA |
464 | }; |
465 | ||
466 | spi_1: spi@12d30000 { | |
467 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 468 | status = "disabled"; |
79989ba3 TA |
469 | reg = <0x12d30000 0x100>; |
470 | interrupts = <0 67 0>; | |
a4a8a9d3 PV |
471 | dmas = <&pdma1 5 |
472 | &pdma1 4>; | |
473 | dma-names = "tx", "rx"; | |
79989ba3 TA |
474 | #address-cells = <1>; |
475 | #size-cells = <0>; | |
fe273c3e | 476 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
2de6847c | 477 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
478 | pinctrl-names = "default"; |
479 | pinctrl-0 = <&spi1_bus>; | |
79989ba3 TA |
480 | }; |
481 | ||
482 | spi_2: spi@12d40000 { | |
483 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 484 | status = "disabled"; |
79989ba3 TA |
485 | reg = <0x12d40000 0x100>; |
486 | interrupts = <0 68 0>; | |
a4a8a9d3 PV |
487 | dmas = <&pdma0 7 |
488 | &pdma0 6>; | |
489 | dma-names = "tx", "rx"; | |
79989ba3 TA |
490 | #address-cells = <1>; |
491 | #size-cells = <0>; | |
fe273c3e | 492 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
2de6847c | 493 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
494 | pinctrl-names = "default"; |
495 | pinctrl-0 = <&spi2_bus>; | |
79989ba3 TA |
496 | }; |
497 | ||
c8149df0 | 498 | mmc_0: mmc@12200000 { |
906fd84e YK |
499 | compatible = "samsung,exynos5250-dw-mshc"; |
500 | interrupts = <0 75 0>; | |
501 | #address-cells = <1>; | |
502 | #size-cells = <0>; | |
84bd48a0 | 503 | reg = <0x12200000 0x1000>; |
fe273c3e | 504 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; |
2de6847c | 505 | clock-names = "biu", "ciu"; |
46285a90 | 506 | fifo-depth = <0x80>; |
e908d5c5 | 507 | status = "disabled"; |
84bd48a0 TA |
508 | }; |
509 | ||
c8149df0 | 510 | mmc_1: mmc@12210000 { |
906fd84e YK |
511 | compatible = "samsung,exynos5250-dw-mshc"; |
512 | interrupts = <0 76 0>; | |
513 | #address-cells = <1>; | |
514 | #size-cells = <0>; | |
84bd48a0 | 515 | reg = <0x12210000 0x1000>; |
fe273c3e | 516 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; |
2de6847c | 517 | clock-names = "biu", "ciu"; |
46285a90 | 518 | fifo-depth = <0x80>; |
e908d5c5 | 519 | status = "disabled"; |
84bd48a0 TA |
520 | }; |
521 | ||
c8149df0 | 522 | mmc_2: mmc@12220000 { |
906fd84e YK |
523 | compatible = "samsung,exynos5250-dw-mshc"; |
524 | interrupts = <0 77 0>; | |
525 | #address-cells = <1>; | |
526 | #size-cells = <0>; | |
84bd48a0 | 527 | reg = <0x12220000 0x1000>; |
fe273c3e | 528 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; |
2de6847c | 529 | clock-names = "biu", "ciu"; |
46285a90 | 530 | fifo-depth = <0x80>; |
e908d5c5 | 531 | status = "disabled"; |
84bd48a0 TA |
532 | }; |
533 | ||
c8149df0 | 534 | mmc_3: mmc@12230000 { |
84bd48a0 TA |
535 | compatible = "samsung,exynos5250-dw-mshc"; |
536 | reg = <0x12230000 0x1000>; | |
537 | interrupts = <0 78 0>; | |
538 | #address-cells = <1>; | |
539 | #size-cells = <0>; | |
fe273c3e | 540 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; |
2de6847c | 541 | clock-names = "biu", "ciu"; |
46285a90 | 542 | fifo-depth = <0x80>; |
e908d5c5 | 543 | status = "disabled"; |
84bd48a0 TA |
544 | }; |
545 | ||
28a48058 | 546 | i2s0: i2s@03830000 { |
64183656 | 547 | compatible = "samsung,s5pv210-i2s"; |
328aee4b | 548 | status = "disabled"; |
a0b5f81e | 549 | reg = <0x03830000 0x100>; |
4c4c7463 PV |
550 | dmas = <&pdma0 10 |
551 | &pdma0 9 | |
552 | &pdma0 8>; | |
553 | dma-names = "tx", "rx", "tx-sec"; | |
916ec47e PV |
554 | clocks = <&clock_audss EXYNOS_I2S_BUS>, |
555 | <&clock_audss EXYNOS_I2S_BUS>, | |
556 | <&clock_audss EXYNOS_SCLK_I2S>; | |
557 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
a0b5f81e | 558 | samsung,idma-addr = <0x03000000>; |
f8bfe2b0 TA |
559 | pinctrl-names = "default"; |
560 | pinctrl-0 = <&i2s0_bus>; | |
4c4c7463 PV |
561 | }; |
562 | ||
28a48058 | 563 | i2s1: i2s@12D60000 { |
64183656 | 564 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 565 | status = "disabled"; |
a0b5f81e MB |
566 | reg = <0x12D60000 0x100>; |
567 | dmas = <&pdma1 12 | |
568 | &pdma1 11>; | |
569 | dma-names = "tx", "rx"; | |
fe273c3e | 570 | clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; |
916ec47e | 571 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
572 | pinctrl-names = "default"; |
573 | pinctrl-0 = <&i2s1_bus>; | |
4c4c7463 PV |
574 | }; |
575 | ||
28a48058 | 576 | i2s2: i2s@12D70000 { |
64183656 | 577 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 578 | status = "disabled"; |
a0b5f81e MB |
579 | reg = <0x12D70000 0x100>; |
580 | dmas = <&pdma0 12 | |
581 | &pdma0 11>; | |
582 | dma-names = "tx", "rx"; | |
fe273c3e | 583 | clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; |
916ec47e | 584 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
585 | pinctrl-names = "default"; |
586 | pinctrl-0 = <&i2s2_bus>; | |
4c4c7463 PV |
587 | }; |
588 | ||
0b3dc97e VG |
589 | usb@12000000 { |
590 | compatible = "samsung,exynos5250-dwusb3"; | |
fe273c3e | 591 | clocks = <&clock CLK_USB3>; |
0b3dc97e VG |
592 | clock-names = "usbdrd30"; |
593 | #address-cells = <1>; | |
594 | #size-cells = <1>; | |
595 | ranges; | |
596 | ||
0526f276 | 597 | usbdrd_dwc3: dwc3 { |
0b3dc97e VG |
598 | compatible = "synopsys,dwc3"; |
599 | reg = <0x12000000 0x10000>; | |
600 | interrupts = <0 72 0>; | |
7a4cf0fd VG |
601 | phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; |
602 | phy-names = "usb2-phy", "usb3-phy"; | |
896db3b3 VG |
603 | }; |
604 | }; | |
605 | ||
517083f4 VG |
606 | usbdrd_phy: phy@12100000 { |
607 | compatible = "samsung,exynos5250-usbdrd-phy"; | |
608 | reg = <0x12100000 0x100>; | |
609 | clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; | |
610 | clock-names = "phy", "ref"; | |
611 | samsung,pmu-syscon = <&pmu_system_controller>; | |
612 | #phy-cells = <1>; | |
613 | }; | |
614 | ||
19fd45bf | 615 | ehci: usb@12110000 { |
13cbd1e3 VG |
616 | compatible = "samsung,exynos4210-ehci"; |
617 | reg = <0x12110000 0x100>; | |
618 | interrupts = <0 71 0>; | |
b3cd7d87 | 619 | |
fe273c3e | 620 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 621 | clock-names = "usbhost"; |
dba2f058 KD |
622 | #address-cells = <1>; |
623 | #size-cells = <0>; | |
624 | port@0 { | |
625 | reg = <0>; | |
626 | phys = <&usb2_phy_gen 1>; | |
627 | }; | |
13cbd1e3 VG |
628 | }; |
629 | ||
19fd45bf | 630 | ohci: usb@12120000 { |
7d40d867 VG |
631 | compatible = "samsung,exynos4210-ohci"; |
632 | reg = <0x12120000 0x100>; | |
633 | interrupts = <0 71 0>; | |
b3cd7d87 | 634 | |
fe273c3e | 635 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 636 | clock-names = "usbhost"; |
dba2f058 KD |
637 | #address-cells = <1>; |
638 | #size-cells = <0>; | |
639 | port@0 { | |
640 | reg = <0>; | |
641 | phys = <&usb2_phy_gen 1>; | |
642 | }; | |
7d40d867 VG |
643 | }; |
644 | ||
dba2f058 KD |
645 | usb2_phy_gen: phy@12130000 { |
646 | compatible = "samsung,exynos5250-usb2-phy"; | |
647 | reg = <0x12130000 0x100>; | |
648 | clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; | |
649 | clock-names = "phy", "ref"; | |
650 | #phy-cells = <1>; | |
651 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
652 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
653 | }; | |
654 | ||
022cf308 LKA |
655 | pwm: pwm@12dd0000 { |
656 | compatible = "samsung,exynos4210-pwm"; | |
657 | reg = <0x12dd0000 0x100>; | |
658 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
659 | #pwm-cells = <3>; | |
fe273c3e | 660 | clocks = <&clock CLK_PWM>; |
022cf308 LKA |
661 | clock-names = "timers"; |
662 | }; | |
663 | ||
b074abb7 KK |
664 | amba { |
665 | #address-cells = <1>; | |
666 | #size-cells = <1>; | |
667 | compatible = "arm,amba-bus"; | |
668 | interrupt-parent = <&gic>; | |
669 | ranges; | |
670 | ||
671 | pdma0: pdma@121A0000 { | |
672 | compatible = "arm,pl330", "arm,primecell"; | |
673 | reg = <0x121A0000 0x1000>; | |
674 | interrupts = <0 34 0>; | |
fe273c3e | 675 | clocks = <&clock CLK_PDMA0>; |
2de6847c | 676 | clock-names = "apb_pclk"; |
42cf2098 PV |
677 | #dma-cells = <1>; |
678 | #dma-channels = <8>; | |
679 | #dma-requests = <32>; | |
b074abb7 KK |
680 | }; |
681 | ||
682 | pdma1: pdma@121B0000 { | |
683 | compatible = "arm,pl330", "arm,primecell"; | |
684 | reg = <0x121B0000 0x1000>; | |
685 | interrupts = <0 35 0>; | |
fe273c3e | 686 | clocks = <&clock CLK_PDMA1>; |
2de6847c | 687 | clock-names = "apb_pclk"; |
42cf2098 PV |
688 | #dma-cells = <1>; |
689 | #dma-channels = <8>; | |
690 | #dma-requests = <32>; | |
b074abb7 KK |
691 | }; |
692 | ||
009f7c9f | 693 | mdma0: mdma@10800000 { |
b074abb7 KK |
694 | compatible = "arm,pl330", "arm,primecell"; |
695 | reg = <0x10800000 0x1000>; | |
696 | interrupts = <0 33 0>; | |
fe273c3e | 697 | clocks = <&clock CLK_MDMA0>; |
2de6847c | 698 | clock-names = "apb_pclk"; |
42cf2098 PV |
699 | #dma-cells = <1>; |
700 | #dma-channels = <8>; | |
701 | #dma-requests = <1>; | |
b074abb7 KK |
702 | }; |
703 | ||
009f7c9f | 704 | mdma1: mdma@11C10000 { |
b074abb7 KK |
705 | compatible = "arm,pl330", "arm,primecell"; |
706 | reg = <0x11C10000 0x1000>; | |
707 | interrupts = <0 124 0>; | |
fe273c3e | 708 | clocks = <&clock CLK_MDMA1>; |
2de6847c | 709 | clock-names = "apb_pclk"; |
42cf2098 PV |
710 | #dma-cells = <1>; |
711 | #dma-channels = <8>; | |
712 | #dma-requests = <1>; | |
b074abb7 KK |
713 | }; |
714 | }; | |
715 | ||
c31f566d | 716 | gsc_0: gsc@13e00000 { |
1128658a SAB |
717 | compatible = "samsung,exynos5-gsc"; |
718 | reg = <0x13e00000 0x1000>; | |
719 | interrupts = <0 85 0>; | |
0da65870 | 720 | power-domains = <&pd_gsc>; |
fe273c3e | 721 | clocks = <&clock CLK_GSCL0>; |
2de6847c | 722 | clock-names = "gscl"; |
1128658a SAB |
723 | }; |
724 | ||
c31f566d | 725 | gsc_1: gsc@13e10000 { |
1128658a SAB |
726 | compatible = "samsung,exynos5-gsc"; |
727 | reg = <0x13e10000 0x1000>; | |
728 | interrupts = <0 86 0>; | |
0da65870 | 729 | power-domains = <&pd_gsc>; |
fe273c3e | 730 | clocks = <&clock CLK_GSCL1>; |
2de6847c | 731 | clock-names = "gscl"; |
1128658a SAB |
732 | }; |
733 | ||
c31f566d | 734 | gsc_2: gsc@13e20000 { |
1128658a SAB |
735 | compatible = "samsung,exynos5-gsc"; |
736 | reg = <0x13e20000 0x1000>; | |
737 | interrupts = <0 87 0>; | |
0da65870 | 738 | power-domains = <&pd_gsc>; |
fe273c3e | 739 | clocks = <&clock CLK_GSCL2>; |
2de6847c | 740 | clock-names = "gscl"; |
1128658a SAB |
741 | }; |
742 | ||
c31f566d | 743 | gsc_3: gsc@13e30000 { |
1128658a SAB |
744 | compatible = "samsung,exynos5-gsc"; |
745 | reg = <0x13e30000 0x1000>; | |
746 | interrupts = <0 88 0>; | |
0da65870 | 747 | power-domains = <&pd_gsc>; |
fe273c3e | 748 | clocks = <&clock CLK_GSCL3>; |
2de6847c | 749 | clock-names = "gscl"; |
1128658a | 750 | }; |
566cf8ee | 751 | |
19fd45bf | 752 | hdmi: hdmi { |
0d1fc829 | 753 | compatible = "samsung,exynos4212-hdmi"; |
101250ce | 754 | reg = <0x14530000 0x70000>; |
2d2c9a8d | 755 | power-domains = <&pd_disp1>; |
566cf8ee | 756 | interrupts = <0 95 0>; |
fe273c3e AH |
757 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
758 | <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
759 | <&clock CLK_MOUT_HDMI>; | |
2de6847c | 760 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
27c16d19 | 761 | "sclk_hdmiphy", "mout_hdmi"; |
e54d90ec | 762 | samsung,syscon-phandle = <&pmu_system_controller>; |
566cf8ee | 763 | }; |
5af0d8a3 RS |
764 | |
765 | mixer { | |
0d1fc829 | 766 | compatible = "samsung,exynos5250-mixer"; |
5af0d8a3 | 767 | reg = <0x14450000 0x10000>; |
2d2c9a8d | 768 | power-domains = <&pd_disp1>; |
5af0d8a3 | 769 | interrupts = <0 94 0>; |
c950ea68 MS |
770 | clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, |
771 | <&clock CLK_SCLK_HDMI>; | |
772 | clock-names = "mixer", "hdmi", "sclk_hdmi"; | |
5af0d8a3 | 773 | }; |
ad4aebe1 | 774 | |
77899d53 VS |
775 | dp_phy: video-phy@10040720 { |
776 | compatible = "samsung,exynos5250-dp-video-phy"; | |
e93e5454 | 777 | samsung,pmu-syscon = <&pmu_system_controller>; |
77899d53 VS |
778 | #phy-cells = <0>; |
779 | }; | |
780 | ||
19fd45bf | 781 | dp: dp-controller@145B0000 { |
2d2c9a8d | 782 | power-domains = <&pd_disp1>; |
fe273c3e | 783 | clocks = <&clock CLK_DP>; |
0f72a9ec | 784 | clock-names = "dp"; |
77899d53 VS |
785 | phys = <&dp_phy>; |
786 | phy-names = "dp"; | |
ad4aebe1 | 787 | }; |
a7389cb1 | 788 | |
19fd45bf | 789 | fimd: fimd@14400000 { |
2d2c9a8d | 790 | power-domains = <&pd_disp1>; |
fe273c3e | 791 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
a7389cb1 LKA |
792 | clock-names = "sclk_fimd", "fimd"; |
793 | }; | |
f408f9db NKC |
794 | |
795 | adc: adc@12D10000 { | |
796 | compatible = "samsung,exynos-adc-v1"; | |
db9bf4d6 | 797 | reg = <0x12D10000 0x100>; |
f408f9db | 798 | interrupts = <0 106 0>; |
fe273c3e | 799 | clocks = <&clock CLK_ADC>; |
f408f9db NKC |
800 | clock-names = "adc"; |
801 | #io-channel-cells = <1>; | |
802 | io-channel-ranges; | |
db9bf4d6 | 803 | samsung,syscon-phandle = <&pmu_system_controller>; |
f408f9db NKC |
804 | status = "disabled"; |
805 | }; | |
183af252 NKC |
806 | |
807 | sss@10830000 { | |
808 | compatible = "samsung,exynos4210-secss"; | |
809 | reg = <0x10830000 0x10000>; | |
810 | interrupts = <0 112 0>; | |
e06e1067 | 811 | clocks = <&clock CLK_SSS>; |
183af252 NKC |
812 | clock-names = "secss"; |
813 | }; | |
b074abb7 | 814 | }; |