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b074abb7 KK |
1 | /* |
2 | * SAMSUNG EXYNOS5250 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. | |
8 | * EXYNOS5250 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, | |
13 | * additional nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
fe273c3e | 20 | #include <dt-bindings/clock/exynos5250.h> |
e6c21cba | 21 | #include "exynos5.dtsi" |
3799279f | 22 | #include "exynos5250-pinctrl.dtsi" |
b074abb7 | 23 | |
916ec47e | 24 | #include <dt-bindings/clk/exynos-audss-clk.h> |
b074abb7 KK |
25 | |
26 | / { | |
27 | compatible = "samsung,exynos5250"; | |
b074abb7 | 28 | |
79989ba3 TA |
29 | aliases { |
30 | spi0 = &spi_0; | |
31 | spi1 = &spi_1; | |
32 | spi2 = &spi_2; | |
1128658a SAB |
33 | gsc0 = &gsc_0; |
34 | gsc1 = &gsc_1; | |
35 | gsc2 = &gsc_2; | |
36 | gsc3 = &gsc_3; | |
c8149df0 YK |
37 | mshc0 = &mmc_0; |
38 | mshc1 = &mmc_1; | |
39 | mshc2 = &mmc_2; | |
40 | mshc3 = &mmc_3; | |
b9fa3e7b AK |
41 | i2c0 = &i2c_0; |
42 | i2c1 = &i2c_1; | |
43 | i2c2 = &i2c_2; | |
44 | i2c3 = &i2c_3; | |
45 | i2c4 = &i2c_4; | |
46 | i2c5 = &i2c_5; | |
47 | i2c6 = &i2c_6; | |
48 | i2c7 = &i2c_7; | |
49 | i2c8 = &i2c_8; | |
f8bfe2b0 TA |
50 | pinctrl0 = &pinctrl_0; |
51 | pinctrl1 = &pinctrl_1; | |
52 | pinctrl2 = &pinctrl_2; | |
53 | pinctrl3 = &pinctrl_3; | |
79989ba3 TA |
54 | }; |
55 | ||
1897d2f3 CK |
56 | cpus { |
57 | #address-cells = <1>; | |
58 | #size-cells = <0>; | |
59 | ||
60 | cpu@0 { | |
61 | device_type = "cpu"; | |
62 | compatible = "arm,cortex-a15"; | |
63 | reg = <0>; | |
0da80563 | 64 | clock-frequency = <1700000000>; |
1897d2f3 CK |
65 | }; |
66 | cpu@1 { | |
67 | device_type = "cpu"; | |
68 | compatible = "arm,cortex-a15"; | |
69 | reg = <1>; | |
0da80563 | 70 | clock-frequency = <1700000000>; |
1897d2f3 | 71 | }; |
79989ba3 TA |
72 | }; |
73 | ||
c31f566d | 74 | pd_gsc: gsc-power-domain@10044000 { |
6f9e95e6 PK |
75 | compatible = "samsung,exynos4210-pd"; |
76 | reg = <0x10044000 0x20>; | |
77 | }; | |
78 | ||
c31f566d | 79 | pd_mfc: mfc-power-domain@10044040 { |
6f9e95e6 PK |
80 | compatible = "samsung,exynos4210-pd"; |
81 | reg = <0x10044040 0x20>; | |
82 | }; | |
83 | ||
c31f566d | 84 | clock: clock-controller@10010000 { |
d8bafc87 TA |
85 | compatible = "samsung,exynos5250-clock"; |
86 | reg = <0x10010000 0x30000>; | |
87 | #clock-cells = <1>; | |
88 | }; | |
89 | ||
bba23d95 PV |
90 | clock_audss: audss-clock-controller@3810000 { |
91 | compatible = "samsung,exynos5250-audss-clock"; | |
92 | reg = <0x03810000 0x0C>; | |
93 | #clock-cells = <1>; | |
fe273c3e AH |
94 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, |
95 | <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; | |
c08ceea3 | 96 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
bba23d95 PV |
97 | }; |
98 | ||
2b7da988 AG |
99 | timer { |
100 | compatible = "arm,armv7-timer"; | |
101 | interrupts = <1 13 0xf08>, | |
102 | <1 14 0xf08>, | |
103 | <1 11 0xf08>, | |
104 | <1 10 0xf08>; | |
4d594dd3 YK |
105 | /* Unfortunately we need this since some versions of U-Boot |
106 | * on Exynos don't set the CNTFRQ register, so we need the | |
107 | * value from DT. | |
108 | */ | |
109 | clock-frequency = <24000000>; | |
b074abb7 KK |
110 | }; |
111 | ||
bbd9700a TA |
112 | mct@101C0000 { |
113 | compatible = "samsung,exynos4210-mct"; | |
114 | reg = <0x101C0000 0x800>; | |
115 | interrupt-controller; | |
116 | #interrups-cells = <2>; | |
117 | interrupt-parent = <&mct_map>; | |
118 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | |
119 | <4 0>, <5 0>; | |
fe273c3e | 120 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
2de6847c | 121 | clock-names = "fin_pll", "mct"; |
bbd9700a TA |
122 | |
123 | mct_map: mct-map { | |
124 | #interrupt-cells = <2>; | |
125 | #address-cells = <0>; | |
126 | #size-cells = <0>; | |
127 | interrupt-map = <0x0 0 &combiner 23 3>, | |
128 | <0x1 0 &combiner 23 4>, | |
129 | <0x2 0 &combiner 25 2>, | |
130 | <0x3 0 &combiner 25 3>, | |
131 | <0x4 0 &gic 0 120 0>, | |
132 | <0x5 0 &gic 0 121 0>; | |
133 | }; | |
134 | }; | |
135 | ||
4f801e59 CP |
136 | pmu { |
137 | compatible = "arm,cortex-a15-pmu"; | |
138 | interrupt-parent = <&combiner>; | |
139 | interrupts = <1 2>, <22 4>; | |
140 | }; | |
141 | ||
f8bfe2b0 TA |
142 | pinctrl_0: pinctrl@11400000 { |
143 | compatible = "samsung,exynos5250-pinctrl"; | |
144 | reg = <0x11400000 0x1000>; | |
145 | interrupts = <0 46 0>; | |
146 | ||
147 | wakup_eint: wakeup-interrupt-controller { | |
148 | compatible = "samsung,exynos4210-wakeup-eint"; | |
149 | interrupt-parent = <&gic>; | |
150 | interrupts = <0 32 0>; | |
151 | }; | |
152 | }; | |
153 | ||
154 | pinctrl_1: pinctrl@13400000 { | |
155 | compatible = "samsung,exynos5250-pinctrl"; | |
156 | reg = <0x13400000 0x1000>; | |
157 | interrupts = <0 45 0>; | |
158 | }; | |
159 | ||
160 | pinctrl_2: pinctrl@10d10000 { | |
161 | compatible = "samsung,exynos5250-pinctrl"; | |
162 | reg = <0x10d10000 0x1000>; | |
163 | interrupts = <0 50 0>; | |
164 | }; | |
165 | ||
0abb6aea | 166 | pinctrl_3: pinctrl@03860000 { |
f8bfe2b0 | 167 | compatible = "samsung,exynos5250-pinctrl"; |
0abb6aea | 168 | reg = <0x03860000 0x1000>; |
f8bfe2b0 TA |
169 | interrupts = <0 47 0>; |
170 | }; | |
171 | ||
c680036a LKA |
172 | pmu_system_controller: system-controller@10040000 { |
173 | compatible = "samsung,exynos5250-pmu", "syscon"; | |
174 | reg = <0x10040000 0x5000>; | |
175 | }; | |
176 | ||
1d287620 LKA |
177 | watchdog@101D0000 { |
178 | compatible = "samsung,exynos5250-wdt"; | |
179 | reg = <0x101D0000 0x100>; | |
180 | interrupts = <0 42 0>; | |
fe273c3e | 181 | clocks = <&clock CLK_WDT>; |
2de6847c | 182 | clock-names = "watchdog"; |
1d287620 | 183 | samsung,syscon-phandle = <&pmu_system_controller>; |
b074abb7 KK |
184 | }; |
185 | ||
21aa5217 SK |
186 | g2d@10850000 { |
187 | compatible = "samsung,exynos5250-g2d"; | |
188 | reg = <0x10850000 0x1000>; | |
189 | interrupts = <0 91 0>; | |
fe273c3e | 190 | clocks = <&clock CLK_G2D>; |
21aa5217 SK |
191 | clock-names = "fimg2d"; |
192 | }; | |
193 | ||
2eae613b AK |
194 | codec@11000000 { |
195 | compatible = "samsung,mfc-v6"; | |
196 | reg = <0x11000000 0x10000>; | |
197 | interrupts = <0 96 0>; | |
6f9e95e6 | 198 | samsung,power-domain = <&pd_mfc>; |
fe273c3e | 199 | clocks = <&clock CLK_MFC>; |
8b6bea33 | 200 | clock-names = "mfc"; |
2eae613b AK |
201 | }; |
202 | ||
24b44d24 | 203 | rtc@101E0000 { |
fe273c3e | 204 | clocks = <&clock CLK_RTC>; |
2de6847c | 205 | clock-names = "rtc"; |
65cedf0e | 206 | status = "disabled"; |
b074abb7 KK |
207 | }; |
208 | ||
ef405e04 ADK |
209 | tmu@10060000 { |
210 | compatible = "samsung,exynos5250-tmu"; | |
211 | reg = <0x10060000 0x100>; | |
212 | interrupts = <0 65 0>; | |
fe273c3e | 213 | clocks = <&clock CLK_TMU>; |
2de6847c | 214 | clock-names = "tmu_apbif"; |
ef405e04 ADK |
215 | }; |
216 | ||
b074abb7 | 217 | serial@12C00000 { |
fe273c3e | 218 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
2de6847c | 219 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
220 | }; |
221 | ||
222 | serial@12C10000 { | |
fe273c3e | 223 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
2de6847c | 224 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
225 | }; |
226 | ||
227 | serial@12C20000 { | |
fe273c3e | 228 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
2de6847c | 229 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
230 | }; |
231 | ||
232 | serial@12C30000 { | |
fe273c3e | 233 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
2de6847c | 234 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
235 | }; |
236 | ||
c47d244a VA |
237 | sata@122F0000 { |
238 | compatible = "samsung,exynos5-sata-ahci"; | |
239 | reg = <0x122F0000 0x1ff>; | |
240 | interrupts = <0 115 0>; | |
fe273c3e | 241 | clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; |
2de6847c | 242 | clock-names = "sata", "sclk_sata"; |
c47d244a VA |
243 | }; |
244 | ||
245 | sata-phy@12170000 { | |
246 | compatible = "samsung,exynos5-sata-phy"; | |
247 | reg = <0x12170000 0x1ff>; | |
248 | }; | |
249 | ||
b9fa3e7b | 250 | i2c_0: i2c@12C60000 { |
b074abb7 KK |
251 | compatible = "samsung,s3c2440-i2c"; |
252 | reg = <0x12C60000 0x100>; | |
253 | interrupts = <0 56 0>; | |
009f7c9f TA |
254 | #address-cells = <1>; |
255 | #size-cells = <0>; | |
fe273c3e | 256 | clocks = <&clock CLK_I2C0>; |
2de6847c | 257 | clock-names = "i2c"; |
f8bfe2b0 TA |
258 | pinctrl-names = "default"; |
259 | pinctrl-0 = <&i2c0_bus>; | |
6ad8ebff | 260 | status = "disabled"; |
b074abb7 KK |
261 | }; |
262 | ||
b9fa3e7b | 263 | i2c_1: i2c@12C70000 { |
b074abb7 KK |
264 | compatible = "samsung,s3c2440-i2c"; |
265 | reg = <0x12C70000 0x100>; | |
266 | interrupts = <0 57 0>; | |
009f7c9f TA |
267 | #address-cells = <1>; |
268 | #size-cells = <0>; | |
fe273c3e | 269 | clocks = <&clock CLK_I2C1>; |
2de6847c | 270 | clock-names = "i2c"; |
f8bfe2b0 TA |
271 | pinctrl-names = "default"; |
272 | pinctrl-0 = <&i2c1_bus>; | |
6ad8ebff | 273 | status = "disabled"; |
b074abb7 KK |
274 | }; |
275 | ||
b9fa3e7b | 276 | i2c_2: i2c@12C80000 { |
b074abb7 KK |
277 | compatible = "samsung,s3c2440-i2c"; |
278 | reg = <0x12C80000 0x100>; | |
279 | interrupts = <0 58 0>; | |
009f7c9f TA |
280 | #address-cells = <1>; |
281 | #size-cells = <0>; | |
fe273c3e | 282 | clocks = <&clock CLK_I2C2>; |
2de6847c | 283 | clock-names = "i2c"; |
f8bfe2b0 TA |
284 | pinctrl-names = "default"; |
285 | pinctrl-0 = <&i2c2_bus>; | |
6ad8ebff | 286 | status = "disabled"; |
b074abb7 KK |
287 | }; |
288 | ||
b9fa3e7b | 289 | i2c_3: i2c@12C90000 { |
b074abb7 KK |
290 | compatible = "samsung,s3c2440-i2c"; |
291 | reg = <0x12C90000 0x100>; | |
292 | interrupts = <0 59 0>; | |
009f7c9f TA |
293 | #address-cells = <1>; |
294 | #size-cells = <0>; | |
fe273c3e | 295 | clocks = <&clock CLK_I2C3>; |
2de6847c | 296 | clock-names = "i2c"; |
f8bfe2b0 TA |
297 | pinctrl-names = "default"; |
298 | pinctrl-0 = <&i2c3_bus>; | |
6ad8ebff | 299 | status = "disabled"; |
b074abb7 KK |
300 | }; |
301 | ||
b9fa3e7b | 302 | i2c_4: i2c@12CA0000 { |
b074abb7 KK |
303 | compatible = "samsung,s3c2440-i2c"; |
304 | reg = <0x12CA0000 0x100>; | |
305 | interrupts = <0 60 0>; | |
009f7c9f TA |
306 | #address-cells = <1>; |
307 | #size-cells = <0>; | |
fe273c3e | 308 | clocks = <&clock CLK_I2C4>; |
2de6847c | 309 | clock-names = "i2c"; |
f8bfe2b0 TA |
310 | pinctrl-names = "default"; |
311 | pinctrl-0 = <&i2c4_bus>; | |
6ad8ebff | 312 | status = "disabled"; |
b074abb7 KK |
313 | }; |
314 | ||
b9fa3e7b | 315 | i2c_5: i2c@12CB0000 { |
b074abb7 KK |
316 | compatible = "samsung,s3c2440-i2c"; |
317 | reg = <0x12CB0000 0x100>; | |
318 | interrupts = <0 61 0>; | |
009f7c9f TA |
319 | #address-cells = <1>; |
320 | #size-cells = <0>; | |
fe273c3e | 321 | clocks = <&clock CLK_I2C5>; |
2de6847c | 322 | clock-names = "i2c"; |
f8bfe2b0 TA |
323 | pinctrl-names = "default"; |
324 | pinctrl-0 = <&i2c5_bus>; | |
6ad8ebff | 325 | status = "disabled"; |
b074abb7 KK |
326 | }; |
327 | ||
b9fa3e7b | 328 | i2c_6: i2c@12CC0000 { |
b074abb7 KK |
329 | compatible = "samsung,s3c2440-i2c"; |
330 | reg = <0x12CC0000 0x100>; | |
331 | interrupts = <0 62 0>; | |
009f7c9f TA |
332 | #address-cells = <1>; |
333 | #size-cells = <0>; | |
fe273c3e | 334 | clocks = <&clock CLK_I2C6>; |
2de6847c | 335 | clock-names = "i2c"; |
f8bfe2b0 TA |
336 | pinctrl-names = "default"; |
337 | pinctrl-0 = <&i2c6_bus>; | |
6ad8ebff | 338 | status = "disabled"; |
b074abb7 KK |
339 | }; |
340 | ||
b9fa3e7b | 341 | i2c_7: i2c@12CD0000 { |
b074abb7 KK |
342 | compatible = "samsung,s3c2440-i2c"; |
343 | reg = <0x12CD0000 0x100>; | |
344 | interrupts = <0 63 0>; | |
009f7c9f TA |
345 | #address-cells = <1>; |
346 | #size-cells = <0>; | |
fe273c3e | 347 | clocks = <&clock CLK_I2C7>; |
2de6847c | 348 | clock-names = "i2c"; |
f8bfe2b0 TA |
349 | pinctrl-names = "default"; |
350 | pinctrl-0 = <&i2c7_bus>; | |
6ad8ebff | 351 | status = "disabled"; |
3e3e9ce4 RS |
352 | }; |
353 | ||
b9fa3e7b | 354 | i2c_8: i2c@12CE0000 { |
3e3e9ce4 RS |
355 | compatible = "samsung,s3c2440-hdmiphy-i2c"; |
356 | reg = <0x12CE0000 0x1000>; | |
357 | interrupts = <0 64 0>; | |
358 | #address-cells = <1>; | |
359 | #size-cells = <0>; | |
fe273c3e | 360 | clocks = <&clock CLK_I2C_HDMI>; |
2de6847c | 361 | clock-names = "i2c"; |
6ad8ebff | 362 | status = "disabled"; |
24025f6f OJ |
363 | }; |
364 | ||
c47d244a VA |
365 | i2c@121D0000 { |
366 | compatible = "samsung,exynos5-sata-phy-i2c"; | |
367 | reg = <0x121D0000 0x100>; | |
368 | #address-cells = <1>; | |
369 | #size-cells = <0>; | |
fe273c3e | 370 | clocks = <&clock CLK_SATA_PHYI2C>; |
2de6847c | 371 | clock-names = "i2c"; |
6ad8ebff | 372 | status = "disabled"; |
b074abb7 KK |
373 | }; |
374 | ||
79989ba3 TA |
375 | spi_0: spi@12d20000 { |
376 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 377 | status = "disabled"; |
79989ba3 TA |
378 | reg = <0x12d20000 0x100>; |
379 | interrupts = <0 66 0>; | |
a4a8a9d3 PV |
380 | dmas = <&pdma0 5 |
381 | &pdma0 4>; | |
382 | dma-names = "tx", "rx"; | |
79989ba3 TA |
383 | #address-cells = <1>; |
384 | #size-cells = <0>; | |
fe273c3e | 385 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
2de6847c | 386 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
387 | pinctrl-names = "default"; |
388 | pinctrl-0 = <&spi0_bus>; | |
79989ba3 TA |
389 | }; |
390 | ||
391 | spi_1: spi@12d30000 { | |
392 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 393 | status = "disabled"; |
79989ba3 TA |
394 | reg = <0x12d30000 0x100>; |
395 | interrupts = <0 67 0>; | |
a4a8a9d3 PV |
396 | dmas = <&pdma1 5 |
397 | &pdma1 4>; | |
398 | dma-names = "tx", "rx"; | |
79989ba3 TA |
399 | #address-cells = <1>; |
400 | #size-cells = <0>; | |
fe273c3e | 401 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
2de6847c | 402 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
403 | pinctrl-names = "default"; |
404 | pinctrl-0 = <&spi1_bus>; | |
79989ba3 TA |
405 | }; |
406 | ||
407 | spi_2: spi@12d40000 { | |
408 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 409 | status = "disabled"; |
79989ba3 TA |
410 | reg = <0x12d40000 0x100>; |
411 | interrupts = <0 68 0>; | |
a4a8a9d3 PV |
412 | dmas = <&pdma0 7 |
413 | &pdma0 6>; | |
414 | dma-names = "tx", "rx"; | |
79989ba3 TA |
415 | #address-cells = <1>; |
416 | #size-cells = <0>; | |
fe273c3e | 417 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
2de6847c | 418 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
419 | pinctrl-names = "default"; |
420 | pinctrl-0 = <&spi2_bus>; | |
79989ba3 TA |
421 | }; |
422 | ||
c8149df0 | 423 | mmc_0: mmc@12200000 { |
906fd84e YK |
424 | compatible = "samsung,exynos5250-dw-mshc"; |
425 | interrupts = <0 75 0>; | |
426 | #address-cells = <1>; | |
427 | #size-cells = <0>; | |
84bd48a0 | 428 | reg = <0x12200000 0x1000>; |
fe273c3e | 429 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; |
2de6847c | 430 | clock-names = "biu", "ciu"; |
46285a90 | 431 | fifo-depth = <0x80>; |
e908d5c5 | 432 | status = "disabled"; |
84bd48a0 TA |
433 | }; |
434 | ||
c8149df0 | 435 | mmc_1: mmc@12210000 { |
906fd84e YK |
436 | compatible = "samsung,exynos5250-dw-mshc"; |
437 | interrupts = <0 76 0>; | |
438 | #address-cells = <1>; | |
439 | #size-cells = <0>; | |
84bd48a0 | 440 | reg = <0x12210000 0x1000>; |
fe273c3e | 441 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; |
2de6847c | 442 | clock-names = "biu", "ciu"; |
46285a90 | 443 | fifo-depth = <0x80>; |
e908d5c5 | 444 | status = "disabled"; |
84bd48a0 TA |
445 | }; |
446 | ||
c8149df0 | 447 | mmc_2: mmc@12220000 { |
906fd84e YK |
448 | compatible = "samsung,exynos5250-dw-mshc"; |
449 | interrupts = <0 77 0>; | |
450 | #address-cells = <1>; | |
451 | #size-cells = <0>; | |
84bd48a0 | 452 | reg = <0x12220000 0x1000>; |
fe273c3e | 453 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; |
2de6847c | 454 | clock-names = "biu", "ciu"; |
46285a90 | 455 | fifo-depth = <0x80>; |
e908d5c5 | 456 | status = "disabled"; |
84bd48a0 TA |
457 | }; |
458 | ||
c8149df0 | 459 | mmc_3: mmc@12230000 { |
84bd48a0 TA |
460 | compatible = "samsung,exynos5250-dw-mshc"; |
461 | reg = <0x12230000 0x1000>; | |
462 | interrupts = <0 78 0>; | |
463 | #address-cells = <1>; | |
464 | #size-cells = <0>; | |
fe273c3e | 465 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; |
2de6847c | 466 | clock-names = "biu", "ciu"; |
46285a90 | 467 | fifo-depth = <0x80>; |
e908d5c5 | 468 | status = "disabled"; |
84bd48a0 TA |
469 | }; |
470 | ||
28a48058 | 471 | i2s0: i2s@03830000 { |
64183656 | 472 | compatible = "samsung,s5pv210-i2s"; |
328aee4b | 473 | status = "disabled"; |
a0b5f81e | 474 | reg = <0x03830000 0x100>; |
4c4c7463 PV |
475 | dmas = <&pdma0 10 |
476 | &pdma0 9 | |
477 | &pdma0 8>; | |
478 | dma-names = "tx", "rx", "tx-sec"; | |
916ec47e PV |
479 | clocks = <&clock_audss EXYNOS_I2S_BUS>, |
480 | <&clock_audss EXYNOS_I2S_BUS>, | |
481 | <&clock_audss EXYNOS_SCLK_I2S>; | |
482 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
a0b5f81e | 483 | samsung,idma-addr = <0x03000000>; |
f8bfe2b0 TA |
484 | pinctrl-names = "default"; |
485 | pinctrl-0 = <&i2s0_bus>; | |
4c4c7463 PV |
486 | }; |
487 | ||
28a48058 | 488 | i2s1: i2s@12D60000 { |
64183656 | 489 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 490 | status = "disabled"; |
a0b5f81e MB |
491 | reg = <0x12D60000 0x100>; |
492 | dmas = <&pdma1 12 | |
493 | &pdma1 11>; | |
494 | dma-names = "tx", "rx"; | |
fe273c3e | 495 | clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; |
916ec47e | 496 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
497 | pinctrl-names = "default"; |
498 | pinctrl-0 = <&i2s1_bus>; | |
4c4c7463 PV |
499 | }; |
500 | ||
28a48058 | 501 | i2s2: i2s@12D70000 { |
64183656 | 502 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 503 | status = "disabled"; |
a0b5f81e MB |
504 | reg = <0x12D70000 0x100>; |
505 | dmas = <&pdma0 12 | |
506 | &pdma0 11>; | |
507 | dma-names = "tx", "rx"; | |
fe273c3e | 508 | clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; |
916ec47e | 509 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
510 | pinctrl-names = "default"; |
511 | pinctrl-0 = <&i2s2_bus>; | |
4c4c7463 PV |
512 | }; |
513 | ||
0b3dc97e VG |
514 | usb@12000000 { |
515 | compatible = "samsung,exynos5250-dwusb3"; | |
fe273c3e | 516 | clocks = <&clock CLK_USB3>; |
0b3dc97e VG |
517 | clock-names = "usbdrd30"; |
518 | #address-cells = <1>; | |
519 | #size-cells = <1>; | |
520 | ranges; | |
521 | ||
522 | dwc3 { | |
523 | compatible = "synopsys,dwc3"; | |
524 | reg = <0x12000000 0x10000>; | |
525 | interrupts = <0 72 0>; | |
526 | usb-phy = <&usb2_phy &usb3_phy>; | |
527 | }; | |
528 | }; | |
529 | ||
530 | usb3_phy: usbphy@12100000 { | |
896db3b3 VG |
531 | compatible = "samsung,exynos5250-usb3phy"; |
532 | reg = <0x12100000 0x100>; | |
fe273c3e | 533 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>; |
896db3b3 VG |
534 | clock-names = "ext_xtal", "usbdrd30"; |
535 | #address-cells = <1>; | |
536 | #size-cells = <1>; | |
537 | ranges; | |
538 | ||
539 | usbphy-sys { | |
540 | reg = <0x10040704 0x8>; | |
541 | }; | |
542 | }; | |
543 | ||
13cbd1e3 VG |
544 | usb@12110000 { |
545 | compatible = "samsung,exynos4210-ehci"; | |
546 | reg = <0x12110000 0x100>; | |
547 | interrupts = <0 71 0>; | |
b3cd7d87 | 548 | |
fe273c3e | 549 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 550 | clock-names = "usbhost"; |
13cbd1e3 VG |
551 | }; |
552 | ||
7d40d867 VG |
553 | usb@12120000 { |
554 | compatible = "samsung,exynos4210-ohci"; | |
555 | reg = <0x12120000 0x100>; | |
556 | interrupts = <0 71 0>; | |
b3cd7d87 | 557 | |
fe273c3e | 558 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 559 | clock-names = "usbhost"; |
7d40d867 VG |
560 | }; |
561 | ||
0b3dc97e | 562 | usb2_phy: usbphy@12130000 { |
7ec892ef VG |
563 | compatible = "samsung,exynos5250-usb2phy"; |
564 | reg = <0x12130000 0x100>; | |
fe273c3e | 565 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>; |
7ec892ef VG |
566 | clock-names = "ext_xtal", "usbhost"; |
567 | #address-cells = <1>; | |
568 | #size-cells = <1>; | |
569 | ranges; | |
570 | ||
571 | usbphy-sys { | |
572 | reg = <0x10040704 0x8>, | |
573 | <0x10050230 0x4>; | |
574 | }; | |
575 | }; | |
576 | ||
022cf308 LKA |
577 | pwm: pwm@12dd0000 { |
578 | compatible = "samsung,exynos4210-pwm"; | |
579 | reg = <0x12dd0000 0x100>; | |
580 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
581 | #pwm-cells = <3>; | |
fe273c3e | 582 | clocks = <&clock CLK_PWM>; |
022cf308 LKA |
583 | clock-names = "timers"; |
584 | }; | |
585 | ||
b074abb7 KK |
586 | amba { |
587 | #address-cells = <1>; | |
588 | #size-cells = <1>; | |
589 | compatible = "arm,amba-bus"; | |
590 | interrupt-parent = <&gic>; | |
591 | ranges; | |
592 | ||
593 | pdma0: pdma@121A0000 { | |
594 | compatible = "arm,pl330", "arm,primecell"; | |
595 | reg = <0x121A0000 0x1000>; | |
596 | interrupts = <0 34 0>; | |
fe273c3e | 597 | clocks = <&clock CLK_PDMA0>; |
2de6847c | 598 | clock-names = "apb_pclk"; |
42cf2098 PV |
599 | #dma-cells = <1>; |
600 | #dma-channels = <8>; | |
601 | #dma-requests = <32>; | |
b074abb7 KK |
602 | }; |
603 | ||
604 | pdma1: pdma@121B0000 { | |
605 | compatible = "arm,pl330", "arm,primecell"; | |
606 | reg = <0x121B0000 0x1000>; | |
607 | interrupts = <0 35 0>; | |
fe273c3e | 608 | clocks = <&clock CLK_PDMA1>; |
2de6847c | 609 | clock-names = "apb_pclk"; |
42cf2098 PV |
610 | #dma-cells = <1>; |
611 | #dma-channels = <8>; | |
612 | #dma-requests = <32>; | |
b074abb7 KK |
613 | }; |
614 | ||
009f7c9f | 615 | mdma0: mdma@10800000 { |
b074abb7 KK |
616 | compatible = "arm,pl330", "arm,primecell"; |
617 | reg = <0x10800000 0x1000>; | |
618 | interrupts = <0 33 0>; | |
fe273c3e | 619 | clocks = <&clock CLK_MDMA0>; |
2de6847c | 620 | clock-names = "apb_pclk"; |
42cf2098 PV |
621 | #dma-cells = <1>; |
622 | #dma-channels = <8>; | |
623 | #dma-requests = <1>; | |
b074abb7 KK |
624 | }; |
625 | ||
009f7c9f | 626 | mdma1: mdma@11C10000 { |
b074abb7 KK |
627 | compatible = "arm,pl330", "arm,primecell"; |
628 | reg = <0x11C10000 0x1000>; | |
629 | interrupts = <0 124 0>; | |
fe273c3e | 630 | clocks = <&clock CLK_MDMA1>; |
2de6847c | 631 | clock-names = "apb_pclk"; |
42cf2098 PV |
632 | #dma-cells = <1>; |
633 | #dma-channels = <8>; | |
634 | #dma-requests = <1>; | |
b074abb7 KK |
635 | }; |
636 | }; | |
637 | ||
c31f566d | 638 | gsc_0: gsc@13e00000 { |
1128658a SAB |
639 | compatible = "samsung,exynos5-gsc"; |
640 | reg = <0x13e00000 0x1000>; | |
641 | interrupts = <0 85 0>; | |
6f9e95e6 | 642 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 643 | clocks = <&clock CLK_GSCL0>; |
2de6847c | 644 | clock-names = "gscl"; |
1128658a SAB |
645 | }; |
646 | ||
c31f566d | 647 | gsc_1: gsc@13e10000 { |
1128658a SAB |
648 | compatible = "samsung,exynos5-gsc"; |
649 | reg = <0x13e10000 0x1000>; | |
650 | interrupts = <0 86 0>; | |
6f9e95e6 | 651 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 652 | clocks = <&clock CLK_GSCL1>; |
2de6847c | 653 | clock-names = "gscl"; |
1128658a SAB |
654 | }; |
655 | ||
c31f566d | 656 | gsc_2: gsc@13e20000 { |
1128658a SAB |
657 | compatible = "samsung,exynos5-gsc"; |
658 | reg = <0x13e20000 0x1000>; | |
659 | interrupts = <0 87 0>; | |
6f9e95e6 | 660 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 661 | clocks = <&clock CLK_GSCL2>; |
2de6847c | 662 | clock-names = "gscl"; |
1128658a SAB |
663 | }; |
664 | ||
c31f566d | 665 | gsc_3: gsc@13e30000 { |
1128658a SAB |
666 | compatible = "samsung,exynos5-gsc"; |
667 | reg = <0x13e30000 0x1000>; | |
668 | interrupts = <0 88 0>; | |
6f9e95e6 | 669 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 670 | clocks = <&clock CLK_GSCL3>; |
2de6847c | 671 | clock-names = "gscl"; |
1128658a | 672 | }; |
566cf8ee RS |
673 | |
674 | hdmi { | |
0d1fc829 | 675 | compatible = "samsung,exynos4212-hdmi"; |
101250ce | 676 | reg = <0x14530000 0x70000>; |
566cf8ee | 677 | interrupts = <0 95 0>; |
fe273c3e AH |
678 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
679 | <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
680 | <&clock CLK_MOUT_HDMI>; | |
2de6847c | 681 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
27c16d19 | 682 | "sclk_hdmiphy", "mout_hdmi"; |
566cf8ee | 683 | }; |
5af0d8a3 RS |
684 | |
685 | mixer { | |
0d1fc829 | 686 | compatible = "samsung,exynos5250-mixer"; |
5af0d8a3 RS |
687 | reg = <0x14450000 0x10000>; |
688 | interrupts = <0 94 0>; | |
fe273c3e | 689 | clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; |
18fe6ef0 | 690 | clock-names = "mixer", "sclk_hdmi"; |
5af0d8a3 | 691 | }; |
ad4aebe1 | 692 | |
77899d53 VS |
693 | dp_phy: video-phy@10040720 { |
694 | compatible = "samsung,exynos5250-dp-video-phy"; | |
695 | reg = <0x10040720 4>; | |
696 | #phy-cells = <0>; | |
697 | }; | |
698 | ||
699 | dp-controller@145B0000 { | |
fe273c3e | 700 | clocks = <&clock CLK_DP>; |
0f72a9ec | 701 | clock-names = "dp"; |
77899d53 VS |
702 | phys = <&dp_phy>; |
703 | phy-names = "dp"; | |
ad4aebe1 | 704 | }; |
a7389cb1 | 705 | |
9ee35a5b | 706 | fimd@14400000 { |
fe273c3e | 707 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
a7389cb1 LKA |
708 | clock-names = "sclk_fimd", "fimd"; |
709 | }; | |
f408f9db NKC |
710 | |
711 | adc: adc@12D10000 { | |
712 | compatible = "samsung,exynos-adc-v1"; | |
713 | reg = <0x12D10000 0x100>, <0x10040718 0x4>; | |
714 | interrupts = <0 106 0>; | |
fe273c3e | 715 | clocks = <&clock CLK_ADC>; |
f408f9db NKC |
716 | clock-names = "adc"; |
717 | #io-channel-cells = <1>; | |
718 | io-channel-ranges; | |
719 | status = "disabled"; | |
720 | }; | |
183af252 NKC |
721 | |
722 | sss@10830000 { | |
723 | compatible = "samsung,exynos4210-secss"; | |
724 | reg = <0x10830000 0x10000>; | |
725 | interrupts = <0 112 0>; | |
726 | clocks = <&clock 348>; | |
727 | clock-names = "secss"; | |
728 | }; | |
b074abb7 | 729 | }; |