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b074abb7 KK |
1 | /* |
2 | * SAMSUNG EXYNOS5250 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. | |
8 | * EXYNOS5250 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, | |
13 | * additional nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
fe273c3e | 20 | #include <dt-bindings/clock/exynos5250.h> |
e6c21cba | 21 | #include "exynos5.dtsi" |
3799279f | 22 | #include "exynos5250-pinctrl.dtsi" |
b074abb7 | 23 | |
602408e3 | 24 | #include <dt-bindings/clock/exynos-audss-clk.h> |
b074abb7 KK |
25 | |
26 | / { | |
8bdb31b4 | 27 | compatible = "samsung,exynos5250", "samsung,exynos5"; |
b074abb7 | 28 | |
79989ba3 TA |
29 | aliases { |
30 | spi0 = &spi_0; | |
31 | spi1 = &spi_1; | |
32 | spi2 = &spi_2; | |
1128658a SAB |
33 | gsc0 = &gsc_0; |
34 | gsc1 = &gsc_1; | |
35 | gsc2 = &gsc_2; | |
36 | gsc3 = &gsc_3; | |
c8149df0 YK |
37 | mshc0 = &mmc_0; |
38 | mshc1 = &mmc_1; | |
39 | mshc2 = &mmc_2; | |
40 | mshc3 = &mmc_3; | |
b9fa3e7b AK |
41 | i2c0 = &i2c_0; |
42 | i2c1 = &i2c_1; | |
43 | i2c2 = &i2c_2; | |
44 | i2c3 = &i2c_3; | |
45 | i2c4 = &i2c_4; | |
46 | i2c5 = &i2c_5; | |
47 | i2c6 = &i2c_6; | |
48 | i2c7 = &i2c_7; | |
49 | i2c8 = &i2c_8; | |
ba0d7ed3 | 50 | i2c9 = &i2c_9; |
f8bfe2b0 TA |
51 | pinctrl0 = &pinctrl_0; |
52 | pinctrl1 = &pinctrl_1; | |
53 | pinctrl2 = &pinctrl_2; | |
54 | pinctrl3 = &pinctrl_3; | |
79989ba3 TA |
55 | }; |
56 | ||
1897d2f3 CK |
57 | cpus { |
58 | #address-cells = <1>; | |
59 | #size-cells = <0>; | |
60 | ||
61 | cpu@0 { | |
62 | device_type = "cpu"; | |
63 | compatible = "arm,cortex-a15"; | |
64 | reg = <0>; | |
0da80563 | 65 | clock-frequency = <1700000000>; |
1897d2f3 CK |
66 | }; |
67 | cpu@1 { | |
68 | device_type = "cpu"; | |
69 | compatible = "arm,cortex-a15"; | |
70 | reg = <1>; | |
0da80563 | 71 | clock-frequency = <1700000000>; |
1897d2f3 | 72 | }; |
79989ba3 TA |
73 | }; |
74 | ||
b3205dea SK |
75 | sysram@02020000 { |
76 | compatible = "mmio-sram"; | |
77 | reg = <0x02020000 0x30000>; | |
78 | #address-cells = <1>; | |
79 | #size-cells = <1>; | |
80 | ranges = <0 0x02020000 0x30000>; | |
81 | ||
82 | smp-sysram@0 { | |
83 | compatible = "samsung,exynos4210-sysram"; | |
84 | reg = <0x0 0x1000>; | |
85 | }; | |
86 | ||
87 | smp-sysram@2f000 { | |
88 | compatible = "samsung,exynos4210-sysram-ns"; | |
89 | reg = <0x2f000 0x1000>; | |
90 | }; | |
91 | }; | |
92 | ||
c31f566d | 93 | pd_gsc: gsc-power-domain@10044000 { |
6f9e95e6 PK |
94 | compatible = "samsung,exynos4210-pd"; |
95 | reg = <0x10044000 0x20>; | |
96 | }; | |
97 | ||
c31f566d | 98 | pd_mfc: mfc-power-domain@10044040 { |
6f9e95e6 PK |
99 | compatible = "samsung,exynos4210-pd"; |
100 | reg = <0x10044040 0x20>; | |
101 | }; | |
102 | ||
c31f566d | 103 | clock: clock-controller@10010000 { |
d8bafc87 TA |
104 | compatible = "samsung,exynos5250-clock"; |
105 | reg = <0x10010000 0x30000>; | |
106 | #clock-cells = <1>; | |
107 | }; | |
108 | ||
bba23d95 PV |
109 | clock_audss: audss-clock-controller@3810000 { |
110 | compatible = "samsung,exynos5250-audss-clock"; | |
111 | reg = <0x03810000 0x0C>; | |
112 | #clock-cells = <1>; | |
fe273c3e AH |
113 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, |
114 | <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; | |
c08ceea3 | 115 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
bba23d95 PV |
116 | }; |
117 | ||
2b7da988 AG |
118 | timer { |
119 | compatible = "arm,armv7-timer"; | |
120 | interrupts = <1 13 0xf08>, | |
121 | <1 14 0xf08>, | |
122 | <1 11 0xf08>, | |
123 | <1 10 0xf08>; | |
4d594dd3 YK |
124 | /* Unfortunately we need this since some versions of U-Boot |
125 | * on Exynos don't set the CNTFRQ register, so we need the | |
126 | * value from DT. | |
127 | */ | |
128 | clock-frequency = <24000000>; | |
b074abb7 KK |
129 | }; |
130 | ||
bbd9700a TA |
131 | mct@101C0000 { |
132 | compatible = "samsung,exynos4210-mct"; | |
133 | reg = <0x101C0000 0x800>; | |
134 | interrupt-controller; | |
135 | #interrups-cells = <2>; | |
136 | interrupt-parent = <&mct_map>; | |
137 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | |
138 | <4 0>, <5 0>; | |
fe273c3e | 139 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
2de6847c | 140 | clock-names = "fin_pll", "mct"; |
bbd9700a TA |
141 | |
142 | mct_map: mct-map { | |
143 | #interrupt-cells = <2>; | |
144 | #address-cells = <0>; | |
145 | #size-cells = <0>; | |
146 | interrupt-map = <0x0 0 &combiner 23 3>, | |
147 | <0x1 0 &combiner 23 4>, | |
148 | <0x2 0 &combiner 25 2>, | |
149 | <0x3 0 &combiner 25 3>, | |
150 | <0x4 0 &gic 0 120 0>, | |
151 | <0x5 0 &gic 0 121 0>; | |
152 | }; | |
153 | }; | |
154 | ||
4f801e59 CP |
155 | pmu { |
156 | compatible = "arm,cortex-a15-pmu"; | |
157 | interrupt-parent = <&combiner>; | |
158 | interrupts = <1 2>, <22 4>; | |
159 | }; | |
160 | ||
f8bfe2b0 TA |
161 | pinctrl_0: pinctrl@11400000 { |
162 | compatible = "samsung,exynos5250-pinctrl"; | |
163 | reg = <0x11400000 0x1000>; | |
164 | interrupts = <0 46 0>; | |
165 | ||
166 | wakup_eint: wakeup-interrupt-controller { | |
167 | compatible = "samsung,exynos4210-wakeup-eint"; | |
168 | interrupt-parent = <&gic>; | |
169 | interrupts = <0 32 0>; | |
170 | }; | |
171 | }; | |
172 | ||
173 | pinctrl_1: pinctrl@13400000 { | |
174 | compatible = "samsung,exynos5250-pinctrl"; | |
175 | reg = <0x13400000 0x1000>; | |
176 | interrupts = <0 45 0>; | |
177 | }; | |
178 | ||
179 | pinctrl_2: pinctrl@10d10000 { | |
180 | compatible = "samsung,exynos5250-pinctrl"; | |
181 | reg = <0x10d10000 0x1000>; | |
182 | interrupts = <0 50 0>; | |
183 | }; | |
184 | ||
0abb6aea | 185 | pinctrl_3: pinctrl@03860000 { |
f8bfe2b0 | 186 | compatible = "samsung,exynos5250-pinctrl"; |
0abb6aea | 187 | reg = <0x03860000 0x1000>; |
f8bfe2b0 TA |
188 | interrupts = <0 47 0>; |
189 | }; | |
190 | ||
c680036a LKA |
191 | pmu_system_controller: system-controller@10040000 { |
192 | compatible = "samsung,exynos5250-pmu", "syscon"; | |
193 | reg = <0x10040000 0x5000>; | |
194 | }; | |
195 | ||
1d287620 LKA |
196 | watchdog@101D0000 { |
197 | compatible = "samsung,exynos5250-wdt"; | |
198 | reg = <0x101D0000 0x100>; | |
199 | interrupts = <0 42 0>; | |
fe273c3e | 200 | clocks = <&clock CLK_WDT>; |
2de6847c | 201 | clock-names = "watchdog"; |
1d287620 | 202 | samsung,syscon-phandle = <&pmu_system_controller>; |
b074abb7 KK |
203 | }; |
204 | ||
21aa5217 SK |
205 | g2d@10850000 { |
206 | compatible = "samsung,exynos5250-g2d"; | |
207 | reg = <0x10850000 0x1000>; | |
208 | interrupts = <0 91 0>; | |
fe273c3e | 209 | clocks = <&clock CLK_G2D>; |
21aa5217 SK |
210 | clock-names = "fimg2d"; |
211 | }; | |
212 | ||
2eae613b AK |
213 | codec@11000000 { |
214 | compatible = "samsung,mfc-v6"; | |
215 | reg = <0x11000000 0x10000>; | |
216 | interrupts = <0 96 0>; | |
6f9e95e6 | 217 | samsung,power-domain = <&pd_mfc>; |
fe273c3e | 218 | clocks = <&clock CLK_MFC>; |
8b6bea33 | 219 | clock-names = "mfc"; |
2eae613b AK |
220 | }; |
221 | ||
24b44d24 | 222 | rtc@101E0000 { |
fe273c3e | 223 | clocks = <&clock CLK_RTC>; |
2de6847c | 224 | clock-names = "rtc"; |
65cedf0e | 225 | status = "disabled"; |
b074abb7 KK |
226 | }; |
227 | ||
ef405e04 ADK |
228 | tmu@10060000 { |
229 | compatible = "samsung,exynos5250-tmu"; | |
230 | reg = <0x10060000 0x100>; | |
231 | interrupts = <0 65 0>; | |
fe273c3e | 232 | clocks = <&clock CLK_TMU>; |
2de6847c | 233 | clock-names = "tmu_apbif"; |
ef405e04 ADK |
234 | }; |
235 | ||
b074abb7 | 236 | serial@12C00000 { |
fe273c3e | 237 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
2de6847c | 238 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
239 | }; |
240 | ||
241 | serial@12C10000 { | |
fe273c3e | 242 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
2de6847c | 243 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
244 | }; |
245 | ||
246 | serial@12C20000 { | |
fe273c3e | 247 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
2de6847c | 248 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
249 | }; |
250 | ||
251 | serial@12C30000 { | |
fe273c3e | 252 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
2de6847c | 253 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
254 | }; |
255 | ||
c47d244a | 256 | sata@122F0000 { |
ba0d7ed3 YK |
257 | compatible = "snps,dwc-ahci"; |
258 | samsung,sata-freq = <66>; | |
c47d244a VA |
259 | reg = <0x122F0000 0x1ff>; |
260 | interrupts = <0 115 0>; | |
fe273c3e | 261 | clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; |
2de6847c | 262 | clock-names = "sata", "sclk_sata"; |
ba0d7ed3 YK |
263 | phys = <&sata_phy>; |
264 | phy-names = "sata-phy"; | |
265 | status = "disabled"; | |
c47d244a VA |
266 | }; |
267 | ||
ba0d7ed3 YK |
268 | sata_phy: sata-phy@12170000 { |
269 | compatible = "samsung,exynos5250-sata-phy"; | |
c47d244a | 270 | reg = <0x12170000 0x1ff>; |
ba0d7ed3 YK |
271 | clocks = <&clock 287>; |
272 | clock-names = "sata_phyctrl"; | |
273 | #phy-cells = <0>; | |
274 | samsung,syscon-phandle = <&pmu_system_controller>; | |
275 | status = "disabled"; | |
c47d244a VA |
276 | }; |
277 | ||
b9fa3e7b | 278 | i2c_0: i2c@12C60000 { |
b074abb7 KK |
279 | compatible = "samsung,s3c2440-i2c"; |
280 | reg = <0x12C60000 0x100>; | |
281 | interrupts = <0 56 0>; | |
009f7c9f TA |
282 | #address-cells = <1>; |
283 | #size-cells = <0>; | |
fe273c3e | 284 | clocks = <&clock CLK_I2C0>; |
2de6847c | 285 | clock-names = "i2c"; |
f8bfe2b0 TA |
286 | pinctrl-names = "default"; |
287 | pinctrl-0 = <&i2c0_bus>; | |
6ad8ebff | 288 | status = "disabled"; |
b074abb7 KK |
289 | }; |
290 | ||
b9fa3e7b | 291 | i2c_1: i2c@12C70000 { |
b074abb7 KK |
292 | compatible = "samsung,s3c2440-i2c"; |
293 | reg = <0x12C70000 0x100>; | |
294 | interrupts = <0 57 0>; | |
009f7c9f TA |
295 | #address-cells = <1>; |
296 | #size-cells = <0>; | |
fe273c3e | 297 | clocks = <&clock CLK_I2C1>; |
2de6847c | 298 | clock-names = "i2c"; |
f8bfe2b0 TA |
299 | pinctrl-names = "default"; |
300 | pinctrl-0 = <&i2c1_bus>; | |
6ad8ebff | 301 | status = "disabled"; |
b074abb7 KK |
302 | }; |
303 | ||
b9fa3e7b | 304 | i2c_2: i2c@12C80000 { |
b074abb7 KK |
305 | compatible = "samsung,s3c2440-i2c"; |
306 | reg = <0x12C80000 0x100>; | |
307 | interrupts = <0 58 0>; | |
009f7c9f TA |
308 | #address-cells = <1>; |
309 | #size-cells = <0>; | |
fe273c3e | 310 | clocks = <&clock CLK_I2C2>; |
2de6847c | 311 | clock-names = "i2c"; |
f8bfe2b0 TA |
312 | pinctrl-names = "default"; |
313 | pinctrl-0 = <&i2c2_bus>; | |
6ad8ebff | 314 | status = "disabled"; |
b074abb7 KK |
315 | }; |
316 | ||
b9fa3e7b | 317 | i2c_3: i2c@12C90000 { |
b074abb7 KK |
318 | compatible = "samsung,s3c2440-i2c"; |
319 | reg = <0x12C90000 0x100>; | |
320 | interrupts = <0 59 0>; | |
009f7c9f TA |
321 | #address-cells = <1>; |
322 | #size-cells = <0>; | |
fe273c3e | 323 | clocks = <&clock CLK_I2C3>; |
2de6847c | 324 | clock-names = "i2c"; |
f8bfe2b0 TA |
325 | pinctrl-names = "default"; |
326 | pinctrl-0 = <&i2c3_bus>; | |
6ad8ebff | 327 | status = "disabled"; |
b074abb7 KK |
328 | }; |
329 | ||
b9fa3e7b | 330 | i2c_4: i2c@12CA0000 { |
b074abb7 KK |
331 | compatible = "samsung,s3c2440-i2c"; |
332 | reg = <0x12CA0000 0x100>; | |
333 | interrupts = <0 60 0>; | |
009f7c9f TA |
334 | #address-cells = <1>; |
335 | #size-cells = <0>; | |
fe273c3e | 336 | clocks = <&clock CLK_I2C4>; |
2de6847c | 337 | clock-names = "i2c"; |
f8bfe2b0 TA |
338 | pinctrl-names = "default"; |
339 | pinctrl-0 = <&i2c4_bus>; | |
6ad8ebff | 340 | status = "disabled"; |
b074abb7 KK |
341 | }; |
342 | ||
b9fa3e7b | 343 | i2c_5: i2c@12CB0000 { |
b074abb7 KK |
344 | compatible = "samsung,s3c2440-i2c"; |
345 | reg = <0x12CB0000 0x100>; | |
346 | interrupts = <0 61 0>; | |
009f7c9f TA |
347 | #address-cells = <1>; |
348 | #size-cells = <0>; | |
fe273c3e | 349 | clocks = <&clock CLK_I2C5>; |
2de6847c | 350 | clock-names = "i2c"; |
f8bfe2b0 TA |
351 | pinctrl-names = "default"; |
352 | pinctrl-0 = <&i2c5_bus>; | |
6ad8ebff | 353 | status = "disabled"; |
b074abb7 KK |
354 | }; |
355 | ||
b9fa3e7b | 356 | i2c_6: i2c@12CC0000 { |
b074abb7 KK |
357 | compatible = "samsung,s3c2440-i2c"; |
358 | reg = <0x12CC0000 0x100>; | |
359 | interrupts = <0 62 0>; | |
009f7c9f TA |
360 | #address-cells = <1>; |
361 | #size-cells = <0>; | |
fe273c3e | 362 | clocks = <&clock CLK_I2C6>; |
2de6847c | 363 | clock-names = "i2c"; |
f8bfe2b0 TA |
364 | pinctrl-names = "default"; |
365 | pinctrl-0 = <&i2c6_bus>; | |
6ad8ebff | 366 | status = "disabled"; |
b074abb7 KK |
367 | }; |
368 | ||
b9fa3e7b | 369 | i2c_7: i2c@12CD0000 { |
b074abb7 KK |
370 | compatible = "samsung,s3c2440-i2c"; |
371 | reg = <0x12CD0000 0x100>; | |
372 | interrupts = <0 63 0>; | |
009f7c9f TA |
373 | #address-cells = <1>; |
374 | #size-cells = <0>; | |
fe273c3e | 375 | clocks = <&clock CLK_I2C7>; |
2de6847c | 376 | clock-names = "i2c"; |
f8bfe2b0 TA |
377 | pinctrl-names = "default"; |
378 | pinctrl-0 = <&i2c7_bus>; | |
6ad8ebff | 379 | status = "disabled"; |
3e3e9ce4 RS |
380 | }; |
381 | ||
b9fa3e7b | 382 | i2c_8: i2c@12CE0000 { |
3e3e9ce4 RS |
383 | compatible = "samsung,s3c2440-hdmiphy-i2c"; |
384 | reg = <0x12CE0000 0x1000>; | |
385 | interrupts = <0 64 0>; | |
386 | #address-cells = <1>; | |
387 | #size-cells = <0>; | |
fe273c3e | 388 | clocks = <&clock CLK_I2C_HDMI>; |
2de6847c | 389 | clock-names = "i2c"; |
6ad8ebff | 390 | status = "disabled"; |
24025f6f OJ |
391 | }; |
392 | ||
ba0d7ed3 | 393 | i2c_9: i2c@121D0000 { |
c47d244a VA |
394 | compatible = "samsung,exynos5-sata-phy-i2c"; |
395 | reg = <0x121D0000 0x100>; | |
396 | #address-cells = <1>; | |
397 | #size-cells = <0>; | |
fe273c3e | 398 | clocks = <&clock CLK_SATA_PHYI2C>; |
2de6847c | 399 | clock-names = "i2c"; |
6ad8ebff | 400 | status = "disabled"; |
b074abb7 KK |
401 | }; |
402 | ||
79989ba3 TA |
403 | spi_0: spi@12d20000 { |
404 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 405 | status = "disabled"; |
79989ba3 TA |
406 | reg = <0x12d20000 0x100>; |
407 | interrupts = <0 66 0>; | |
a4a8a9d3 PV |
408 | dmas = <&pdma0 5 |
409 | &pdma0 4>; | |
410 | dma-names = "tx", "rx"; | |
79989ba3 TA |
411 | #address-cells = <1>; |
412 | #size-cells = <0>; | |
fe273c3e | 413 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
2de6847c | 414 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
415 | pinctrl-names = "default"; |
416 | pinctrl-0 = <&spi0_bus>; | |
79989ba3 TA |
417 | }; |
418 | ||
419 | spi_1: spi@12d30000 { | |
420 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 421 | status = "disabled"; |
79989ba3 TA |
422 | reg = <0x12d30000 0x100>; |
423 | interrupts = <0 67 0>; | |
a4a8a9d3 PV |
424 | dmas = <&pdma1 5 |
425 | &pdma1 4>; | |
426 | dma-names = "tx", "rx"; | |
79989ba3 TA |
427 | #address-cells = <1>; |
428 | #size-cells = <0>; | |
fe273c3e | 429 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
2de6847c | 430 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
431 | pinctrl-names = "default"; |
432 | pinctrl-0 = <&spi1_bus>; | |
79989ba3 TA |
433 | }; |
434 | ||
435 | spi_2: spi@12d40000 { | |
436 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 437 | status = "disabled"; |
79989ba3 TA |
438 | reg = <0x12d40000 0x100>; |
439 | interrupts = <0 68 0>; | |
a4a8a9d3 PV |
440 | dmas = <&pdma0 7 |
441 | &pdma0 6>; | |
442 | dma-names = "tx", "rx"; | |
79989ba3 TA |
443 | #address-cells = <1>; |
444 | #size-cells = <0>; | |
fe273c3e | 445 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
2de6847c | 446 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
447 | pinctrl-names = "default"; |
448 | pinctrl-0 = <&spi2_bus>; | |
79989ba3 TA |
449 | }; |
450 | ||
c8149df0 | 451 | mmc_0: mmc@12200000 { |
906fd84e YK |
452 | compatible = "samsung,exynos5250-dw-mshc"; |
453 | interrupts = <0 75 0>; | |
454 | #address-cells = <1>; | |
455 | #size-cells = <0>; | |
84bd48a0 | 456 | reg = <0x12200000 0x1000>; |
fe273c3e | 457 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; |
2de6847c | 458 | clock-names = "biu", "ciu"; |
46285a90 | 459 | fifo-depth = <0x80>; |
e908d5c5 | 460 | status = "disabled"; |
84bd48a0 TA |
461 | }; |
462 | ||
c8149df0 | 463 | mmc_1: mmc@12210000 { |
906fd84e YK |
464 | compatible = "samsung,exynos5250-dw-mshc"; |
465 | interrupts = <0 76 0>; | |
466 | #address-cells = <1>; | |
467 | #size-cells = <0>; | |
84bd48a0 | 468 | reg = <0x12210000 0x1000>; |
fe273c3e | 469 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; |
2de6847c | 470 | clock-names = "biu", "ciu"; |
46285a90 | 471 | fifo-depth = <0x80>; |
e908d5c5 | 472 | status = "disabled"; |
84bd48a0 TA |
473 | }; |
474 | ||
c8149df0 | 475 | mmc_2: mmc@12220000 { |
906fd84e YK |
476 | compatible = "samsung,exynos5250-dw-mshc"; |
477 | interrupts = <0 77 0>; | |
478 | #address-cells = <1>; | |
479 | #size-cells = <0>; | |
84bd48a0 | 480 | reg = <0x12220000 0x1000>; |
fe273c3e | 481 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; |
2de6847c | 482 | clock-names = "biu", "ciu"; |
46285a90 | 483 | fifo-depth = <0x80>; |
e908d5c5 | 484 | status = "disabled"; |
84bd48a0 TA |
485 | }; |
486 | ||
c8149df0 | 487 | mmc_3: mmc@12230000 { |
84bd48a0 TA |
488 | compatible = "samsung,exynos5250-dw-mshc"; |
489 | reg = <0x12230000 0x1000>; | |
490 | interrupts = <0 78 0>; | |
491 | #address-cells = <1>; | |
492 | #size-cells = <0>; | |
fe273c3e | 493 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; |
2de6847c | 494 | clock-names = "biu", "ciu"; |
46285a90 | 495 | fifo-depth = <0x80>; |
e908d5c5 | 496 | status = "disabled"; |
84bd48a0 TA |
497 | }; |
498 | ||
28a48058 | 499 | i2s0: i2s@03830000 { |
64183656 | 500 | compatible = "samsung,s5pv210-i2s"; |
328aee4b | 501 | status = "disabled"; |
a0b5f81e | 502 | reg = <0x03830000 0x100>; |
4c4c7463 PV |
503 | dmas = <&pdma0 10 |
504 | &pdma0 9 | |
505 | &pdma0 8>; | |
506 | dma-names = "tx", "rx", "tx-sec"; | |
916ec47e PV |
507 | clocks = <&clock_audss EXYNOS_I2S_BUS>, |
508 | <&clock_audss EXYNOS_I2S_BUS>, | |
509 | <&clock_audss EXYNOS_SCLK_I2S>; | |
510 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
a0b5f81e | 511 | samsung,idma-addr = <0x03000000>; |
f8bfe2b0 TA |
512 | pinctrl-names = "default"; |
513 | pinctrl-0 = <&i2s0_bus>; | |
4c4c7463 PV |
514 | }; |
515 | ||
28a48058 | 516 | i2s1: i2s@12D60000 { |
64183656 | 517 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 518 | status = "disabled"; |
a0b5f81e MB |
519 | reg = <0x12D60000 0x100>; |
520 | dmas = <&pdma1 12 | |
521 | &pdma1 11>; | |
522 | dma-names = "tx", "rx"; | |
fe273c3e | 523 | clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; |
916ec47e | 524 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
525 | pinctrl-names = "default"; |
526 | pinctrl-0 = <&i2s1_bus>; | |
4c4c7463 PV |
527 | }; |
528 | ||
28a48058 | 529 | i2s2: i2s@12D70000 { |
64183656 | 530 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 531 | status = "disabled"; |
a0b5f81e MB |
532 | reg = <0x12D70000 0x100>; |
533 | dmas = <&pdma0 12 | |
534 | &pdma0 11>; | |
535 | dma-names = "tx", "rx"; | |
fe273c3e | 536 | clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; |
916ec47e | 537 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
538 | pinctrl-names = "default"; |
539 | pinctrl-0 = <&i2s2_bus>; | |
4c4c7463 PV |
540 | }; |
541 | ||
0b3dc97e VG |
542 | usb@12000000 { |
543 | compatible = "samsung,exynos5250-dwusb3"; | |
fe273c3e | 544 | clocks = <&clock CLK_USB3>; |
0b3dc97e VG |
545 | clock-names = "usbdrd30"; |
546 | #address-cells = <1>; | |
547 | #size-cells = <1>; | |
548 | ranges; | |
549 | ||
550 | dwc3 { | |
551 | compatible = "synopsys,dwc3"; | |
552 | reg = <0x12000000 0x10000>; | |
553 | interrupts = <0 72 0>; | |
554 | usb-phy = <&usb2_phy &usb3_phy>; | |
555 | }; | |
556 | }; | |
557 | ||
558 | usb3_phy: usbphy@12100000 { | |
896db3b3 VG |
559 | compatible = "samsung,exynos5250-usb3phy"; |
560 | reg = <0x12100000 0x100>; | |
fe273c3e | 561 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>; |
896db3b3 VG |
562 | clock-names = "ext_xtal", "usbdrd30"; |
563 | #address-cells = <1>; | |
564 | #size-cells = <1>; | |
565 | ranges; | |
566 | ||
567 | usbphy-sys { | |
568 | reg = <0x10040704 0x8>; | |
569 | }; | |
570 | }; | |
571 | ||
517083f4 VG |
572 | usbdrd_phy: phy@12100000 { |
573 | compatible = "samsung,exynos5250-usbdrd-phy"; | |
574 | reg = <0x12100000 0x100>; | |
575 | clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; | |
576 | clock-names = "phy", "ref"; | |
577 | samsung,pmu-syscon = <&pmu_system_controller>; | |
578 | #phy-cells = <1>; | |
579 | }; | |
580 | ||
13cbd1e3 VG |
581 | usb@12110000 { |
582 | compatible = "samsung,exynos4210-ehci"; | |
583 | reg = <0x12110000 0x100>; | |
584 | interrupts = <0 71 0>; | |
b3cd7d87 | 585 | |
fe273c3e | 586 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 587 | clock-names = "usbhost"; |
13cbd1e3 VG |
588 | }; |
589 | ||
7d40d867 VG |
590 | usb@12120000 { |
591 | compatible = "samsung,exynos4210-ohci"; | |
592 | reg = <0x12120000 0x100>; | |
593 | interrupts = <0 71 0>; | |
b3cd7d87 | 594 | |
fe273c3e | 595 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 596 | clock-names = "usbhost"; |
7d40d867 VG |
597 | }; |
598 | ||
0b3dc97e | 599 | usb2_phy: usbphy@12130000 { |
7ec892ef VG |
600 | compatible = "samsung,exynos5250-usb2phy"; |
601 | reg = <0x12130000 0x100>; | |
fe273c3e | 602 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>; |
7ec892ef VG |
603 | clock-names = "ext_xtal", "usbhost"; |
604 | #address-cells = <1>; | |
605 | #size-cells = <1>; | |
606 | ranges; | |
607 | ||
608 | usbphy-sys { | |
609 | reg = <0x10040704 0x8>, | |
610 | <0x10050230 0x4>; | |
611 | }; | |
612 | }; | |
613 | ||
022cf308 LKA |
614 | pwm: pwm@12dd0000 { |
615 | compatible = "samsung,exynos4210-pwm"; | |
616 | reg = <0x12dd0000 0x100>; | |
617 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
618 | #pwm-cells = <3>; | |
fe273c3e | 619 | clocks = <&clock CLK_PWM>; |
022cf308 LKA |
620 | clock-names = "timers"; |
621 | }; | |
622 | ||
b074abb7 KK |
623 | amba { |
624 | #address-cells = <1>; | |
625 | #size-cells = <1>; | |
626 | compatible = "arm,amba-bus"; | |
627 | interrupt-parent = <&gic>; | |
628 | ranges; | |
629 | ||
630 | pdma0: pdma@121A0000 { | |
631 | compatible = "arm,pl330", "arm,primecell"; | |
632 | reg = <0x121A0000 0x1000>; | |
633 | interrupts = <0 34 0>; | |
fe273c3e | 634 | clocks = <&clock CLK_PDMA0>; |
2de6847c | 635 | clock-names = "apb_pclk"; |
42cf2098 PV |
636 | #dma-cells = <1>; |
637 | #dma-channels = <8>; | |
638 | #dma-requests = <32>; | |
b074abb7 KK |
639 | }; |
640 | ||
641 | pdma1: pdma@121B0000 { | |
642 | compatible = "arm,pl330", "arm,primecell"; | |
643 | reg = <0x121B0000 0x1000>; | |
644 | interrupts = <0 35 0>; | |
fe273c3e | 645 | clocks = <&clock CLK_PDMA1>; |
2de6847c | 646 | clock-names = "apb_pclk"; |
42cf2098 PV |
647 | #dma-cells = <1>; |
648 | #dma-channels = <8>; | |
649 | #dma-requests = <32>; | |
b074abb7 KK |
650 | }; |
651 | ||
009f7c9f | 652 | mdma0: mdma@10800000 { |
b074abb7 KK |
653 | compatible = "arm,pl330", "arm,primecell"; |
654 | reg = <0x10800000 0x1000>; | |
655 | interrupts = <0 33 0>; | |
fe273c3e | 656 | clocks = <&clock CLK_MDMA0>; |
2de6847c | 657 | clock-names = "apb_pclk"; |
42cf2098 PV |
658 | #dma-cells = <1>; |
659 | #dma-channels = <8>; | |
660 | #dma-requests = <1>; | |
b074abb7 KK |
661 | }; |
662 | ||
009f7c9f | 663 | mdma1: mdma@11C10000 { |
b074abb7 KK |
664 | compatible = "arm,pl330", "arm,primecell"; |
665 | reg = <0x11C10000 0x1000>; | |
666 | interrupts = <0 124 0>; | |
fe273c3e | 667 | clocks = <&clock CLK_MDMA1>; |
2de6847c | 668 | clock-names = "apb_pclk"; |
42cf2098 PV |
669 | #dma-cells = <1>; |
670 | #dma-channels = <8>; | |
671 | #dma-requests = <1>; | |
b074abb7 KK |
672 | }; |
673 | }; | |
674 | ||
c31f566d | 675 | gsc_0: gsc@13e00000 { |
1128658a SAB |
676 | compatible = "samsung,exynos5-gsc"; |
677 | reg = <0x13e00000 0x1000>; | |
678 | interrupts = <0 85 0>; | |
6f9e95e6 | 679 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 680 | clocks = <&clock CLK_GSCL0>; |
2de6847c | 681 | clock-names = "gscl"; |
1128658a SAB |
682 | }; |
683 | ||
c31f566d | 684 | gsc_1: gsc@13e10000 { |
1128658a SAB |
685 | compatible = "samsung,exynos5-gsc"; |
686 | reg = <0x13e10000 0x1000>; | |
687 | interrupts = <0 86 0>; | |
6f9e95e6 | 688 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 689 | clocks = <&clock CLK_GSCL1>; |
2de6847c | 690 | clock-names = "gscl"; |
1128658a SAB |
691 | }; |
692 | ||
c31f566d | 693 | gsc_2: gsc@13e20000 { |
1128658a SAB |
694 | compatible = "samsung,exynos5-gsc"; |
695 | reg = <0x13e20000 0x1000>; | |
696 | interrupts = <0 87 0>; | |
6f9e95e6 | 697 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 698 | clocks = <&clock CLK_GSCL2>; |
2de6847c | 699 | clock-names = "gscl"; |
1128658a SAB |
700 | }; |
701 | ||
c31f566d | 702 | gsc_3: gsc@13e30000 { |
1128658a SAB |
703 | compatible = "samsung,exynos5-gsc"; |
704 | reg = <0x13e30000 0x1000>; | |
705 | interrupts = <0 88 0>; | |
6f9e95e6 | 706 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 707 | clocks = <&clock CLK_GSCL3>; |
2de6847c | 708 | clock-names = "gscl"; |
1128658a | 709 | }; |
566cf8ee RS |
710 | |
711 | hdmi { | |
0d1fc829 | 712 | compatible = "samsung,exynos4212-hdmi"; |
101250ce | 713 | reg = <0x14530000 0x70000>; |
566cf8ee | 714 | interrupts = <0 95 0>; |
fe273c3e AH |
715 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
716 | <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
717 | <&clock CLK_MOUT_HDMI>; | |
2de6847c | 718 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
27c16d19 | 719 | "sclk_hdmiphy", "mout_hdmi"; |
566cf8ee | 720 | }; |
5af0d8a3 RS |
721 | |
722 | mixer { | |
0d1fc829 | 723 | compatible = "samsung,exynos5250-mixer"; |
5af0d8a3 RS |
724 | reg = <0x14450000 0x10000>; |
725 | interrupts = <0 94 0>; | |
fe273c3e | 726 | clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; |
18fe6ef0 | 727 | clock-names = "mixer", "sclk_hdmi"; |
5af0d8a3 | 728 | }; |
ad4aebe1 | 729 | |
77899d53 VS |
730 | dp_phy: video-phy@10040720 { |
731 | compatible = "samsung,exynos5250-dp-video-phy"; | |
732 | reg = <0x10040720 4>; | |
733 | #phy-cells = <0>; | |
734 | }; | |
735 | ||
736 | dp-controller@145B0000 { | |
fe273c3e | 737 | clocks = <&clock CLK_DP>; |
0f72a9ec | 738 | clock-names = "dp"; |
77899d53 VS |
739 | phys = <&dp_phy>; |
740 | phy-names = "dp"; | |
ad4aebe1 | 741 | }; |
a7389cb1 | 742 | |
9ee35a5b | 743 | fimd@14400000 { |
fe273c3e | 744 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
a7389cb1 LKA |
745 | clock-names = "sclk_fimd", "fimd"; |
746 | }; | |
f408f9db NKC |
747 | |
748 | adc: adc@12D10000 { | |
749 | compatible = "samsung,exynos-adc-v1"; | |
750 | reg = <0x12D10000 0x100>, <0x10040718 0x4>; | |
751 | interrupts = <0 106 0>; | |
fe273c3e | 752 | clocks = <&clock CLK_ADC>; |
f408f9db NKC |
753 | clock-names = "adc"; |
754 | #io-channel-cells = <1>; | |
755 | io-channel-ranges; | |
756 | status = "disabled"; | |
757 | }; | |
183af252 NKC |
758 | |
759 | sss@10830000 { | |
760 | compatible = "samsung,exynos4210-secss"; | |
761 | reg = <0x10830000 0x10000>; | |
762 | interrupts = <0 112 0>; | |
763 | clocks = <&clock 348>; | |
764 | clock-names = "secss"; | |
765 | }; | |
b074abb7 | 766 | }; |