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b074abb7 KK |
1 | /* |
2 | * SAMSUNG EXYNOS5250 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. | |
8 | * EXYNOS5250 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, | |
13 | * additional nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
fe273c3e | 20 | #include <dt-bindings/clock/exynos5250.h> |
e6c21cba | 21 | #include "exynos5.dtsi" |
9843a223 | 22 | #include "exynos4-cpu-thermal.dtsi" |
602408e3 | 23 | #include <dt-bindings/clock/exynos-audss-clk.h> |
b074abb7 KK |
24 | |
25 | / { | |
8bdb31b4 | 26 | compatible = "samsung,exynos5250", "samsung,exynos5"; |
b074abb7 | 27 | |
79989ba3 TA |
28 | aliases { |
29 | spi0 = &spi_0; | |
30 | spi1 = &spi_1; | |
31 | spi2 = &spi_2; | |
1128658a SAB |
32 | gsc0 = &gsc_0; |
33 | gsc1 = &gsc_1; | |
34 | gsc2 = &gsc_2; | |
35 | gsc3 = &gsc_3; | |
c8149df0 YK |
36 | mshc0 = &mmc_0; |
37 | mshc1 = &mmc_1; | |
38 | mshc2 = &mmc_2; | |
39 | mshc3 = &mmc_3; | |
b9fa3e7b AK |
40 | i2c4 = &i2c_4; |
41 | i2c5 = &i2c_5; | |
42 | i2c6 = &i2c_6; | |
43 | i2c7 = &i2c_7; | |
44 | i2c8 = &i2c_8; | |
ba0d7ed3 | 45 | i2c9 = &i2c_9; |
f8bfe2b0 TA |
46 | pinctrl0 = &pinctrl_0; |
47 | pinctrl1 = &pinctrl_1; | |
48 | pinctrl2 = &pinctrl_2; | |
49 | pinctrl3 = &pinctrl_3; | |
79989ba3 TA |
50 | }; |
51 | ||
1897d2f3 CK |
52 | cpus { |
53 | #address-cells = <1>; | |
54 | #size-cells = <0>; | |
55 | ||
bf4a0bed | 56 | cpu0: cpu@0 { |
1897d2f3 CK |
57 | device_type = "cpu"; |
58 | compatible = "arm,cortex-a15"; | |
59 | reg = <0>; | |
0da80563 | 60 | clock-frequency = <1700000000>; |
846c5300 TA |
61 | clocks = <&clock CLK_ARM_CLK>; |
62 | clock-names = "cpu"; | |
63 | clock-latency = <140000>; | |
64 | ||
65 | operating-points = < | |
66 | 1700000 1300000 | |
67 | 1600000 1250000 | |
68 | 1500000 1225000 | |
69 | 1400000 1200000 | |
70 | 1300000 1150000 | |
71 | 1200000 1125000 | |
72 | 1100000 1100000 | |
73 | 1000000 1075000 | |
74 | 900000 1050000 | |
75 | 800000 1025000 | |
76 | 700000 1012500 | |
77 | 600000 1000000 | |
78 | 500000 975000 | |
79 | 400000 950000 | |
80 | 300000 937500 | |
81 | 200000 925000 | |
82 | >; | |
bf4a0bed LM |
83 | cooling-min-level = <15>; |
84 | cooling-max-level = <9>; | |
85 | #cooling-cells = <2>; /* min followed by max */ | |
1897d2f3 CK |
86 | }; |
87 | cpu@1 { | |
88 | device_type = "cpu"; | |
89 | compatible = "arm,cortex-a15"; | |
90 | reg = <1>; | |
0da80563 | 91 | clock-frequency = <1700000000>; |
1897d2f3 | 92 | }; |
79989ba3 TA |
93 | }; |
94 | ||
5d99cc59 KK |
95 | soc: soc { |
96 | sysram@02020000 { | |
97 | compatible = "mmio-sram"; | |
98 | reg = <0x02020000 0x30000>; | |
99 | #address-cells = <1>; | |
100 | #size-cells = <1>; | |
101 | ranges = <0 0x02020000 0x30000>; | |
102 | ||
103 | smp-sysram@0 { | |
104 | compatible = "samsung,exynos4210-sysram"; | |
105 | reg = <0x0 0x1000>; | |
106 | }; | |
107 | ||
108 | smp-sysram@2f000 { | |
109 | compatible = "samsung,exynos4210-sysram-ns"; | |
110 | reg = <0x2f000 0x1000>; | |
111 | }; | |
b3205dea SK |
112 | }; |
113 | ||
5d99cc59 KK |
114 | pd_gsc: gsc-power-domain@10044000 { |
115 | compatible = "samsung,exynos4210-pd"; | |
116 | reg = <0x10044000 0x20>; | |
117 | #power-domain-cells = <0>; | |
55d74adf | 118 | label = "GSC"; |
b3205dea | 119 | }; |
6f9e95e6 | 120 | |
5d99cc59 KK |
121 | pd_mfc: mfc-power-domain@10044040 { |
122 | compatible = "samsung,exynos4210-pd"; | |
123 | reg = <0x10044040 0x20>; | |
124 | #power-domain-cells = <0>; | |
55d74adf | 125 | label = "MFC"; |
5d99cc59 | 126 | }; |
6f9e95e6 | 127 | |
5d99cc59 KK |
128 | pd_disp1: disp1-power-domain@100440A0 { |
129 | compatible = "samsung,exynos4210-pd"; | |
130 | reg = <0x100440A0 0x20>; | |
131 | #power-domain-cells = <0>; | |
55d74adf | 132 | label = "DISP1"; |
5d99cc59 KK |
133 | clocks = <&clock CLK_FIN_PLL>, |
134 | <&clock CLK_MOUT_ACLK200_DISP1_SUB>, | |
135 | <&clock CLK_MOUT_ACLK300_DISP1_SUB>; | |
136 | clock-names = "oscclk", "clk0", "clk1"; | |
137 | }; | |
2d2c9a8d | 138 | |
5d99cc59 KK |
139 | clock: clock-controller@10010000 { |
140 | compatible = "samsung,exynos5250-clock"; | |
141 | reg = <0x10010000 0x30000>; | |
142 | #clock-cells = <1>; | |
143 | }; | |
d8bafc87 | 144 | |
5d99cc59 KK |
145 | clock_audss: audss-clock-controller@3810000 { |
146 | compatible = "samsung,exynos5250-audss-clock"; | |
147 | reg = <0x03810000 0x0C>; | |
148 | #clock-cells = <1>; | |
149 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, | |
150 | <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; | |
151 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; | |
152 | }; | |
bba23d95 | 153 | |
5d99cc59 KK |
154 | timer { |
155 | compatible = "arm,armv7-timer"; | |
156 | interrupts = <1 13 0xf08>, | |
157 | <1 14 0xf08>, | |
158 | <1 11 0xf08>, | |
159 | <1 10 0xf08>; | |
160 | /* | |
161 | * Unfortunately we need this since some versions | |
162 | * of U-Boot on Exynos don't set the CNTFRQ register, | |
163 | * so we need the value from DT. | |
164 | */ | |
165 | clock-frequency = <24000000>; | |
166 | }; | |
b074abb7 | 167 | |
5d99cc59 KK |
168 | mct@101C0000 { |
169 | compatible = "samsung,exynos4210-mct"; | |
170 | reg = <0x101C0000 0x800>; | |
171 | interrupt-controller; | |
bbd9700a | 172 | #interrupt-cells = <2>; |
5d99cc59 KK |
173 | interrupt-parent = <&mct_map>; |
174 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | |
175 | <4 0>, <5 0>; | |
176 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; | |
177 | clock-names = "fin_pll", "mct"; | |
178 | ||
179 | mct_map: mct-map { | |
180 | #interrupt-cells = <2>; | |
181 | #address-cells = <0>; | |
182 | #size-cells = <0>; | |
183 | interrupt-map = <0x0 0 &combiner 23 3>, | |
184 | <0x1 0 &combiner 23 4>, | |
185 | <0x2 0 &combiner 25 2>, | |
186 | <0x3 0 &combiner 25 3>, | |
27e64b27 KK |
187 | <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>, |
188 | <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>; | |
5d99cc59 | 189 | }; |
bbd9700a | 190 | }; |
bbd9700a | 191 | |
5d99cc59 KK |
192 | pmu { |
193 | compatible = "arm,cortex-a15-pmu"; | |
194 | interrupt-parent = <&combiner>; | |
195 | interrupts = <1 2>, <22 4>; | |
196 | }; | |
4f801e59 | 197 | |
5d99cc59 KK |
198 | pinctrl_0: pinctrl@11400000 { |
199 | compatible = "samsung,exynos5250-pinctrl"; | |
200 | reg = <0x11400000 0x1000>; | |
888950b0 | 201 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
f8bfe2b0 | 202 | |
5d99cc59 KK |
203 | wakup_eint: wakeup-interrupt-controller { |
204 | compatible = "samsung,exynos4210-wakeup-eint"; | |
205 | interrupt-parent = <&gic>; | |
888950b0 | 206 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 | 207 | }; |
f8bfe2b0 | 208 | }; |
f8bfe2b0 | 209 | |
5d99cc59 KK |
210 | pinctrl_1: pinctrl@13400000 { |
211 | compatible = "samsung,exynos5250-pinctrl"; | |
212 | reg = <0x13400000 0x1000>; | |
888950b0 | 213 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 | 214 | }; |
f8bfe2b0 | 215 | |
5d99cc59 KK |
216 | pinctrl_2: pinctrl@10d10000 { |
217 | compatible = "samsung,exynos5250-pinctrl"; | |
218 | reg = <0x10d10000 0x1000>; | |
888950b0 | 219 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 | 220 | }; |
f8bfe2b0 | 221 | |
5d99cc59 KK |
222 | pinctrl_3: pinctrl@03860000 { |
223 | compatible = "samsung,exynos5250-pinctrl"; | |
224 | reg = <0x03860000 0x1000>; | |
888950b0 | 225 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 | 226 | }; |
f8bfe2b0 | 227 | |
5d99cc59 KK |
228 | pmu_system_controller: system-controller@10040000 { |
229 | compatible = "samsung,exynos5250-pmu", "syscon"; | |
230 | reg = <0x10040000 0x5000>; | |
231 | clock-names = "clkout16"; | |
232 | clocks = <&clock CLK_FIN_PLL>; | |
233 | #clock-cells = <1>; | |
234 | interrupt-controller; | |
235 | #interrupt-cells = <3>; | |
236 | interrupt-parent = <&gic>; | |
237 | }; | |
c680036a | 238 | |
5d99cc59 KK |
239 | watchdog@101D0000 { |
240 | compatible = "samsung,exynos5250-wdt"; | |
241 | reg = <0x101D0000 0x100>; | |
888950b0 | 242 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
243 | clocks = <&clock CLK_WDT>; |
244 | clock-names = "watchdog"; | |
245 | samsung,syscon-phandle = <&pmu_system_controller>; | |
246 | }; | |
b074abb7 | 247 | |
5d99cc59 KK |
248 | g2d@10850000 { |
249 | compatible = "samsung,exynos5250-g2d"; | |
250 | reg = <0x10850000 0x1000>; | |
888950b0 | 251 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
252 | clocks = <&clock CLK_G2D>; |
253 | clock-names = "fimg2d"; | |
254 | iommus = <&sysmmu_g2d>; | |
255 | }; | |
21aa5217 | 256 | |
5d99cc59 KK |
257 | mfc: codec@11000000 { |
258 | compatible = "samsung,mfc-v6"; | |
259 | reg = <0x11000000 0x10000>; | |
888950b0 | 260 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
261 | power-domains = <&pd_mfc>; |
262 | clocks = <&clock CLK_MFC>; | |
263 | clock-names = "mfc"; | |
264 | iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; | |
265 | iommu-names = "left", "right"; | |
266 | }; | |
2eae613b | 267 | |
5d99cc59 KK |
268 | rotator: rotator@11C00000 { |
269 | compatible = "samsung,exynos5250-rotator"; | |
270 | reg = <0x11C00000 0x64>; | |
888950b0 | 271 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
272 | clocks = <&clock CLK_ROTATOR>; |
273 | clock-names = "rotator"; | |
274 | iommus = <&sysmmu_rotator>; | |
275 | }; | |
d35e20d9 | 276 | |
5d99cc59 KK |
277 | tmu: tmu@10060000 { |
278 | compatible = "samsung,exynos5250-tmu"; | |
279 | reg = <0x10060000 0x100>; | |
888950b0 | 280 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
281 | clocks = <&clock CLK_TMU>; |
282 | clock-names = "tmu_apbif"; | |
283 | #include "exynos4412-tmu-sensor-conf.dtsi" | |
284 | }; | |
ef405e04 | 285 | |
5d99cc59 KK |
286 | sata: sata@122F0000 { |
287 | compatible = "snps,dwc-ahci"; | |
288 | samsung,sata-freq = <66>; | |
289 | reg = <0x122F0000 0x1ff>; | |
888950b0 | 290 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
291 | clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; |
292 | clock-names = "sata", "sclk_sata"; | |
293 | phys = <&sata_phy>; | |
294 | phy-names = "sata-phy"; | |
295 | status = "disabled"; | |
296 | }; | |
9843a223 | 297 | |
5d99cc59 KK |
298 | sata_phy: sata-phy@12170000 { |
299 | compatible = "samsung,exynos5250-sata-phy"; | |
300 | reg = <0x12170000 0x1ff>; | |
301 | clocks = <&clock CLK_SATA_PHYCTRL>; | |
302 | clock-names = "sata_phyctrl"; | |
303 | #phy-cells = <0>; | |
304 | samsung,syscon-phandle = <&pmu_system_controller>; | |
305 | status = "disabled"; | |
bf4a0bed | 306 | }; |
bf4a0bed | 307 | |
5d99cc59 KK |
308 | /* i2c_0-3 are defined in exynos5.dtsi */ |
309 | i2c_4: i2c@12CA0000 { | |
310 | compatible = "samsung,s3c2440-i2c"; | |
311 | reg = <0x12CA0000 0x100>; | |
888950b0 | 312 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
313 | #address-cells = <1>; |
314 | #size-cells = <0>; | |
315 | clocks = <&clock CLK_I2C4>; | |
316 | clock-names = "i2c"; | |
317 | pinctrl-names = "default"; | |
318 | pinctrl-0 = <&i2c4_bus>; | |
319 | status = "disabled"; | |
320 | }; | |
c47d244a | 321 | |
5d99cc59 KK |
322 | i2c_5: i2c@12CB0000 { |
323 | compatible = "samsung,s3c2440-i2c"; | |
324 | reg = <0x12CB0000 0x100>; | |
888950b0 | 325 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
326 | #address-cells = <1>; |
327 | #size-cells = <0>; | |
328 | clocks = <&clock CLK_I2C5>; | |
329 | clock-names = "i2c"; | |
330 | pinctrl-names = "default"; | |
331 | pinctrl-0 = <&i2c5_bus>; | |
332 | status = "disabled"; | |
333 | }; | |
c47d244a | 334 | |
5d99cc59 KK |
335 | i2c_6: i2c@12CC0000 { |
336 | compatible = "samsung,s3c2440-i2c"; | |
337 | reg = <0x12CC0000 0x100>; | |
888950b0 | 338 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
339 | #address-cells = <1>; |
340 | #size-cells = <0>; | |
341 | clocks = <&clock CLK_I2C6>; | |
342 | clock-names = "i2c"; | |
343 | pinctrl-names = "default"; | |
344 | pinctrl-0 = <&i2c6_bus>; | |
345 | status = "disabled"; | |
346 | }; | |
b074abb7 | 347 | |
5d99cc59 KK |
348 | i2c_7: i2c@12CD0000 { |
349 | compatible = "samsung,s3c2440-i2c"; | |
350 | reg = <0x12CD0000 0x100>; | |
888950b0 | 351 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
352 | #address-cells = <1>; |
353 | #size-cells = <0>; | |
354 | clocks = <&clock CLK_I2C7>; | |
355 | clock-names = "i2c"; | |
356 | pinctrl-names = "default"; | |
357 | pinctrl-0 = <&i2c7_bus>; | |
358 | status = "disabled"; | |
359 | }; | |
b074abb7 | 360 | |
5d99cc59 KK |
361 | i2c_8: i2c@12CE0000 { |
362 | compatible = "samsung,s3c2440-hdmiphy-i2c"; | |
363 | reg = <0x12CE0000 0x1000>; | |
888950b0 | 364 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
365 | #address-cells = <1>; |
366 | #size-cells = <0>; | |
367 | clocks = <&clock CLK_I2C_HDMI>; | |
368 | clock-names = "i2c"; | |
369 | status = "disabled"; | |
370 | }; | |
b074abb7 | 371 | |
5d99cc59 KK |
372 | i2c_9: i2c@121D0000 { |
373 | compatible = "samsung,exynos5-sata-phy-i2c"; | |
374 | reg = <0x121D0000 0x100>; | |
375 | #address-cells = <1>; | |
376 | #size-cells = <0>; | |
377 | clocks = <&clock CLK_SATA_PHYI2C>; | |
378 | clock-names = "i2c"; | |
379 | status = "disabled"; | |
380 | }; | |
3e3e9ce4 | 381 | |
5d99cc59 KK |
382 | spi_0: spi@12d20000 { |
383 | compatible = "samsung,exynos4210-spi"; | |
384 | status = "disabled"; | |
385 | reg = <0x12d20000 0x100>; | |
888950b0 | 386 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
387 | dmas = <&pdma0 5 |
388 | &pdma0 4>; | |
389 | dma-names = "tx", "rx"; | |
390 | #address-cells = <1>; | |
391 | #size-cells = <0>; | |
392 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; | |
393 | clock-names = "spi", "spi_busclk0"; | |
394 | pinctrl-names = "default"; | |
395 | pinctrl-0 = <&spi0_bus>; | |
396 | }; | |
24025f6f | 397 | |
5d99cc59 KK |
398 | spi_1: spi@12d30000 { |
399 | compatible = "samsung,exynos4210-spi"; | |
400 | status = "disabled"; | |
401 | reg = <0x12d30000 0x100>; | |
888950b0 | 402 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
403 | dmas = <&pdma1 5 |
404 | &pdma1 4>; | |
405 | dma-names = "tx", "rx"; | |
406 | #address-cells = <1>; | |
407 | #size-cells = <0>; | |
408 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; | |
409 | clock-names = "spi", "spi_busclk0"; | |
410 | pinctrl-names = "default"; | |
411 | pinctrl-0 = <&spi1_bus>; | |
412 | }; | |
b074abb7 | 413 | |
5d99cc59 KK |
414 | spi_2: spi@12d40000 { |
415 | compatible = "samsung,exynos4210-spi"; | |
416 | status = "disabled"; | |
417 | reg = <0x12d40000 0x100>; | |
888950b0 | 418 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
419 | dmas = <&pdma0 7 |
420 | &pdma0 6>; | |
421 | dma-names = "tx", "rx"; | |
422 | #address-cells = <1>; | |
423 | #size-cells = <0>; | |
424 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; | |
425 | clock-names = "spi", "spi_busclk0"; | |
426 | pinctrl-names = "default"; | |
427 | pinctrl-0 = <&spi2_bus>; | |
428 | }; | |
79989ba3 | 429 | |
5d99cc59 KK |
430 | mmc_0: mmc@12200000 { |
431 | compatible = "samsung,exynos5250-dw-mshc"; | |
888950b0 | 432 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
433 | #address-cells = <1>; |
434 | #size-cells = <0>; | |
435 | reg = <0x12200000 0x1000>; | |
436 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; | |
437 | clock-names = "biu", "ciu"; | |
438 | fifo-depth = <0x80>; | |
439 | status = "disabled"; | |
440 | }; | |
79989ba3 | 441 | |
5d99cc59 KK |
442 | mmc_1: mmc@12210000 { |
443 | compatible = "samsung,exynos5250-dw-mshc"; | |
888950b0 | 444 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
445 | #address-cells = <1>; |
446 | #size-cells = <0>; | |
447 | reg = <0x12210000 0x1000>; | |
448 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; | |
449 | clock-names = "biu", "ciu"; | |
450 | fifo-depth = <0x80>; | |
451 | status = "disabled"; | |
452 | }; | |
79989ba3 | 453 | |
5d99cc59 KK |
454 | mmc_2: mmc@12220000 { |
455 | compatible = "samsung,exynos5250-dw-mshc"; | |
888950b0 | 456 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
457 | #address-cells = <1>; |
458 | #size-cells = <0>; | |
459 | reg = <0x12220000 0x1000>; | |
460 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; | |
461 | clock-names = "biu", "ciu"; | |
462 | fifo-depth = <0x80>; | |
463 | status = "disabled"; | |
464 | }; | |
84bd48a0 | 465 | |
5d99cc59 KK |
466 | mmc_3: mmc@12230000 { |
467 | compatible = "samsung,exynos5250-dw-mshc"; | |
468 | reg = <0x12230000 0x1000>; | |
888950b0 | 469 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
470 | #address-cells = <1>; |
471 | #size-cells = <0>; | |
472 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; | |
473 | clock-names = "biu", "ciu"; | |
474 | fifo-depth = <0x80>; | |
475 | status = "disabled"; | |
476 | }; | |
84bd48a0 | 477 | |
5d99cc59 KK |
478 | i2s0: i2s@03830000 { |
479 | compatible = "samsung,s5pv210-i2s"; | |
480 | status = "disabled"; | |
481 | reg = <0x03830000 0x100>; | |
482 | dmas = <&pdma0 10 | |
483 | &pdma0 9 | |
484 | &pdma0 8>; | |
485 | dma-names = "tx", "rx", "tx-sec"; | |
486 | clocks = <&clock_audss EXYNOS_I2S_BUS>, | |
487 | <&clock_audss EXYNOS_I2S_BUS>, | |
488 | <&clock_audss EXYNOS_SCLK_I2S>; | |
489 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
490 | samsung,idma-addr = <0x03000000>; | |
491 | pinctrl-names = "default"; | |
492 | pinctrl-0 = <&i2s0_bus>; | |
493 | }; | |
84bd48a0 | 494 | |
5d99cc59 KK |
495 | i2s1: i2s@12D60000 { |
496 | compatible = "samsung,s3c6410-i2s"; | |
497 | status = "disabled"; | |
498 | reg = <0x12D60000 0x100>; | |
499 | dmas = <&pdma1 12 | |
500 | &pdma1 11>; | |
501 | dma-names = "tx", "rx"; | |
502 | clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; | |
503 | clock-names = "iis", "i2s_opclk0"; | |
504 | pinctrl-names = "default"; | |
505 | pinctrl-0 = <&i2s1_bus>; | |
506 | }; | |
84bd48a0 | 507 | |
5d99cc59 KK |
508 | i2s2: i2s@12D70000 { |
509 | compatible = "samsung,s3c6410-i2s"; | |
510 | status = "disabled"; | |
511 | reg = <0x12D70000 0x100>; | |
512 | dmas = <&pdma0 12 | |
513 | &pdma0 11>; | |
514 | dma-names = "tx", "rx"; | |
515 | clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; | |
516 | clock-names = "iis", "i2s_opclk0"; | |
517 | pinctrl-names = "default"; | |
518 | pinctrl-0 = <&i2s2_bus>; | |
519 | }; | |
4c4c7463 | 520 | |
5d99cc59 KK |
521 | usb_dwc3 { |
522 | compatible = "samsung,exynos5250-dwusb3"; | |
523 | clocks = <&clock CLK_USB3>; | |
524 | clock-names = "usbdrd30"; | |
525 | #address-cells = <1>; | |
526 | #size-cells = <1>; | |
527 | ranges; | |
528 | ||
529 | usbdrd_dwc3: dwc3@12000000 { | |
530 | compatible = "synopsys,dwc3"; | |
531 | reg = <0x12000000 0x10000>; | |
888950b0 | 532 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
533 | phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; |
534 | phy-names = "usb2-phy", "usb3-phy"; | |
535 | }; | |
536 | }; | |
4c4c7463 | 537 | |
5d99cc59 KK |
538 | usbdrd_phy: phy@12100000 { |
539 | compatible = "samsung,exynos5250-usbdrd-phy"; | |
540 | reg = <0x12100000 0x100>; | |
541 | clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; | |
542 | clock-names = "phy", "ref"; | |
543 | samsung,pmu-syscon = <&pmu_system_controller>; | |
544 | #phy-cells = <1>; | |
545 | }; | |
4c4c7463 | 546 | |
5d99cc59 KK |
547 | ehci: usb@12110000 { |
548 | compatible = "samsung,exynos4210-ehci"; | |
549 | reg = <0x12110000 0x100>; | |
888950b0 | 550 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
0b3dc97e | 551 | |
5d99cc59 KK |
552 | clocks = <&clock CLK_USB2>; |
553 | clock-names = "usbhost"; | |
554 | #address-cells = <1>; | |
555 | #size-cells = <0>; | |
556 | port@0 { | |
557 | reg = <0>; | |
558 | phys = <&usb2_phy_gen 1>; | |
559 | }; | |
896db3b3 | 560 | }; |
517083f4 | 561 | |
5d99cc59 KK |
562 | ohci: usb@12120000 { |
563 | compatible = "samsung,exynos4210-ohci"; | |
564 | reg = <0x12120000 0x100>; | |
888950b0 | 565 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
b3cd7d87 | 566 | |
5d99cc59 KK |
567 | clocks = <&clock CLK_USB2>; |
568 | clock-names = "usbhost"; | |
569 | #address-cells = <1>; | |
570 | #size-cells = <0>; | |
571 | port@0 { | |
572 | reg = <0>; | |
573 | phys = <&usb2_phy_gen 1>; | |
574 | }; | |
dba2f058 | 575 | }; |
13cbd1e3 | 576 | |
5d99cc59 KK |
577 | usb2_phy_gen: phy@12130000 { |
578 | compatible = "samsung,exynos5250-usb2-phy"; | |
579 | reg = <0x12130000 0x100>; | |
580 | clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; | |
581 | clock-names = "phy", "ref"; | |
582 | #phy-cells = <1>; | |
583 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
584 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
585 | }; | |
b3cd7d87 | 586 | |
5d99cc59 KK |
587 | amba { |
588 | #address-cells = <1>; | |
589 | #size-cells = <1>; | |
590 | compatible = "simple-bus"; | |
591 | interrupt-parent = <&gic>; | |
592 | ranges; | |
593 | ||
594 | pdma0: pdma@121A0000 { | |
595 | compatible = "arm,pl330", "arm,primecell"; | |
596 | reg = <0x121A0000 0x1000>; | |
888950b0 | 597 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
598 | clocks = <&clock CLK_PDMA0>; |
599 | clock-names = "apb_pclk"; | |
600 | #dma-cells = <1>; | |
601 | #dma-channels = <8>; | |
602 | #dma-requests = <32>; | |
603 | }; | |
604 | ||
605 | pdma1: pdma@121B0000 { | |
606 | compatible = "arm,pl330", "arm,primecell"; | |
607 | reg = <0x121B0000 0x1000>; | |
888950b0 | 608 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
609 | clocks = <&clock CLK_PDMA1>; |
610 | clock-names = "apb_pclk"; | |
611 | #dma-cells = <1>; | |
612 | #dma-channels = <8>; | |
613 | #dma-requests = <32>; | |
614 | }; | |
615 | ||
616 | mdma0: mdma@10800000 { | |
617 | compatible = "arm,pl330", "arm,primecell"; | |
618 | reg = <0x10800000 0x1000>; | |
888950b0 | 619 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
620 | clocks = <&clock CLK_MDMA0>; |
621 | clock-names = "apb_pclk"; | |
622 | #dma-cells = <1>; | |
623 | #dma-channels = <8>; | |
624 | #dma-requests = <1>; | |
625 | }; | |
626 | ||
627 | mdma1: mdma@11C10000 { | |
628 | compatible = "arm,pl330", "arm,primecell"; | |
629 | reg = <0x11C10000 0x1000>; | |
888950b0 | 630 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
631 | clocks = <&clock CLK_MDMA1>; |
632 | clock-names = "apb_pclk"; | |
633 | #dma-cells = <1>; | |
634 | #dma-channels = <8>; | |
635 | #dma-requests = <1>; | |
636 | }; | |
dba2f058 | 637 | }; |
7d40d867 | 638 | |
5d99cc59 KK |
639 | gsc_0: gsc@13e00000 { |
640 | compatible = "samsung,exynos5-gsc"; | |
641 | reg = <0x13e00000 0x1000>; | |
888950b0 | 642 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
643 | power-domains = <&pd_gsc>; |
644 | clocks = <&clock CLK_GSCL0>; | |
645 | clock-names = "gscl"; | |
646 | iommu = <&sysmmu_gsc0>; | |
647 | }; | |
dba2f058 | 648 | |
5d99cc59 KK |
649 | gsc_1: gsc@13e10000 { |
650 | compatible = "samsung,exynos5-gsc"; | |
651 | reg = <0x13e10000 0x1000>; | |
888950b0 | 652 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
653 | power-domains = <&pd_gsc>; |
654 | clocks = <&clock CLK_GSCL1>; | |
655 | clock-names = "gscl"; | |
656 | iommu = <&sysmmu_gsc1>; | |
b074abb7 | 657 | }; |
b074abb7 | 658 | |
5d99cc59 KK |
659 | gsc_2: gsc@13e20000 { |
660 | compatible = "samsung,exynos5-gsc"; | |
661 | reg = <0x13e20000 0x1000>; | |
888950b0 | 662 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
663 | power-domains = <&pd_gsc>; |
664 | clocks = <&clock CLK_GSCL2>; | |
665 | clock-names = "gscl"; | |
666 | iommu = <&sysmmu_gsc2>; | |
667 | }; | |
1128658a | 668 | |
5d99cc59 KK |
669 | gsc_3: gsc@13e30000 { |
670 | compatible = "samsung,exynos5-gsc"; | |
671 | reg = <0x13e30000 0x1000>; | |
888950b0 | 672 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
673 | power-domains = <&pd_gsc>; |
674 | clocks = <&clock CLK_GSCL3>; | |
675 | clock-names = "gscl"; | |
676 | iommu = <&sysmmu_gsc3>; | |
677 | }; | |
1128658a | 678 | |
5d99cc59 KK |
679 | hdmi: hdmi@14530000 { |
680 | compatible = "samsung,exynos4212-hdmi"; | |
681 | reg = <0x14530000 0x70000>; | |
682 | power-domains = <&pd_disp1>; | |
888950b0 | 683 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
684 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
685 | <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
686 | <&clock CLK_MOUT_HDMI>; | |
687 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", | |
688 | "sclk_hdmiphy", "mout_hdmi"; | |
689 | samsung,syscon-phandle = <&pmu_system_controller>; | |
690 | }; | |
1128658a | 691 | |
5343b157 MS |
692 | hdmicec: cec@101B0000 { |
693 | compatible = "samsung,s5p-cec"; | |
694 | reg = <0x101B0000 0x200>; | |
695 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
696 | clocks = <&clock CLK_HDMI_CEC>; | |
697 | clock-names = "hdmicec"; | |
698 | samsung,syscon-phandle = <&pmu_system_controller>; | |
699 | hdmi-phandle = <&hdmi>; | |
700 | pinctrl-names = "default"; | |
701 | pinctrl-0 = <&hdmi_cec>; | |
702 | status = "disabled"; | |
703 | }; | |
704 | ||
5d99cc59 KK |
705 | mixer@14450000 { |
706 | compatible = "samsung,exynos5250-mixer"; | |
707 | reg = <0x14450000 0x10000>; | |
708 | power-domains = <&pd_disp1>; | |
888950b0 | 709 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
710 | clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, |
711 | <&clock CLK_SCLK_HDMI>; | |
712 | clock-names = "mixer", "hdmi", "sclk_hdmi"; | |
713 | iommus = <&sysmmu_tv>; | |
714 | }; | |
566cf8ee | 715 | |
5d99cc59 KK |
716 | dp_phy: video-phy { |
717 | compatible = "samsung,exynos5250-dp-video-phy"; | |
718 | samsung,pmu-syscon = <&pmu_system_controller>; | |
719 | #phy-cells = <0>; | |
720 | }; | |
5af0d8a3 | 721 | |
5d99cc59 KK |
722 | adc: adc@12D10000 { |
723 | compatible = "samsung,exynos-adc-v1"; | |
724 | reg = <0x12D10000 0x100>; | |
888950b0 | 725 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
726 | clocks = <&clock CLK_ADC>; |
727 | clock-names = "adc"; | |
728 | #io-channel-cells = <1>; | |
729 | io-channel-ranges; | |
730 | samsung,syscon-phandle = <&pmu_system_controller>; | |
731 | status = "disabled"; | |
732 | }; | |
ad4aebe1 | 733 | |
5d99cc59 KK |
734 | sss@10830000 { |
735 | compatible = "samsung,exynos4210-secss"; | |
736 | reg = <0x10830000 0x300>; | |
888950b0 | 737 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
738 | clocks = <&clock CLK_SSS>; |
739 | clock-names = "secss"; | |
740 | }; | |
77899d53 | 741 | |
5d99cc59 KK |
742 | sysmmu_g2d: sysmmu@10A60000 { |
743 | compatible = "samsung,exynos-sysmmu"; | |
744 | reg = <0x10A60000 0x1000>; | |
745 | interrupt-parent = <&combiner>; | |
746 | interrupts = <24 5>; | |
747 | clock-names = "sysmmu", "master"; | |
748 | clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; | |
749 | #iommu-cells = <0>; | |
750 | }; | |
183af252 | 751 | |
5d99cc59 KK |
752 | sysmmu_mfc_r: sysmmu@11200000 { |
753 | compatible = "samsung,exynos-sysmmu"; | |
754 | reg = <0x11200000 0x1000>; | |
755 | interrupt-parent = <&combiner>; | |
756 | interrupts = <6 2>; | |
757 | power-domains = <&pd_mfc>; | |
758 | clock-names = "sysmmu", "master"; | |
759 | clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; | |
760 | #iommu-cells = <0>; | |
761 | }; | |
6cbfdd73 | 762 | |
5d99cc59 KK |
763 | sysmmu_mfc_l: sysmmu@11210000 { |
764 | compatible = "samsung,exynos-sysmmu"; | |
765 | reg = <0x11210000 0x1000>; | |
766 | interrupt-parent = <&combiner>; | |
767 | interrupts = <8 5>; | |
768 | power-domains = <&pd_mfc>; | |
769 | clock-names = "sysmmu", "master"; | |
770 | clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; | |
771 | #iommu-cells = <0>; | |
772 | }; | |
6cbfdd73 | 773 | |
5d99cc59 KK |
774 | sysmmu_rotator: sysmmu@11D40000 { |
775 | compatible = "samsung,exynos-sysmmu"; | |
776 | reg = <0x11D40000 0x1000>; | |
777 | interrupt-parent = <&combiner>; | |
778 | interrupts = <4 0>; | |
779 | clock-names = "sysmmu", "master"; | |
780 | clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; | |
781 | #iommu-cells = <0>; | |
782 | }; | |
6cbfdd73 | 783 | |
5d99cc59 KK |
784 | sysmmu_jpeg: sysmmu@11F20000 { |
785 | compatible = "samsung,exynos-sysmmu"; | |
786 | reg = <0x11F20000 0x1000>; | |
787 | interrupt-parent = <&combiner>; | |
788 | interrupts = <4 2>; | |
789 | power-domains = <&pd_gsc>; | |
790 | clock-names = "sysmmu", "master"; | |
791 | clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; | |
792 | #iommu-cells = <0>; | |
793 | }; | |
6cbfdd73 | 794 | |
5d99cc59 KK |
795 | sysmmu_fimc_isp: sysmmu@13260000 { |
796 | compatible = "samsung,exynos-sysmmu"; | |
797 | reg = <0x13260000 0x1000>; | |
798 | interrupt-parent = <&combiner>; | |
799 | interrupts = <10 6>; | |
800 | clock-names = "sysmmu"; | |
801 | clocks = <&clock CLK_SMMU_FIMC_ISP>; | |
802 | #iommu-cells = <0>; | |
803 | }; | |
6cbfdd73 | 804 | |
5d99cc59 KK |
805 | sysmmu_fimc_drc: sysmmu@13270000 { |
806 | compatible = "samsung,exynos-sysmmu"; | |
807 | reg = <0x13270000 0x1000>; | |
808 | interrupt-parent = <&combiner>; | |
809 | interrupts = <11 6>; | |
810 | clock-names = "sysmmu"; | |
811 | clocks = <&clock CLK_SMMU_FIMC_DRC>; | |
812 | #iommu-cells = <0>; | |
813 | }; | |
6cbfdd73 | 814 | |
5d99cc59 KK |
815 | sysmmu_fimc_fd: sysmmu@132A0000 { |
816 | compatible = "samsung,exynos-sysmmu"; | |
817 | reg = <0x132A0000 0x1000>; | |
818 | interrupt-parent = <&combiner>; | |
819 | interrupts = <5 0>; | |
820 | clock-names = "sysmmu"; | |
821 | clocks = <&clock CLK_SMMU_FIMC_FD>; | |
822 | #iommu-cells = <0>; | |
823 | }; | |
6cbfdd73 | 824 | |
5d99cc59 KK |
825 | sysmmu_fimc_scc: sysmmu@13280000 { |
826 | compatible = "samsung,exynos-sysmmu"; | |
827 | reg = <0x13280000 0x1000>; | |
828 | interrupt-parent = <&combiner>; | |
829 | interrupts = <5 2>; | |
830 | clock-names = "sysmmu"; | |
831 | clocks = <&clock CLK_SMMU_FIMC_SCC>; | |
832 | #iommu-cells = <0>; | |
833 | }; | |
6cbfdd73 | 834 | |
5d99cc59 KK |
835 | sysmmu_fimc_scp: sysmmu@13290000 { |
836 | compatible = "samsung,exynos-sysmmu"; | |
837 | reg = <0x13290000 0x1000>; | |
838 | interrupt-parent = <&combiner>; | |
839 | interrupts = <3 6>; | |
840 | clock-names = "sysmmu"; | |
841 | clocks = <&clock CLK_SMMU_FIMC_SCP>; | |
842 | #iommu-cells = <0>; | |
843 | }; | |
6cbfdd73 | 844 | |
5d99cc59 KK |
845 | sysmmu_fimc_mcuctl: sysmmu@132B0000 { |
846 | compatible = "samsung,exynos-sysmmu"; | |
847 | reg = <0x132B0000 0x1000>; | |
848 | interrupt-parent = <&combiner>; | |
849 | interrupts = <5 4>; | |
850 | clock-names = "sysmmu"; | |
851 | clocks = <&clock CLK_SMMU_FIMC_MCU>; | |
852 | #iommu-cells = <0>; | |
853 | }; | |
6cbfdd73 | 854 | |
5d99cc59 KK |
855 | sysmmu_fimc_odc: sysmmu@132C0000 { |
856 | compatible = "samsung,exynos-sysmmu"; | |
857 | reg = <0x132C0000 0x1000>; | |
858 | interrupt-parent = <&combiner>; | |
859 | interrupts = <11 0>; | |
860 | clock-names = "sysmmu"; | |
861 | clocks = <&clock CLK_SMMU_FIMC_ODC>; | |
862 | #iommu-cells = <0>; | |
863 | }; | |
6cbfdd73 | 864 | |
5d99cc59 KK |
865 | sysmmu_fimc_dis0: sysmmu@132D0000 { |
866 | compatible = "samsung,exynos-sysmmu"; | |
867 | reg = <0x132D0000 0x1000>; | |
868 | interrupt-parent = <&combiner>; | |
869 | interrupts = <10 4>; | |
870 | clock-names = "sysmmu"; | |
871 | clocks = <&clock CLK_SMMU_FIMC_DIS0>; | |
872 | #iommu-cells = <0>; | |
873 | }; | |
6cbfdd73 | 874 | |
5d99cc59 KK |
875 | sysmmu_fimc_dis1: sysmmu@132E0000{ |
876 | compatible = "samsung,exynos-sysmmu"; | |
877 | reg = <0x132E0000 0x1000>; | |
878 | interrupt-parent = <&combiner>; | |
879 | interrupts = <9 4>; | |
880 | clock-names = "sysmmu"; | |
881 | clocks = <&clock CLK_SMMU_FIMC_DIS1>; | |
882 | #iommu-cells = <0>; | |
883 | }; | |
6cbfdd73 | 884 | |
5d99cc59 KK |
885 | sysmmu_fimc_3dnr: sysmmu@132F0000 { |
886 | compatible = "samsung,exynos-sysmmu"; | |
887 | reg = <0x132F0000 0x1000>; | |
888 | interrupt-parent = <&combiner>; | |
889 | interrupts = <5 6>; | |
890 | clock-names = "sysmmu"; | |
891 | clocks = <&clock CLK_SMMU_FIMC_3DNR>; | |
892 | #iommu-cells = <0>; | |
893 | }; | |
6cbfdd73 | 894 | |
5d99cc59 KK |
895 | sysmmu_fimc_lite0: sysmmu@13C40000 { |
896 | compatible = "samsung,exynos-sysmmu"; | |
897 | reg = <0x13C40000 0x1000>; | |
898 | interrupt-parent = <&combiner>; | |
899 | interrupts = <3 4>; | |
900 | power-domains = <&pd_gsc>; | |
901 | clock-names = "sysmmu", "master"; | |
902 | clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; | |
903 | #iommu-cells = <0>; | |
904 | }; | |
6cbfdd73 | 905 | |
5d99cc59 KK |
906 | sysmmu_fimc_lite1: sysmmu@13C50000 { |
907 | compatible = "samsung,exynos-sysmmu"; | |
908 | reg = <0x13C50000 0x1000>; | |
909 | interrupt-parent = <&combiner>; | |
910 | interrupts = <24 1>; | |
911 | power-domains = <&pd_gsc>; | |
912 | clock-names = "sysmmu", "master"; | |
913 | clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; | |
914 | #iommu-cells = <0>; | |
915 | }; | |
6cbfdd73 | 916 | |
5d99cc59 KK |
917 | sysmmu_gsc0: sysmmu@13E80000 { |
918 | compatible = "samsung,exynos-sysmmu"; | |
919 | reg = <0x13E80000 0x1000>; | |
920 | interrupt-parent = <&combiner>; | |
921 | interrupts = <2 0>; | |
922 | power-domains = <&pd_gsc>; | |
923 | clock-names = "sysmmu", "master"; | |
924 | clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; | |
925 | #iommu-cells = <0>; | |
926 | }; | |
6cbfdd73 | 927 | |
5d99cc59 KK |
928 | sysmmu_gsc1: sysmmu@13E90000 { |
929 | compatible = "samsung,exynos-sysmmu"; | |
930 | reg = <0x13E90000 0x1000>; | |
931 | interrupt-parent = <&combiner>; | |
932 | interrupts = <2 2>; | |
933 | power-domains = <&pd_gsc>; | |
934 | clock-names = "sysmmu", "master"; | |
935 | clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; | |
936 | #iommu-cells = <0>; | |
937 | }; | |
6cbfdd73 | 938 | |
5d99cc59 KK |
939 | sysmmu_gsc2: sysmmu@13EA0000 { |
940 | compatible = "samsung,exynos-sysmmu"; | |
941 | reg = <0x13EA0000 0x1000>; | |
942 | interrupt-parent = <&combiner>; | |
943 | interrupts = <2 4>; | |
944 | power-domains = <&pd_gsc>; | |
945 | clock-names = "sysmmu", "master"; | |
946 | clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; | |
947 | #iommu-cells = <0>; | |
948 | }; | |
6cbfdd73 | 949 | |
5d99cc59 KK |
950 | sysmmu_gsc3: sysmmu@13EB0000 { |
951 | compatible = "samsung,exynos-sysmmu"; | |
952 | reg = <0x13EB0000 0x1000>; | |
953 | interrupt-parent = <&combiner>; | |
954 | interrupts = <2 6>; | |
955 | power-domains = <&pd_gsc>; | |
956 | clock-names = "sysmmu", "master"; | |
957 | clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; | |
958 | #iommu-cells = <0>; | |
959 | }; | |
6cbfdd73 | 960 | |
5d99cc59 KK |
961 | sysmmu_fimd1: sysmmu@14640000 { |
962 | compatible = "samsung,exynos-sysmmu"; | |
963 | reg = <0x14640000 0x1000>; | |
964 | interrupt-parent = <&combiner>; | |
965 | interrupts = <3 2>; | |
966 | power-domains = <&pd_disp1>; | |
967 | clock-names = "sysmmu", "master"; | |
968 | clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; | |
969 | #iommu-cells = <0>; | |
970 | }; | |
6cbfdd73 | 971 | |
5d99cc59 KK |
972 | sysmmu_tv: sysmmu@14650000 { |
973 | compatible = "samsung,exynos-sysmmu"; | |
974 | reg = <0x14650000 0x1000>; | |
975 | interrupt-parent = <&combiner>; | |
976 | interrupts = <7 4>; | |
977 | power-domains = <&pd_disp1>; | |
978 | clock-names = "sysmmu", "master"; | |
979 | clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; | |
980 | #iommu-cells = <0>; | |
981 | }; | |
6cbfdd73 MS |
982 | }; |
983 | ||
5d99cc59 KK |
984 | thermal-zones { |
985 | cpu_thermal: cpu-thermal { | |
986 | polling-delay-passive = <0>; | |
987 | polling-delay = <0>; | |
988 | thermal-sensors = <&tmu 0>; | |
6cbfdd73 | 989 | |
5d99cc59 KK |
990 | cooling-maps { |
991 | map0 { | |
992 | /* Corresponds to 800MHz at freq_table */ | |
993 | cooling-device = <&cpu0 9 9>; | |
994 | }; | |
995 | map1 { | |
996 | /* Corresponds to 200MHz at freq_table */ | |
997 | cooling-device = <&cpu0 15 15>; | |
998 | }; | |
999 | }; | |
1000 | }; | |
6cbfdd73 | 1001 | }; |
b074abb7 | 1002 | }; |
e9a2f409 KK |
1003 | |
1004 | &dp { | |
1005 | power-domains = <&pd_disp1>; | |
1006 | clocks = <&clock CLK_DP>; | |
1007 | clock-names = "dp"; | |
1008 | phys = <&dp_phy>; | |
1009 | phy-names = "dp"; | |
1010 | }; | |
1011 | ||
1012 | &fimd { | |
1013 | power-domains = <&pd_disp1>; | |
1014 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; | |
1015 | clock-names = "sclk_fimd", "fimd"; | |
6cbfdd73 | 1016 | iommus = <&sysmmu_fimd1>; |
e9a2f409 KK |
1017 | }; |
1018 | ||
5a124fe0 KK |
1019 | &i2c_0 { |
1020 | clocks = <&clock CLK_I2C0>; | |
1021 | clock-names = "i2c"; | |
1022 | pinctrl-names = "default"; | |
1023 | pinctrl-0 = <&i2c0_bus>; | |
1024 | }; | |
1025 | ||
1026 | &i2c_1 { | |
1027 | clocks = <&clock CLK_I2C1>; | |
1028 | clock-names = "i2c"; | |
1029 | pinctrl-names = "default"; | |
1030 | pinctrl-0 = <&i2c1_bus>; | |
1031 | }; | |
1032 | ||
1033 | &i2c_2 { | |
1034 | clocks = <&clock CLK_I2C2>; | |
1035 | clock-names = "i2c"; | |
1036 | pinctrl-names = "default"; | |
1037 | pinctrl-0 = <&i2c2_bus>; | |
1038 | }; | |
1039 | ||
1040 | &i2c_3 { | |
1041 | clocks = <&clock CLK_I2C3>; | |
1042 | clock-names = "i2c"; | |
1043 | pinctrl-names = "default"; | |
1044 | pinctrl-0 = <&i2c3_bus>; | |
1045 | }; | |
1046 | ||
1047 | &pwm { | |
1048 | clocks = <&clock CLK_PWM>; | |
1049 | clock-names = "timers"; | |
1050 | }; | |
1051 | ||
e9a2f409 KK |
1052 | &rtc { |
1053 | clocks = <&clock CLK_RTC>; | |
1054 | clock-names = "rtc"; | |
1055 | interrupt-parent = <&pmu_system_controller>; | |
1056 | status = "disabled"; | |
1057 | }; | |
1058 | ||
1059 | &serial_0 { | |
1060 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; | |
1061 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
1062 | dmas = <&pdma0 13>, <&pdma0 14>; |
1063 | dma-names = "rx", "tx"; | |
e9a2f409 KK |
1064 | }; |
1065 | ||
1066 | &serial_1 { | |
1067 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; | |
1068 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
1069 | dmas = <&pdma1 15>, <&pdma1 16>; |
1070 | dma-names = "rx", "tx"; | |
e9a2f409 KK |
1071 | }; |
1072 | ||
1073 | &serial_2 { | |
1074 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; | |
1075 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
1076 | dmas = <&pdma0 15>, <&pdma0 16>; |
1077 | dma-names = "rx", "tx"; | |
e9a2f409 KK |
1078 | }; |
1079 | ||
1080 | &serial_3 { | |
1081 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; | |
1082 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
1083 | dmas = <&pdma1 17>, <&pdma1 18>; |
1084 | dma-names = "rx", "tx"; | |
e9a2f409 | 1085 | }; |
dc561797 JMC |
1086 | |
1087 | #include "exynos5250-pinctrl.dtsi" |