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b074abb7 KK |
1 | /* |
2 | * SAMSUNG EXYNOS5250 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. | |
8 | * EXYNOS5250 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, | |
13 | * additional nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
fe273c3e | 20 | #include <dt-bindings/clock/exynos5250.h> |
e6c21cba | 21 | #include "exynos5.dtsi" |
3799279f | 22 | #include "exynos5250-pinctrl.dtsi" |
9843a223 | 23 | #include "exynos4-cpu-thermal.dtsi" |
602408e3 | 24 | #include <dt-bindings/clock/exynos-audss-clk.h> |
b074abb7 KK |
25 | |
26 | / { | |
8bdb31b4 | 27 | compatible = "samsung,exynos5250", "samsung,exynos5"; |
b074abb7 | 28 | |
79989ba3 TA |
29 | aliases { |
30 | spi0 = &spi_0; | |
31 | spi1 = &spi_1; | |
32 | spi2 = &spi_2; | |
1128658a SAB |
33 | gsc0 = &gsc_0; |
34 | gsc1 = &gsc_1; | |
35 | gsc2 = &gsc_2; | |
36 | gsc3 = &gsc_3; | |
c8149df0 YK |
37 | mshc0 = &mmc_0; |
38 | mshc1 = &mmc_1; | |
39 | mshc2 = &mmc_2; | |
40 | mshc3 = &mmc_3; | |
b9fa3e7b AK |
41 | i2c0 = &i2c_0; |
42 | i2c1 = &i2c_1; | |
43 | i2c2 = &i2c_2; | |
44 | i2c3 = &i2c_3; | |
45 | i2c4 = &i2c_4; | |
46 | i2c5 = &i2c_5; | |
47 | i2c6 = &i2c_6; | |
48 | i2c7 = &i2c_7; | |
49 | i2c8 = &i2c_8; | |
ba0d7ed3 | 50 | i2c9 = &i2c_9; |
f8bfe2b0 TA |
51 | pinctrl0 = &pinctrl_0; |
52 | pinctrl1 = &pinctrl_1; | |
53 | pinctrl2 = &pinctrl_2; | |
54 | pinctrl3 = &pinctrl_3; | |
79989ba3 TA |
55 | }; |
56 | ||
1897d2f3 CK |
57 | cpus { |
58 | #address-cells = <1>; | |
59 | #size-cells = <0>; | |
60 | ||
bf4a0bed | 61 | cpu0: cpu@0 { |
1897d2f3 CK |
62 | device_type = "cpu"; |
63 | compatible = "arm,cortex-a15"; | |
64 | reg = <0>; | |
0da80563 | 65 | clock-frequency = <1700000000>; |
bf4a0bed LM |
66 | cooling-min-level = <15>; |
67 | cooling-max-level = <9>; | |
68 | #cooling-cells = <2>; /* min followed by max */ | |
1897d2f3 CK |
69 | }; |
70 | cpu@1 { | |
71 | device_type = "cpu"; | |
72 | compatible = "arm,cortex-a15"; | |
73 | reg = <1>; | |
0da80563 | 74 | clock-frequency = <1700000000>; |
1897d2f3 | 75 | }; |
79989ba3 TA |
76 | }; |
77 | ||
b3205dea SK |
78 | sysram@02020000 { |
79 | compatible = "mmio-sram"; | |
80 | reg = <0x02020000 0x30000>; | |
81 | #address-cells = <1>; | |
82 | #size-cells = <1>; | |
83 | ranges = <0 0x02020000 0x30000>; | |
84 | ||
85 | smp-sysram@0 { | |
86 | compatible = "samsung,exynos4210-sysram"; | |
87 | reg = <0x0 0x1000>; | |
88 | }; | |
89 | ||
90 | smp-sysram@2f000 { | |
91 | compatible = "samsung,exynos4210-sysram-ns"; | |
92 | reg = <0x2f000 0x1000>; | |
93 | }; | |
94 | }; | |
95 | ||
c31f566d | 96 | pd_gsc: gsc-power-domain@10044000 { |
6f9e95e6 PK |
97 | compatible = "samsung,exynos4210-pd"; |
98 | reg = <0x10044000 0x20>; | |
0da65870 | 99 | #power-domain-cells = <0>; |
6f9e95e6 PK |
100 | }; |
101 | ||
c31f566d | 102 | pd_mfc: mfc-power-domain@10044040 { |
6f9e95e6 PK |
103 | compatible = "samsung,exynos4210-pd"; |
104 | reg = <0x10044040 0x20>; | |
0da65870 | 105 | #power-domain-cells = <0>; |
6f9e95e6 PK |
106 | }; |
107 | ||
c31f566d | 108 | clock: clock-controller@10010000 { |
d8bafc87 TA |
109 | compatible = "samsung,exynos5250-clock"; |
110 | reg = <0x10010000 0x30000>; | |
111 | #clock-cells = <1>; | |
112 | }; | |
113 | ||
bba23d95 PV |
114 | clock_audss: audss-clock-controller@3810000 { |
115 | compatible = "samsung,exynos5250-audss-clock"; | |
116 | reg = <0x03810000 0x0C>; | |
117 | #clock-cells = <1>; | |
fe273c3e AH |
118 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, |
119 | <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; | |
c08ceea3 | 120 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
bba23d95 PV |
121 | }; |
122 | ||
2b7da988 AG |
123 | timer { |
124 | compatible = "arm,armv7-timer"; | |
125 | interrupts = <1 13 0xf08>, | |
126 | <1 14 0xf08>, | |
127 | <1 11 0xf08>, | |
128 | <1 10 0xf08>; | |
4d594dd3 YK |
129 | /* Unfortunately we need this since some versions of U-Boot |
130 | * on Exynos don't set the CNTFRQ register, so we need the | |
131 | * value from DT. | |
132 | */ | |
133 | clock-frequency = <24000000>; | |
b074abb7 KK |
134 | }; |
135 | ||
bbd9700a TA |
136 | mct@101C0000 { |
137 | compatible = "samsung,exynos4210-mct"; | |
138 | reg = <0x101C0000 0x800>; | |
139 | interrupt-controller; | |
140 | #interrups-cells = <2>; | |
141 | interrupt-parent = <&mct_map>; | |
142 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | |
143 | <4 0>, <5 0>; | |
fe273c3e | 144 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
2de6847c | 145 | clock-names = "fin_pll", "mct"; |
bbd9700a TA |
146 | |
147 | mct_map: mct-map { | |
148 | #interrupt-cells = <2>; | |
149 | #address-cells = <0>; | |
150 | #size-cells = <0>; | |
151 | interrupt-map = <0x0 0 &combiner 23 3>, | |
152 | <0x1 0 &combiner 23 4>, | |
153 | <0x2 0 &combiner 25 2>, | |
154 | <0x3 0 &combiner 25 3>, | |
155 | <0x4 0 &gic 0 120 0>, | |
156 | <0x5 0 &gic 0 121 0>; | |
157 | }; | |
158 | }; | |
159 | ||
4f801e59 CP |
160 | pmu { |
161 | compatible = "arm,cortex-a15-pmu"; | |
162 | interrupt-parent = <&combiner>; | |
163 | interrupts = <1 2>, <22 4>; | |
164 | }; | |
165 | ||
f8bfe2b0 TA |
166 | pinctrl_0: pinctrl@11400000 { |
167 | compatible = "samsung,exynos5250-pinctrl"; | |
168 | reg = <0x11400000 0x1000>; | |
169 | interrupts = <0 46 0>; | |
170 | ||
171 | wakup_eint: wakeup-interrupt-controller { | |
172 | compatible = "samsung,exynos4210-wakeup-eint"; | |
173 | interrupt-parent = <&gic>; | |
174 | interrupts = <0 32 0>; | |
175 | }; | |
176 | }; | |
177 | ||
178 | pinctrl_1: pinctrl@13400000 { | |
179 | compatible = "samsung,exynos5250-pinctrl"; | |
180 | reg = <0x13400000 0x1000>; | |
181 | interrupts = <0 45 0>; | |
182 | }; | |
183 | ||
184 | pinctrl_2: pinctrl@10d10000 { | |
185 | compatible = "samsung,exynos5250-pinctrl"; | |
186 | reg = <0x10d10000 0x1000>; | |
187 | interrupts = <0 50 0>; | |
188 | }; | |
189 | ||
0abb6aea | 190 | pinctrl_3: pinctrl@03860000 { |
f8bfe2b0 | 191 | compatible = "samsung,exynos5250-pinctrl"; |
0abb6aea | 192 | reg = <0x03860000 0x1000>; |
f8bfe2b0 TA |
193 | interrupts = <0 47 0>; |
194 | }; | |
195 | ||
c680036a LKA |
196 | pmu_system_controller: system-controller@10040000 { |
197 | compatible = "samsung,exynos5250-pmu", "syscon"; | |
198 | reg = <0x10040000 0x5000>; | |
d19bb397 TF |
199 | clock-names = "clkout16"; |
200 | clocks = <&clock CLK_FIN_PLL>; | |
201 | #clock-cells = <1>; | |
c680036a LKA |
202 | }; |
203 | ||
dfbbdbf4 VG |
204 | sysreg_system_controller: syscon@10050000 { |
205 | compatible = "samsung,exynos5-sysreg", "syscon"; | |
206 | reg = <0x10050000 0x5000>; | |
207 | }; | |
208 | ||
1d287620 LKA |
209 | watchdog@101D0000 { |
210 | compatible = "samsung,exynos5250-wdt"; | |
211 | reg = <0x101D0000 0x100>; | |
212 | interrupts = <0 42 0>; | |
fe273c3e | 213 | clocks = <&clock CLK_WDT>; |
2de6847c | 214 | clock-names = "watchdog"; |
1d287620 | 215 | samsung,syscon-phandle = <&pmu_system_controller>; |
b074abb7 KK |
216 | }; |
217 | ||
21aa5217 SK |
218 | g2d@10850000 { |
219 | compatible = "samsung,exynos5250-g2d"; | |
220 | reg = <0x10850000 0x1000>; | |
221 | interrupts = <0 91 0>; | |
fe273c3e | 222 | clocks = <&clock CLK_G2D>; |
21aa5217 SK |
223 | clock-names = "fimg2d"; |
224 | }; | |
225 | ||
19fd45bf | 226 | mfc: codec@11000000 { |
2eae613b AK |
227 | compatible = "samsung,mfc-v6"; |
228 | reg = <0x11000000 0x10000>; | |
229 | interrupts = <0 96 0>; | |
0da65870 | 230 | power-domains = <&pd_mfc>; |
fe273c3e | 231 | clocks = <&clock CLK_MFC>; |
8b6bea33 | 232 | clock-names = "mfc"; |
2eae613b AK |
233 | }; |
234 | ||
19fd45bf | 235 | rtc: rtc@101E0000 { |
fe273c3e | 236 | clocks = <&clock CLK_RTC>; |
2de6847c | 237 | clock-names = "rtc"; |
65cedf0e | 238 | status = "disabled"; |
b074abb7 KK |
239 | }; |
240 | ||
9843a223 | 241 | tmu: tmu@10060000 { |
ef405e04 ADK |
242 | compatible = "samsung,exynos5250-tmu"; |
243 | reg = <0x10060000 0x100>; | |
244 | interrupts = <0 65 0>; | |
fe273c3e | 245 | clocks = <&clock CLK_TMU>; |
2de6847c | 246 | clock-names = "tmu_apbif"; |
9843a223 | 247 | #include "exynos4412-tmu-sensor-conf.dtsi" |
ef405e04 ADK |
248 | }; |
249 | ||
bf4a0bed LM |
250 | thermal-zones { |
251 | cpu_thermal: cpu-thermal { | |
9843a223 LM |
252 | polling-delay-passive = <0>; |
253 | polling-delay = <0>; | |
254 | thermal-sensors = <&tmu 0>; | |
255 | ||
bf4a0bed LM |
256 | cooling-maps { |
257 | map0 { | |
258 | /* Corresponds to 800MHz at freq_table */ | |
259 | cooling-device = <&cpu0 9 9>; | |
260 | }; | |
261 | map1 { | |
262 | /* Corresponds to 200MHz at freq_table */ | |
263 | cooling-device = <&cpu0 15 15>; | |
264 | }; | |
265 | }; | |
266 | }; | |
267 | }; | |
268 | ||
b074abb7 | 269 | serial@12C00000 { |
fe273c3e | 270 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
2de6847c | 271 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
272 | }; |
273 | ||
274 | serial@12C10000 { | |
fe273c3e | 275 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
2de6847c | 276 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
277 | }; |
278 | ||
279 | serial@12C20000 { | |
fe273c3e | 280 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
2de6847c | 281 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
282 | }; |
283 | ||
284 | serial@12C30000 { | |
fe273c3e | 285 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
2de6847c | 286 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
287 | }; |
288 | ||
19fd45bf | 289 | sata: sata@122F0000 { |
ba0d7ed3 YK |
290 | compatible = "snps,dwc-ahci"; |
291 | samsung,sata-freq = <66>; | |
c47d244a VA |
292 | reg = <0x122F0000 0x1ff>; |
293 | interrupts = <0 115 0>; | |
fe273c3e | 294 | clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; |
2de6847c | 295 | clock-names = "sata", "sclk_sata"; |
ba0d7ed3 YK |
296 | phys = <&sata_phy>; |
297 | phy-names = "sata-phy"; | |
298 | status = "disabled"; | |
c47d244a VA |
299 | }; |
300 | ||
ba0d7ed3 YK |
301 | sata_phy: sata-phy@12170000 { |
302 | compatible = "samsung,exynos5250-sata-phy"; | |
c47d244a | 303 | reg = <0x12170000 0x1ff>; |
e06e1067 | 304 | clocks = <&clock CLK_SATA_PHYCTRL>; |
ba0d7ed3 YK |
305 | clock-names = "sata_phyctrl"; |
306 | #phy-cells = <0>; | |
307 | samsung,syscon-phandle = <&pmu_system_controller>; | |
308 | status = "disabled"; | |
c47d244a VA |
309 | }; |
310 | ||
b9fa3e7b | 311 | i2c_0: i2c@12C60000 { |
b074abb7 KK |
312 | compatible = "samsung,s3c2440-i2c"; |
313 | reg = <0x12C60000 0x100>; | |
314 | interrupts = <0 56 0>; | |
009f7c9f TA |
315 | #address-cells = <1>; |
316 | #size-cells = <0>; | |
fe273c3e | 317 | clocks = <&clock CLK_I2C0>; |
2de6847c | 318 | clock-names = "i2c"; |
f8bfe2b0 TA |
319 | pinctrl-names = "default"; |
320 | pinctrl-0 = <&i2c0_bus>; | |
1888eb75 | 321 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 322 | status = "disabled"; |
b074abb7 KK |
323 | }; |
324 | ||
b9fa3e7b | 325 | i2c_1: i2c@12C70000 { |
b074abb7 KK |
326 | compatible = "samsung,s3c2440-i2c"; |
327 | reg = <0x12C70000 0x100>; | |
328 | interrupts = <0 57 0>; | |
009f7c9f TA |
329 | #address-cells = <1>; |
330 | #size-cells = <0>; | |
fe273c3e | 331 | clocks = <&clock CLK_I2C1>; |
2de6847c | 332 | clock-names = "i2c"; |
f8bfe2b0 TA |
333 | pinctrl-names = "default"; |
334 | pinctrl-0 = <&i2c1_bus>; | |
1888eb75 | 335 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 336 | status = "disabled"; |
b074abb7 KK |
337 | }; |
338 | ||
b9fa3e7b | 339 | i2c_2: i2c@12C80000 { |
b074abb7 KK |
340 | compatible = "samsung,s3c2440-i2c"; |
341 | reg = <0x12C80000 0x100>; | |
342 | interrupts = <0 58 0>; | |
009f7c9f TA |
343 | #address-cells = <1>; |
344 | #size-cells = <0>; | |
fe273c3e | 345 | clocks = <&clock CLK_I2C2>; |
2de6847c | 346 | clock-names = "i2c"; |
f8bfe2b0 TA |
347 | pinctrl-names = "default"; |
348 | pinctrl-0 = <&i2c2_bus>; | |
1888eb75 | 349 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 350 | status = "disabled"; |
b074abb7 KK |
351 | }; |
352 | ||
b9fa3e7b | 353 | i2c_3: i2c@12C90000 { |
b074abb7 KK |
354 | compatible = "samsung,s3c2440-i2c"; |
355 | reg = <0x12C90000 0x100>; | |
356 | interrupts = <0 59 0>; | |
009f7c9f TA |
357 | #address-cells = <1>; |
358 | #size-cells = <0>; | |
fe273c3e | 359 | clocks = <&clock CLK_I2C3>; |
2de6847c | 360 | clock-names = "i2c"; |
f8bfe2b0 TA |
361 | pinctrl-names = "default"; |
362 | pinctrl-0 = <&i2c3_bus>; | |
1888eb75 | 363 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 364 | status = "disabled"; |
b074abb7 KK |
365 | }; |
366 | ||
b9fa3e7b | 367 | i2c_4: i2c@12CA0000 { |
b074abb7 KK |
368 | compatible = "samsung,s3c2440-i2c"; |
369 | reg = <0x12CA0000 0x100>; | |
370 | interrupts = <0 60 0>; | |
009f7c9f TA |
371 | #address-cells = <1>; |
372 | #size-cells = <0>; | |
fe273c3e | 373 | clocks = <&clock CLK_I2C4>; |
2de6847c | 374 | clock-names = "i2c"; |
f8bfe2b0 TA |
375 | pinctrl-names = "default"; |
376 | pinctrl-0 = <&i2c4_bus>; | |
6ad8ebff | 377 | status = "disabled"; |
b074abb7 KK |
378 | }; |
379 | ||
b9fa3e7b | 380 | i2c_5: i2c@12CB0000 { |
b074abb7 KK |
381 | compatible = "samsung,s3c2440-i2c"; |
382 | reg = <0x12CB0000 0x100>; | |
383 | interrupts = <0 61 0>; | |
009f7c9f TA |
384 | #address-cells = <1>; |
385 | #size-cells = <0>; | |
fe273c3e | 386 | clocks = <&clock CLK_I2C5>; |
2de6847c | 387 | clock-names = "i2c"; |
f8bfe2b0 TA |
388 | pinctrl-names = "default"; |
389 | pinctrl-0 = <&i2c5_bus>; | |
6ad8ebff | 390 | status = "disabled"; |
b074abb7 KK |
391 | }; |
392 | ||
b9fa3e7b | 393 | i2c_6: i2c@12CC0000 { |
b074abb7 KK |
394 | compatible = "samsung,s3c2440-i2c"; |
395 | reg = <0x12CC0000 0x100>; | |
396 | interrupts = <0 62 0>; | |
009f7c9f TA |
397 | #address-cells = <1>; |
398 | #size-cells = <0>; | |
fe273c3e | 399 | clocks = <&clock CLK_I2C6>; |
2de6847c | 400 | clock-names = "i2c"; |
f8bfe2b0 TA |
401 | pinctrl-names = "default"; |
402 | pinctrl-0 = <&i2c6_bus>; | |
6ad8ebff | 403 | status = "disabled"; |
b074abb7 KK |
404 | }; |
405 | ||
b9fa3e7b | 406 | i2c_7: i2c@12CD0000 { |
b074abb7 KK |
407 | compatible = "samsung,s3c2440-i2c"; |
408 | reg = <0x12CD0000 0x100>; | |
409 | interrupts = <0 63 0>; | |
009f7c9f TA |
410 | #address-cells = <1>; |
411 | #size-cells = <0>; | |
fe273c3e | 412 | clocks = <&clock CLK_I2C7>; |
2de6847c | 413 | clock-names = "i2c"; |
f8bfe2b0 TA |
414 | pinctrl-names = "default"; |
415 | pinctrl-0 = <&i2c7_bus>; | |
6ad8ebff | 416 | status = "disabled"; |
3e3e9ce4 RS |
417 | }; |
418 | ||
b9fa3e7b | 419 | i2c_8: i2c@12CE0000 { |
3e3e9ce4 RS |
420 | compatible = "samsung,s3c2440-hdmiphy-i2c"; |
421 | reg = <0x12CE0000 0x1000>; | |
422 | interrupts = <0 64 0>; | |
423 | #address-cells = <1>; | |
424 | #size-cells = <0>; | |
fe273c3e | 425 | clocks = <&clock CLK_I2C_HDMI>; |
2de6847c | 426 | clock-names = "i2c"; |
6ad8ebff | 427 | status = "disabled"; |
24025f6f OJ |
428 | }; |
429 | ||
ba0d7ed3 | 430 | i2c_9: i2c@121D0000 { |
c47d244a VA |
431 | compatible = "samsung,exynos5-sata-phy-i2c"; |
432 | reg = <0x121D0000 0x100>; | |
433 | #address-cells = <1>; | |
434 | #size-cells = <0>; | |
fe273c3e | 435 | clocks = <&clock CLK_SATA_PHYI2C>; |
2de6847c | 436 | clock-names = "i2c"; |
6ad8ebff | 437 | status = "disabled"; |
b074abb7 KK |
438 | }; |
439 | ||
79989ba3 TA |
440 | spi_0: spi@12d20000 { |
441 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 442 | status = "disabled"; |
79989ba3 TA |
443 | reg = <0x12d20000 0x100>; |
444 | interrupts = <0 66 0>; | |
a4a8a9d3 PV |
445 | dmas = <&pdma0 5 |
446 | &pdma0 4>; | |
447 | dma-names = "tx", "rx"; | |
79989ba3 TA |
448 | #address-cells = <1>; |
449 | #size-cells = <0>; | |
fe273c3e | 450 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
2de6847c | 451 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
452 | pinctrl-names = "default"; |
453 | pinctrl-0 = <&spi0_bus>; | |
79989ba3 TA |
454 | }; |
455 | ||
456 | spi_1: spi@12d30000 { | |
457 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 458 | status = "disabled"; |
79989ba3 TA |
459 | reg = <0x12d30000 0x100>; |
460 | interrupts = <0 67 0>; | |
a4a8a9d3 PV |
461 | dmas = <&pdma1 5 |
462 | &pdma1 4>; | |
463 | dma-names = "tx", "rx"; | |
79989ba3 TA |
464 | #address-cells = <1>; |
465 | #size-cells = <0>; | |
fe273c3e | 466 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
2de6847c | 467 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
468 | pinctrl-names = "default"; |
469 | pinctrl-0 = <&spi1_bus>; | |
79989ba3 TA |
470 | }; |
471 | ||
472 | spi_2: spi@12d40000 { | |
473 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 474 | status = "disabled"; |
79989ba3 TA |
475 | reg = <0x12d40000 0x100>; |
476 | interrupts = <0 68 0>; | |
a4a8a9d3 PV |
477 | dmas = <&pdma0 7 |
478 | &pdma0 6>; | |
479 | dma-names = "tx", "rx"; | |
79989ba3 TA |
480 | #address-cells = <1>; |
481 | #size-cells = <0>; | |
fe273c3e | 482 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
2de6847c | 483 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
484 | pinctrl-names = "default"; |
485 | pinctrl-0 = <&spi2_bus>; | |
79989ba3 TA |
486 | }; |
487 | ||
c8149df0 | 488 | mmc_0: mmc@12200000 { |
906fd84e YK |
489 | compatible = "samsung,exynos5250-dw-mshc"; |
490 | interrupts = <0 75 0>; | |
491 | #address-cells = <1>; | |
492 | #size-cells = <0>; | |
84bd48a0 | 493 | reg = <0x12200000 0x1000>; |
fe273c3e | 494 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; |
2de6847c | 495 | clock-names = "biu", "ciu"; |
46285a90 | 496 | fifo-depth = <0x80>; |
e908d5c5 | 497 | status = "disabled"; |
84bd48a0 TA |
498 | }; |
499 | ||
c8149df0 | 500 | mmc_1: mmc@12210000 { |
906fd84e YK |
501 | compatible = "samsung,exynos5250-dw-mshc"; |
502 | interrupts = <0 76 0>; | |
503 | #address-cells = <1>; | |
504 | #size-cells = <0>; | |
84bd48a0 | 505 | reg = <0x12210000 0x1000>; |
fe273c3e | 506 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; |
2de6847c | 507 | clock-names = "biu", "ciu"; |
46285a90 | 508 | fifo-depth = <0x80>; |
e908d5c5 | 509 | status = "disabled"; |
84bd48a0 TA |
510 | }; |
511 | ||
c8149df0 | 512 | mmc_2: mmc@12220000 { |
906fd84e YK |
513 | compatible = "samsung,exynos5250-dw-mshc"; |
514 | interrupts = <0 77 0>; | |
515 | #address-cells = <1>; | |
516 | #size-cells = <0>; | |
84bd48a0 | 517 | reg = <0x12220000 0x1000>; |
fe273c3e | 518 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; |
2de6847c | 519 | clock-names = "biu", "ciu"; |
46285a90 | 520 | fifo-depth = <0x80>; |
e908d5c5 | 521 | status = "disabled"; |
84bd48a0 TA |
522 | }; |
523 | ||
c8149df0 | 524 | mmc_3: mmc@12230000 { |
84bd48a0 TA |
525 | compatible = "samsung,exynos5250-dw-mshc"; |
526 | reg = <0x12230000 0x1000>; | |
527 | interrupts = <0 78 0>; | |
528 | #address-cells = <1>; | |
529 | #size-cells = <0>; | |
fe273c3e | 530 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; |
2de6847c | 531 | clock-names = "biu", "ciu"; |
46285a90 | 532 | fifo-depth = <0x80>; |
e908d5c5 | 533 | status = "disabled"; |
84bd48a0 TA |
534 | }; |
535 | ||
28a48058 | 536 | i2s0: i2s@03830000 { |
64183656 | 537 | compatible = "samsung,s5pv210-i2s"; |
328aee4b | 538 | status = "disabled"; |
a0b5f81e | 539 | reg = <0x03830000 0x100>; |
4c4c7463 PV |
540 | dmas = <&pdma0 10 |
541 | &pdma0 9 | |
542 | &pdma0 8>; | |
543 | dma-names = "tx", "rx", "tx-sec"; | |
916ec47e PV |
544 | clocks = <&clock_audss EXYNOS_I2S_BUS>, |
545 | <&clock_audss EXYNOS_I2S_BUS>, | |
546 | <&clock_audss EXYNOS_SCLK_I2S>; | |
547 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
a0b5f81e | 548 | samsung,idma-addr = <0x03000000>; |
f8bfe2b0 TA |
549 | pinctrl-names = "default"; |
550 | pinctrl-0 = <&i2s0_bus>; | |
4c4c7463 PV |
551 | }; |
552 | ||
28a48058 | 553 | i2s1: i2s@12D60000 { |
64183656 | 554 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 555 | status = "disabled"; |
a0b5f81e MB |
556 | reg = <0x12D60000 0x100>; |
557 | dmas = <&pdma1 12 | |
558 | &pdma1 11>; | |
559 | dma-names = "tx", "rx"; | |
fe273c3e | 560 | clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; |
916ec47e | 561 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
562 | pinctrl-names = "default"; |
563 | pinctrl-0 = <&i2s1_bus>; | |
4c4c7463 PV |
564 | }; |
565 | ||
28a48058 | 566 | i2s2: i2s@12D70000 { |
64183656 | 567 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 568 | status = "disabled"; |
a0b5f81e MB |
569 | reg = <0x12D70000 0x100>; |
570 | dmas = <&pdma0 12 | |
571 | &pdma0 11>; | |
572 | dma-names = "tx", "rx"; | |
fe273c3e | 573 | clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; |
916ec47e | 574 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
575 | pinctrl-names = "default"; |
576 | pinctrl-0 = <&i2s2_bus>; | |
4c4c7463 PV |
577 | }; |
578 | ||
0b3dc97e VG |
579 | usb@12000000 { |
580 | compatible = "samsung,exynos5250-dwusb3"; | |
fe273c3e | 581 | clocks = <&clock CLK_USB3>; |
0b3dc97e VG |
582 | clock-names = "usbdrd30"; |
583 | #address-cells = <1>; | |
584 | #size-cells = <1>; | |
585 | ranges; | |
586 | ||
0526f276 | 587 | usbdrd_dwc3: dwc3 { |
0b3dc97e VG |
588 | compatible = "synopsys,dwc3"; |
589 | reg = <0x12000000 0x10000>; | |
590 | interrupts = <0 72 0>; | |
7a4cf0fd VG |
591 | phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; |
592 | phy-names = "usb2-phy", "usb3-phy"; | |
896db3b3 VG |
593 | }; |
594 | }; | |
595 | ||
517083f4 VG |
596 | usbdrd_phy: phy@12100000 { |
597 | compatible = "samsung,exynos5250-usbdrd-phy"; | |
598 | reg = <0x12100000 0x100>; | |
599 | clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; | |
600 | clock-names = "phy", "ref"; | |
601 | samsung,pmu-syscon = <&pmu_system_controller>; | |
602 | #phy-cells = <1>; | |
603 | }; | |
604 | ||
19fd45bf | 605 | ehci: usb@12110000 { |
13cbd1e3 VG |
606 | compatible = "samsung,exynos4210-ehci"; |
607 | reg = <0x12110000 0x100>; | |
608 | interrupts = <0 71 0>; | |
b3cd7d87 | 609 | |
fe273c3e | 610 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 611 | clock-names = "usbhost"; |
dba2f058 KD |
612 | #address-cells = <1>; |
613 | #size-cells = <0>; | |
614 | port@0 { | |
615 | reg = <0>; | |
616 | phys = <&usb2_phy_gen 1>; | |
617 | }; | |
13cbd1e3 VG |
618 | }; |
619 | ||
19fd45bf | 620 | ohci: usb@12120000 { |
7d40d867 VG |
621 | compatible = "samsung,exynos4210-ohci"; |
622 | reg = <0x12120000 0x100>; | |
623 | interrupts = <0 71 0>; | |
b3cd7d87 | 624 | |
fe273c3e | 625 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 626 | clock-names = "usbhost"; |
dba2f058 KD |
627 | #address-cells = <1>; |
628 | #size-cells = <0>; | |
629 | port@0 { | |
630 | reg = <0>; | |
631 | phys = <&usb2_phy_gen 1>; | |
632 | }; | |
7d40d867 VG |
633 | }; |
634 | ||
dba2f058 KD |
635 | usb2_phy_gen: phy@12130000 { |
636 | compatible = "samsung,exynos5250-usb2-phy"; | |
637 | reg = <0x12130000 0x100>; | |
638 | clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; | |
639 | clock-names = "phy", "ref"; | |
640 | #phy-cells = <1>; | |
641 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
642 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
643 | }; | |
644 | ||
022cf308 LKA |
645 | pwm: pwm@12dd0000 { |
646 | compatible = "samsung,exynos4210-pwm"; | |
647 | reg = <0x12dd0000 0x100>; | |
648 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
649 | #pwm-cells = <3>; | |
fe273c3e | 650 | clocks = <&clock CLK_PWM>; |
022cf308 LKA |
651 | clock-names = "timers"; |
652 | }; | |
653 | ||
b074abb7 KK |
654 | amba { |
655 | #address-cells = <1>; | |
656 | #size-cells = <1>; | |
657 | compatible = "arm,amba-bus"; | |
658 | interrupt-parent = <&gic>; | |
659 | ranges; | |
660 | ||
661 | pdma0: pdma@121A0000 { | |
662 | compatible = "arm,pl330", "arm,primecell"; | |
663 | reg = <0x121A0000 0x1000>; | |
664 | interrupts = <0 34 0>; | |
fe273c3e | 665 | clocks = <&clock CLK_PDMA0>; |
2de6847c | 666 | clock-names = "apb_pclk"; |
42cf2098 PV |
667 | #dma-cells = <1>; |
668 | #dma-channels = <8>; | |
669 | #dma-requests = <32>; | |
b074abb7 KK |
670 | }; |
671 | ||
672 | pdma1: pdma@121B0000 { | |
673 | compatible = "arm,pl330", "arm,primecell"; | |
674 | reg = <0x121B0000 0x1000>; | |
675 | interrupts = <0 35 0>; | |
fe273c3e | 676 | clocks = <&clock CLK_PDMA1>; |
2de6847c | 677 | clock-names = "apb_pclk"; |
42cf2098 PV |
678 | #dma-cells = <1>; |
679 | #dma-channels = <8>; | |
680 | #dma-requests = <32>; | |
b074abb7 KK |
681 | }; |
682 | ||
009f7c9f | 683 | mdma0: mdma@10800000 { |
b074abb7 KK |
684 | compatible = "arm,pl330", "arm,primecell"; |
685 | reg = <0x10800000 0x1000>; | |
686 | interrupts = <0 33 0>; | |
fe273c3e | 687 | clocks = <&clock CLK_MDMA0>; |
2de6847c | 688 | clock-names = "apb_pclk"; |
42cf2098 PV |
689 | #dma-cells = <1>; |
690 | #dma-channels = <8>; | |
691 | #dma-requests = <1>; | |
b074abb7 KK |
692 | }; |
693 | ||
009f7c9f | 694 | mdma1: mdma@11C10000 { |
b074abb7 KK |
695 | compatible = "arm,pl330", "arm,primecell"; |
696 | reg = <0x11C10000 0x1000>; | |
697 | interrupts = <0 124 0>; | |
fe273c3e | 698 | clocks = <&clock CLK_MDMA1>; |
2de6847c | 699 | clock-names = "apb_pclk"; |
42cf2098 PV |
700 | #dma-cells = <1>; |
701 | #dma-channels = <8>; | |
702 | #dma-requests = <1>; | |
b074abb7 KK |
703 | }; |
704 | }; | |
705 | ||
c31f566d | 706 | gsc_0: gsc@13e00000 { |
1128658a SAB |
707 | compatible = "samsung,exynos5-gsc"; |
708 | reg = <0x13e00000 0x1000>; | |
709 | interrupts = <0 85 0>; | |
0da65870 | 710 | power-domains = <&pd_gsc>; |
fe273c3e | 711 | clocks = <&clock CLK_GSCL0>; |
2de6847c | 712 | clock-names = "gscl"; |
1128658a SAB |
713 | }; |
714 | ||
c31f566d | 715 | gsc_1: gsc@13e10000 { |
1128658a SAB |
716 | compatible = "samsung,exynos5-gsc"; |
717 | reg = <0x13e10000 0x1000>; | |
718 | interrupts = <0 86 0>; | |
0da65870 | 719 | power-domains = <&pd_gsc>; |
fe273c3e | 720 | clocks = <&clock CLK_GSCL1>; |
2de6847c | 721 | clock-names = "gscl"; |
1128658a SAB |
722 | }; |
723 | ||
c31f566d | 724 | gsc_2: gsc@13e20000 { |
1128658a SAB |
725 | compatible = "samsung,exynos5-gsc"; |
726 | reg = <0x13e20000 0x1000>; | |
727 | interrupts = <0 87 0>; | |
0da65870 | 728 | power-domains = <&pd_gsc>; |
fe273c3e | 729 | clocks = <&clock CLK_GSCL2>; |
2de6847c | 730 | clock-names = "gscl"; |
1128658a SAB |
731 | }; |
732 | ||
c31f566d | 733 | gsc_3: gsc@13e30000 { |
1128658a SAB |
734 | compatible = "samsung,exynos5-gsc"; |
735 | reg = <0x13e30000 0x1000>; | |
736 | interrupts = <0 88 0>; | |
0da65870 | 737 | power-domains = <&pd_gsc>; |
fe273c3e | 738 | clocks = <&clock CLK_GSCL3>; |
2de6847c | 739 | clock-names = "gscl"; |
1128658a | 740 | }; |
566cf8ee | 741 | |
19fd45bf | 742 | hdmi: hdmi { |
0d1fc829 | 743 | compatible = "samsung,exynos4212-hdmi"; |
101250ce | 744 | reg = <0x14530000 0x70000>; |
566cf8ee | 745 | interrupts = <0 95 0>; |
fe273c3e AH |
746 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
747 | <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
748 | <&clock CLK_MOUT_HDMI>; | |
2de6847c | 749 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
27c16d19 | 750 | "sclk_hdmiphy", "mout_hdmi"; |
e54d90ec | 751 | samsung,syscon-phandle = <&pmu_system_controller>; |
566cf8ee | 752 | }; |
5af0d8a3 RS |
753 | |
754 | mixer { | |
0d1fc829 | 755 | compatible = "samsung,exynos5250-mixer"; |
5af0d8a3 RS |
756 | reg = <0x14450000 0x10000>; |
757 | interrupts = <0 94 0>; | |
c950ea68 MS |
758 | clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, |
759 | <&clock CLK_SCLK_HDMI>; | |
760 | clock-names = "mixer", "hdmi", "sclk_hdmi"; | |
5af0d8a3 | 761 | }; |
ad4aebe1 | 762 | |
77899d53 VS |
763 | dp_phy: video-phy@10040720 { |
764 | compatible = "samsung,exynos5250-dp-video-phy"; | |
e93e5454 | 765 | samsung,pmu-syscon = <&pmu_system_controller>; |
77899d53 VS |
766 | #phy-cells = <0>; |
767 | }; | |
768 | ||
19fd45bf | 769 | dp: dp-controller@145B0000 { |
fe273c3e | 770 | clocks = <&clock CLK_DP>; |
0f72a9ec | 771 | clock-names = "dp"; |
77899d53 VS |
772 | phys = <&dp_phy>; |
773 | phy-names = "dp"; | |
ad4aebe1 | 774 | }; |
a7389cb1 | 775 | |
19fd45bf | 776 | fimd: fimd@14400000 { |
fe273c3e | 777 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
a7389cb1 LKA |
778 | clock-names = "sclk_fimd", "fimd"; |
779 | }; | |
f408f9db NKC |
780 | |
781 | adc: adc@12D10000 { | |
782 | compatible = "samsung,exynos-adc-v1"; | |
db9bf4d6 | 783 | reg = <0x12D10000 0x100>; |
f408f9db | 784 | interrupts = <0 106 0>; |
fe273c3e | 785 | clocks = <&clock CLK_ADC>; |
f408f9db NKC |
786 | clock-names = "adc"; |
787 | #io-channel-cells = <1>; | |
788 | io-channel-ranges; | |
db9bf4d6 | 789 | samsung,syscon-phandle = <&pmu_system_controller>; |
f408f9db NKC |
790 | status = "disabled"; |
791 | }; | |
183af252 NKC |
792 | |
793 | sss@10830000 { | |
794 | compatible = "samsung,exynos4210-secss"; | |
795 | reg = <0x10830000 0x10000>; | |
796 | interrupts = <0 112 0>; | |
e06e1067 | 797 | clocks = <&clock CLK_SSS>; |
183af252 NKC |
798 | clock-names = "secss"; |
799 | }; | |
b074abb7 | 800 | }; |