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ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / exynos5250.dtsi
CommitLineData
b074abb7
KK		 1/*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
fe273c3e 20#include <dt-bindings/clock/exynos5250.h>
e6c21cba 21#include "exynos5.dtsi"
9843a223 22#include "exynos4-cpu-thermal.dtsi"
602408e3 23#include <dt-bindings/clock/exynos-audss-clk.h>
b074abb7
KK		 24
25/ {
8bdb31b4 26 compatible = "samsung,exynos5250", "samsung,exynos5";
b074abb7 27
79989ba3
TA		 28 aliases {
29 spi0 = &spi_0;
30 spi1 = &spi_1;
31 spi2 = &spi_2;
1128658a
SAB		 32 gsc0 = &gsc_0;
33 gsc1 = &gsc_1;
34 gsc2 = &gsc_2;
35 gsc3 = &gsc_3;
c8149df0
YK		 36 mshc0 = &mmc_0;
37 mshc1 = &mmc_1;
38 mshc2 = &mmc_2;
39 mshc3 = &mmc_3;
b9fa3e7b
AK		 40 i2c4 = &i2c_4;
41 i2c5 = &i2c_5;
42 i2c6 = &i2c_6;
43 i2c7 = &i2c_7;
44 i2c8 = &i2c_8;
ba0d7ed3 45 i2c9 = &i2c_9;
f8bfe2b0
TA		 46 pinctrl0 = &pinctrl_0;
47 pinctrl1 = &pinctrl_1;
48 pinctrl2 = &pinctrl_2;
49 pinctrl3 = &pinctrl_3;
79989ba3
TA		 50 };
51
1897d2f3
CK		 52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
bf4a0bed 56 cpu0: cpu@0 {
1897d2f3
CK		 57 device_type = "cpu";
58 compatible = "arm,cortex-a15";
59 reg = <0>;
0da80563 60 clock-frequency = <1700000000>;
846c5300
TA		 61 clocks = <&clock CLK_ARM_CLK>;
62 clock-names = "cpu";
63 clock-latency = <140000>;
64
65 operating-points = <
66 1700000 1300000
67 1600000 1250000
68 1500000 1225000
69 1400000 1200000
70 1300000 1150000
71 1200000 1125000
72 1100000 1100000
73 1000000 1075000
74 900000 1050000
75 800000 1025000
76 700000 1012500
77 600000 1000000
78 500000 975000
79 400000 950000
80 300000 937500
81 200000 925000
82 >;
bf4a0bed
LM		 83 cooling-min-level = <15>;
84 cooling-max-level = <9>;
85 #cooling-cells = <2>; /* min followed by max */
1897d2f3
CK		 86 };
87 cpu@1 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a15";
90 reg = <1>;
0da80563 91 clock-frequency = <1700000000>;
1897d2f3 92 };
79989ba3
TA		 93 };
94
b3205dea
SK		 95 sysram@02020000 {
96 compatible = "mmio-sram";
97 reg = <0x02020000 0x30000>;
98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges = <0 0x02020000 0x30000>;
101
102 smp-sysram@0 {
103 compatible = "samsung,exynos4210-sysram";
104 reg = <0x0 0x1000>;
105 };
106
107 smp-sysram@2f000 {
108 compatible = "samsung,exynos4210-sysram-ns";
109 reg = <0x2f000 0x1000>;
110 };
111 };
112
c31f566d 113 pd_gsc: gsc-power-domain@10044000 {
6f9e95e6
PK		 114 compatible = "samsung,exynos4210-pd";
115 reg = <0x10044000 0x20>;
0da65870 116 #power-domain-cells = <0>;
6f9e95e6
PK		 117 };
118
c31f566d 119 pd_mfc: mfc-power-domain@10044040 {
6f9e95e6
PK		 120 compatible = "samsung,exynos4210-pd";
121 reg = <0x10044040 0x20>;
0da65870 122 #power-domain-cells = <0>;
6f9e95e6
PK		 123 };
124
2d2c9a8d
AH		 125 pd_disp1: disp1-power-domain@100440A0 {
126 compatible = "samsung,exynos4210-pd";
127 reg = <0x100440A0 0x20>;
128 #power-domain-cells = <0>;
69636a85
TV		 129 clocks = <&clock CLK_FIN_PLL>,
130 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
131 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
132 clock-names = "oscclk", "clk0", "clk1";
2d2c9a8d
AH		 133 };
134
c31f566d 135 clock: clock-controller@10010000 {
d8bafc87
TA		 136 compatible = "samsung,exynos5250-clock";
137 reg = <0x10010000 0x30000>;
138 #clock-cells = <1>;
139 };
140
bba23d95
PV		 141 clock_audss: audss-clock-controller@3810000 {
142 compatible = "samsung,exynos5250-audss-clock";
143 reg = <0x03810000 0x0C>;
144 #clock-cells = <1>;
fe273c3e
AH		 145 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
146 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
c08ceea3 147 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
bba23d95
PV		 148 };
149
2b7da988
AG		 150 timer {
151 compatible = "arm,armv7-timer";
152 interrupts = <1 13 0xf08>,
153 <1 14 0xf08>,
154 <1 11 0xf08>,
155 <1 10 0xf08>;
4d594dd3
YK		 156 /* Unfortunately we need this since some versions of U-Boot
157 * on Exynos don't set the CNTFRQ register, so we need the
158 * value from DT.
159 */
160 clock-frequency = <24000000>;
b074abb7
KK		 161 };
162
bbd9700a
TA		 163 mct@101C0000 {
164 compatible = "samsung,exynos4210-mct";
165 reg = <0x101C0000 0x800>;
166 interrupt-controller;
f27b9075 167 #interrupt-cells = <2>;
bbd9700a
TA		 168 interrupt-parent = <&mct_map>;
169 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
170 <4 0>, <5 0>;
fe273c3e 171 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
2de6847c 172 clock-names = "fin_pll", "mct";
bbd9700a
TA		 173
174 mct_map: mct-map {
175 #interrupt-cells = <2>;
176 #address-cells = <0>;
177 #size-cells = <0>;
178 interrupt-map = <0x0 0 &combiner 23 3>,
179 <0x1 0 &combiner 23 4>,
180 <0x2 0 &combiner 25 2>,
181 <0x3 0 &combiner 25 3>,
182 <0x4 0 &gic 0 120 0>,
183 <0x5 0 &gic 0 121 0>;
184 };
185 };
186
4f801e59
CP		 187 pmu {
188 compatible = "arm,cortex-a15-pmu";
189 interrupt-parent = <&combiner>;
190 interrupts = <1 2>, <22 4>;
191 };
192
f8bfe2b0
TA		 193 pinctrl_0: pinctrl@11400000 {
194 compatible = "samsung,exynos5250-pinctrl";
195 reg = <0x11400000 0x1000>;
196 interrupts = <0 46 0>;
197
198 wakup_eint: wakeup-interrupt-controller {
199 compatible = "samsung,exynos4210-wakeup-eint";
200 interrupt-parent = <&gic>;
201 interrupts = <0 32 0>;
202 };
203 };
204
205 pinctrl_1: pinctrl@13400000 {
206 compatible = "samsung,exynos5250-pinctrl";
207 reg = <0x13400000 0x1000>;
208 interrupts = <0 45 0>;
209 };
210
211 pinctrl_2: pinctrl@10d10000 {
212 compatible = "samsung,exynos5250-pinctrl";
213 reg = <0x10d10000 0x1000>;
214 interrupts = <0 50 0>;
215 };
216
0abb6aea 217 pinctrl_3: pinctrl@03860000 {
f8bfe2b0 218 compatible = "samsung,exynos5250-pinctrl";
0abb6aea 219 reg = <0x03860000 0x1000>;
f8bfe2b0
TA		 220 interrupts = <0 47 0>;
221 };
222
c680036a
LKA		 223 pmu_system_controller: system-controller@10040000 {
224 compatible = "samsung,exynos5250-pmu", "syscon";
225 reg = <0x10040000 0x5000>;
d19bb397
TF		 226 clock-names = "clkout16";
227 clocks = <&clock CLK_FIN_PLL>;
228 #clock-cells = <1>;
8b283c02
MZ		 229 interrupt-controller;
230 #interrupt-cells = <3>;
231 interrupt-parent = <&gic>;
c680036a
LKA		 232 };
233
1d287620
LKA		 234 watchdog@101D0000 {
235 compatible = "samsung,exynos5250-wdt";
236 reg = <0x101D0000 0x100>;
237 interrupts = <0 42 0>;
fe273c3e 238 clocks = <&clock CLK_WDT>;
2de6847c 239 clock-names = "watchdog";
1d287620 240 samsung,syscon-phandle = <&pmu_system_controller>;
b074abb7
KK		 241 };
242
21aa5217
SK		 243 g2d@10850000 {
244 compatible = "samsung,exynos5250-g2d";
245 reg = <0x10850000 0x1000>;
246 interrupts = <0 91 0>;
fe273c3e 247 clocks = <&clock CLK_G2D>;
21aa5217 248 clock-names = "fimg2d";
6cbfdd73 249 iommus = <&sysmmu_g2d>;
21aa5217
SK		 250 };
251
19fd45bf 252 mfc: codec@11000000 {
2eae613b
AK		 253 compatible = "samsung,mfc-v6";
254 reg = <0x11000000 0x10000>;
255 interrupts = <0 96 0>;
0da65870 256 power-domains = <&pd_mfc>;
fe273c3e 257 clocks = <&clock CLK_MFC>;
8b6bea33 258 clock-names = "mfc";
6cbfdd73
MS		 259 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
260 iommu-names = "left", "right";
2eae613b
AK		 261 };
262
d35e20d9
MS		 263 rotator: rotator@11C00000 {
264 compatible = "samsung,exynos5250-rotator";
265 reg = <0x11C00000 0x64>;
266 interrupts = <0 84 0>;
267 clocks = <&clock CLK_ROTATOR>;
268 clock-names = "rotator";
269 iommus = <&sysmmu_rotator>;
270 };
271
9843a223 272 tmu: tmu@10060000 {
ef405e04
ADK		 273 compatible = "samsung,exynos5250-tmu";
274 reg = <0x10060000 0x100>;
275 interrupts = <0 65 0>;
fe273c3e 276 clocks = <&clock CLK_TMU>;
2de6847c 277 clock-names = "tmu_apbif";
9843a223 278 #include "exynos4412-tmu-sensor-conf.dtsi"
ef405e04
ADK		 279 };
280
bf4a0bed
LM		 281 thermal-zones {
282 cpu_thermal: cpu-thermal {
9843a223
LM		 283 polling-delay-passive = <0>;
284 polling-delay = <0>;
285 thermal-sensors = <&tmu 0>;
286
bf4a0bed
LM		 287 cooling-maps {
288 map0 {
289 /* Corresponds to 800MHz at freq_table */
290 cooling-device = <&cpu0 9 9>;
291 };
292 map1 {
293 /* Corresponds to 200MHz at freq_table */
294 cooling-device = <&cpu0 15 15>;
295 };
296 };
297 };
298 };
299
19fd45bf 300 sata: sata@122F0000 {
ba0d7ed3
YK		 301 compatible = "snps,dwc-ahci";
302 samsung,sata-freq = <66>;
c47d244a
VA		 303 reg = <0x122F0000 0x1ff>;
304 interrupts = <0 115 0>;
fe273c3e 305 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
2de6847c 306 clock-names = "sata", "sclk_sata";
ba0d7ed3
YK		 307 phys = <&sata_phy>;
308 phy-names = "sata-phy";
309 status = "disabled";
c47d244a
VA		 310 };
311
ba0d7ed3
YK		 312 sata_phy: sata-phy@12170000 {
313 compatible = "samsung,exynos5250-sata-phy";
c47d244a 314 reg = <0x12170000 0x1ff>;
e06e1067 315 clocks = <&clock CLK_SATA_PHYCTRL>;
ba0d7ed3
YK		 316 clock-names = "sata_phyctrl";
317 #phy-cells = <0>;
318 samsung,syscon-phandle = <&pmu_system_controller>;
319 status = "disabled";
c47d244a
VA		 320 };
321
5a124fe0 322 /* i2c_0-3 are defined in exynos5.dtsi */
b9fa3e7b 323 i2c_4: i2c@12CA0000 {
b074abb7
KK		 324 compatible = "samsung,s3c2440-i2c";
325 reg = <0x12CA0000 0x100>;
326 interrupts = <0 60 0>;
009f7c9f
TA		 327 #address-cells = <1>;
328 #size-cells = <0>;
fe273c3e 329 clocks = <&clock CLK_I2C4>;
2de6847c 330 clock-names = "i2c";
f8bfe2b0
TA		 331 pinctrl-names = "default";
332 pinctrl-0 = <&i2c4_bus>;
6ad8ebff 333 status = "disabled";
b074abb7
KK		 334 };
335
b9fa3e7b 336 i2c_5: i2c@12CB0000 {
b074abb7
KK		 337 compatible = "samsung,s3c2440-i2c";
338 reg = <0x12CB0000 0x100>;
339 interrupts = <0 61 0>;
009f7c9f
TA		 340 #address-cells = <1>;
341 #size-cells = <0>;
fe273c3e 342 clocks = <&clock CLK_I2C5>;
2de6847c 343 clock-names = "i2c";
f8bfe2b0
TA		 344 pinctrl-names = "default";
345 pinctrl-0 = <&i2c5_bus>;
6ad8ebff 346 status = "disabled";
b074abb7
KK		 347 };
348
b9fa3e7b 349 i2c_6: i2c@12CC0000 {
b074abb7
KK		 350 compatible = "samsung,s3c2440-i2c";
351 reg = <0x12CC0000 0x100>;
352 interrupts = <0 62 0>;
009f7c9f
TA		 353 #address-cells = <1>;
354 #size-cells = <0>;
fe273c3e 355 clocks = <&clock CLK_I2C6>;
2de6847c 356 clock-names = "i2c";
f8bfe2b0
TA		 357 pinctrl-names = "default";
358 pinctrl-0 = <&i2c6_bus>;
6ad8ebff 359 status = "disabled";
b074abb7
KK		 360 };
361
b9fa3e7b 362 i2c_7: i2c@12CD0000 {
b074abb7
KK		 363 compatible = "samsung,s3c2440-i2c";
364 reg = <0x12CD0000 0x100>;
365 interrupts = <0 63 0>;
009f7c9f
TA		 366 #address-cells = <1>;
367 #size-cells = <0>;
fe273c3e 368 clocks = <&clock CLK_I2C7>;
2de6847c 369 clock-names = "i2c";
f8bfe2b0
TA		 370 pinctrl-names = "default";
371 pinctrl-0 = <&i2c7_bus>;
6ad8ebff 372 status = "disabled";
3e3e9ce4
RS		 373 };
374
b9fa3e7b 375 i2c_8: i2c@12CE0000 {
3e3e9ce4
RS		 376 compatible = "samsung,s3c2440-hdmiphy-i2c";
377 reg = <0x12CE0000 0x1000>;
378 interrupts = <0 64 0>;
379 #address-cells = <1>;
380 #size-cells = <0>;
fe273c3e 381 clocks = <&clock CLK_I2C_HDMI>;
2de6847c 382 clock-names = "i2c";
6ad8ebff 383 status = "disabled";
24025f6f
OJ		 384 };
385
ba0d7ed3 386 i2c_9: i2c@121D0000 {
c47d244a
VA		 387 compatible = "samsung,exynos5-sata-phy-i2c";
388 reg = <0x121D0000 0x100>;
389 #address-cells = <1>;
390 #size-cells = <0>;
fe273c3e 391 clocks = <&clock CLK_SATA_PHYI2C>;
2de6847c 392 clock-names = "i2c";
6ad8ebff 393 status = "disabled";
b074abb7
KK		 394 };
395
79989ba3
TA		 396 spi_0: spi@12d20000 {
397 compatible = "samsung,exynos4210-spi";
fae93f7c 398 status = "disabled";
79989ba3
TA		 399 reg = <0x12d20000 0x100>;
400 interrupts = <0 66 0>;
a4a8a9d3
PV		 401 dmas = <&pdma0 5
402 &pdma0 4>;
403 dma-names = "tx", "rx";
79989ba3
TA		 404 #address-cells = <1>;
405 #size-cells = <0>;
fe273c3e 406 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
2de6847c 407 clock-names = "spi", "spi_busclk0";
f8bfe2b0
TA		 408 pinctrl-names = "default";
409 pinctrl-0 = <&spi0_bus>;
79989ba3
TA		 410 };
411
412 spi_1: spi@12d30000 {
413 compatible = "samsung,exynos4210-spi";
fae93f7c 414 status = "disabled";
79989ba3
TA		 415 reg = <0x12d30000 0x100>;
416 interrupts = <0 67 0>;
a4a8a9d3
PV		 417 dmas = <&pdma1 5
418 &pdma1 4>;
419 dma-names = "tx", "rx";
79989ba3
TA		 420 #address-cells = <1>;
421 #size-cells = <0>;
fe273c3e 422 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
2de6847c 423 clock-names = "spi", "spi_busclk0";
f8bfe2b0
TA		 424 pinctrl-names = "default";
425 pinctrl-0 = <&spi1_bus>;
79989ba3
TA		 426 };
427
428 spi_2: spi@12d40000 {
429 compatible = "samsung,exynos4210-spi";
fae93f7c 430 status = "disabled";
79989ba3
TA		 431 reg = <0x12d40000 0x100>;
432 interrupts = <0 68 0>;
a4a8a9d3
PV		 433 dmas = <&pdma0 7
434 &pdma0 6>;
435 dma-names = "tx", "rx";
79989ba3
TA		 436 #address-cells = <1>;
437 #size-cells = <0>;
fe273c3e 438 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
2de6847c 439 clock-names = "spi", "spi_busclk0";
f8bfe2b0
TA		 440 pinctrl-names = "default";
441 pinctrl-0 = <&spi2_bus>;
79989ba3
TA		 442 };
443
c8149df0 444 mmc_0: mmc@12200000 {
906fd84e
YK		 445 compatible = "samsung,exynos5250-dw-mshc";
446 interrupts = <0 75 0>;
447 #address-cells = <1>;
448 #size-cells = <0>;
84bd48a0 449 reg = <0x12200000 0x1000>;
fe273c3e 450 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
2de6847c 451 clock-names = "biu", "ciu";
46285a90 452 fifo-depth = <0x80>;
e908d5c5 453 status = "disabled";
84bd48a0
TA		 454 };
455
c8149df0 456 mmc_1: mmc@12210000 {
906fd84e
YK		 457 compatible = "samsung,exynos5250-dw-mshc";
458 interrupts = <0 76 0>;
459 #address-cells = <1>;
460 #size-cells = <0>;
84bd48a0 461 reg = <0x12210000 0x1000>;
fe273c3e 462 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
2de6847c 463 clock-names = "biu", "ciu";
46285a90 464 fifo-depth = <0x80>;
e908d5c5 465 status = "disabled";
84bd48a0
TA		 466 };
467
c8149df0 468 mmc_2: mmc@12220000 {
906fd84e
YK		 469 compatible = "samsung,exynos5250-dw-mshc";
470 interrupts = <0 77 0>;
471 #address-cells = <1>;
472 #size-cells = <0>;
84bd48a0 473 reg = <0x12220000 0x1000>;
fe273c3e 474 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
2de6847c 475 clock-names = "biu", "ciu";
46285a90 476 fifo-depth = <0x80>;
e908d5c5 477 status = "disabled";
84bd48a0
TA		 478 };
479
c8149df0 480 mmc_3: mmc@12230000 {
84bd48a0
TA		 481 compatible = "samsung,exynos5250-dw-mshc";
482 reg = <0x12230000 0x1000>;
483 interrupts = <0 78 0>;
484 #address-cells = <1>;
485 #size-cells = <0>;
fe273c3e 486 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
2de6847c 487 clock-names = "biu", "ciu";
46285a90 488 fifo-depth = <0x80>;
e908d5c5 489 status = "disabled";
84bd48a0
TA		 490 };
491
28a48058 492 i2s0: i2s@03830000 {
64183656 493 compatible = "samsung,s5pv210-i2s";
328aee4b 494 status = "disabled";
a0b5f81e 495 reg = <0x03830000 0x100>;
4c4c7463
PV		 496 dmas = <&pdma0 10
497 &pdma0 9
498 &pdma0 8>;
499 dma-names = "tx", "rx", "tx-sec";
916ec47e
PV		 500 clocks = <&clock_audss EXYNOS_I2S_BUS>,
501 <&clock_audss EXYNOS_I2S_BUS>,
502 <&clock_audss EXYNOS_SCLK_I2S>;
503 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
a0b5f81e 504 samsung,idma-addr = <0x03000000>;
f8bfe2b0
TA		 505 pinctrl-names = "default";
506 pinctrl-0 = <&i2s0_bus>;
4c4c7463
PV		 507 };
508
28a48058 509 i2s1: i2s@12D60000 {
64183656 510 compatible = "samsung,s3c6410-i2s";
328aee4b 511 status = "disabled";
a0b5f81e
MB		 512 reg = <0x12D60000 0x100>;
513 dmas = <&pdma1 12
514 &pdma1 11>;
515 dma-names = "tx", "rx";
fe273c3e 516 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
916ec47e 517 clock-names = "iis", "i2s_opclk0";
f8bfe2b0
TA		 518 pinctrl-names = "default";
519 pinctrl-0 = <&i2s1_bus>;
4c4c7463
PV		 520 };
521
28a48058 522 i2s2: i2s@12D70000 {
64183656 523 compatible = "samsung,s3c6410-i2s";
328aee4b 524 status = "disabled";
a0b5f81e
MB		 525 reg = <0x12D70000 0x100>;
526 dmas = <&pdma0 12
527 &pdma0 11>;
528 dma-names = "tx", "rx";
fe273c3e 529 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
916ec47e 530 clock-names = "iis", "i2s_opclk0";
f8bfe2b0
TA		 531 pinctrl-names = "default";
532 pinctrl-0 = <&i2s2_bus>;
4c4c7463
PV		 533 };
534
5c9cbade 535 usb_dwc3 {
0b3dc97e 536 compatible = "samsung,exynos5250-dwusb3";
fe273c3e 537 clocks = <&clock CLK_USB3>;
0b3dc97e
VG		 538 clock-names = "usbdrd30";
539 #address-cells = <1>;
540 #size-cells = <1>;
541 ranges;
542
5c9cbade 543 usbdrd_dwc3: dwc3@12000000 {
0b3dc97e
VG		 544 compatible = "synopsys,dwc3";
545 reg = <0x12000000 0x10000>;
546 interrupts = <0 72 0>;
7a4cf0fd
VG		 547 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
548 phy-names = "usb2-phy", "usb3-phy";
896db3b3
VG		 549 };
550 };
551
517083f4
VG		 552 usbdrd_phy: phy@12100000 {
553 compatible = "samsung,exynos5250-usbdrd-phy";
554 reg = <0x12100000 0x100>;
555 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
556 clock-names = "phy", "ref";
557 samsung,pmu-syscon = <&pmu_system_controller>;
558 #phy-cells = <1>;
559 };
560
19fd45bf 561 ehci: usb@12110000 {
13cbd1e3
VG		 562 compatible = "samsung,exynos4210-ehci";
563 reg = <0x12110000 0x100>;
564 interrupts = <0 71 0>;
b3cd7d87 565
fe273c3e 566 clocks = <&clock CLK_USB2>;
b3cd7d87 567 clock-names = "usbhost";
dba2f058
KD		 568 #address-cells = <1>;
569 #size-cells = <0>;
570 port@0 {
571 reg = <0>;
572 phys = <&usb2_phy_gen 1>;
573 };
13cbd1e3
VG		 574 };
575
19fd45bf 576 ohci: usb@12120000 {
7d40d867
VG		 577 compatible = "samsung,exynos4210-ohci";
578 reg = <0x12120000 0x100>;
579 interrupts = <0 71 0>;
b3cd7d87 580
fe273c3e 581 clocks = <&clock CLK_USB2>;
b3cd7d87 582 clock-names = "usbhost";
dba2f058
KD		 583 #address-cells = <1>;
584 #size-cells = <0>;
585 port@0 {
586 reg = <0>;
587 phys = <&usb2_phy_gen 1>;
588 };
7d40d867
VG		 589 };
590
dba2f058
KD		 591 usb2_phy_gen: phy@12130000 {
592 compatible = "samsung,exynos5250-usb2-phy";
593 reg = <0x12130000 0x100>;
594 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
595 clock-names = "phy", "ref";
596 #phy-cells = <1>;
597 samsung,sysreg-phandle = <&sysreg_system_controller>;
598 samsung,pmureg-phandle = <&pmu_system_controller>;
599 };
600
b074abb7
KK		 601 amba {
602 #address-cells = <1>;
603 #size-cells = <1>;
2ef7d5f3 604 compatible = "simple-bus";
b074abb7
KK		 605 interrupt-parent = <&gic>;
606 ranges;
607
608 pdma0: pdma@121A0000 {
609 compatible = "arm,pl330", "arm,primecell";
610 reg = <0x121A0000 0x1000>;
611 interrupts = <0 34 0>;
fe273c3e 612 clocks = <&clock CLK_PDMA0>;
2de6847c 613 clock-names = "apb_pclk";
42cf2098
PV		 614 #dma-cells = <1>;
615 #dma-channels = <8>;
616 #dma-requests = <32>;
b074abb7
KK		 617 };
618
619 pdma1: pdma@121B0000 {
620 compatible = "arm,pl330", "arm,primecell";
621 reg = <0x121B0000 0x1000>;
622 interrupts = <0 35 0>;
fe273c3e 623 clocks = <&clock CLK_PDMA1>;
2de6847c 624 clock-names = "apb_pclk";
42cf2098
PV		 625 #dma-cells = <1>;
626 #dma-channels = <8>;
627 #dma-requests = <32>;
b074abb7
KK		 628 };
629
009f7c9f 630 mdma0: mdma@10800000 {
b074abb7
KK		 631 compatible = "arm,pl330", "arm,primecell";
632 reg = <0x10800000 0x1000>;
633 interrupts = <0 33 0>;
fe273c3e 634 clocks = <&clock CLK_MDMA0>;
2de6847c 635 clock-names = "apb_pclk";
42cf2098
PV		 636 #dma-cells = <1>;
637 #dma-channels = <8>;
638 #dma-requests = <1>;
b074abb7
KK		 639 };
640
009f7c9f 641 mdma1: mdma@11C10000 {
b074abb7
KK		 642 compatible = "arm,pl330", "arm,primecell";
643 reg = <0x11C10000 0x1000>;
644 interrupts = <0 124 0>;
fe273c3e 645 clocks = <&clock CLK_MDMA1>;
2de6847c 646 clock-names = "apb_pclk";
42cf2098
PV		 647 #dma-cells = <1>;
648 #dma-channels = <8>;
649 #dma-requests = <1>;
b074abb7
KK		 650 };
651 };
652
c31f566d 653 gsc_0: gsc@13e00000 {
1128658a
SAB		 654 compatible = "samsung,exynos5-gsc";
655 reg = <0x13e00000 0x1000>;
656 interrupts = <0 85 0>;
0da65870 657 power-domains = <&pd_gsc>;
fe273c3e 658 clocks = <&clock CLK_GSCL0>;
2de6847c 659 clock-names = "gscl";
6cbfdd73 660 iommu = <&sysmmu_gsc0>;
1128658a
SAB		 661 };
662
c31f566d 663 gsc_1: gsc@13e10000 {
1128658a
SAB		 664 compatible = "samsung,exynos5-gsc";
665 reg = <0x13e10000 0x1000>;
666 interrupts = <0 86 0>;
0da65870 667 power-domains = <&pd_gsc>;
fe273c3e 668 clocks = <&clock CLK_GSCL1>;
2de6847c 669 clock-names = "gscl";
6cbfdd73 670 iommu = <&sysmmu_gsc1>;
1128658a
SAB		 671 };
672
c31f566d 673 gsc_2: gsc@13e20000 {
1128658a
SAB		 674 compatible = "samsung,exynos5-gsc";
675 reg = <0x13e20000 0x1000>;
676 interrupts = <0 87 0>;
0da65870 677 power-domains = <&pd_gsc>;
fe273c3e 678 clocks = <&clock CLK_GSCL2>;
2de6847c 679 clock-names = "gscl";
6cbfdd73 680 iommu = <&sysmmu_gsc2>;
1128658a
SAB		 681 };
682
c31f566d 683 gsc_3: gsc@13e30000 {
1128658a
SAB		 684 compatible = "samsung,exynos5-gsc";
685 reg = <0x13e30000 0x1000>;
686 interrupts = <0 88 0>;
0da65870 687 power-domains = <&pd_gsc>;
fe273c3e 688 clocks = <&clock CLK_GSCL3>;
2de6847c 689 clock-names = "gscl";
6cbfdd73 690 iommu = <&sysmmu_gsc3>;
1128658a 691 };
566cf8ee 692
5c9cbade 693 hdmi: hdmi@14530000 {
0d1fc829 694 compatible = "samsung,exynos4212-hdmi";
101250ce 695 reg = <0x14530000 0x70000>;
2d2c9a8d 696 power-domains = <&pd_disp1>;
566cf8ee 697 interrupts = <0 95 0>;
fe273c3e
AH		 698 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
699 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
700 <&clock CLK_MOUT_HDMI>;
2de6847c 701 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
27c16d19 702 "sclk_hdmiphy", "mout_hdmi";
e54d90ec 703 samsung,syscon-phandle = <&pmu_system_controller>;
566cf8ee 704 };
5af0d8a3 705
5c9cbade 706 mixer@14450000 {
0d1fc829 707 compatible = "samsung,exynos5250-mixer";
5af0d8a3 708 reg = <0x14450000 0x10000>;
2d2c9a8d 709 power-domains = <&pd_disp1>;
5af0d8a3 710 interrupts = <0 94 0>;
c950ea68
MS		 711 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
712 <&clock CLK_SCLK_HDMI>;
713 clock-names = "mixer", "hdmi", "sclk_hdmi";
6cbfdd73 714 iommus = <&sysmmu_tv>;
5af0d8a3 715 };
ad4aebe1 716
5c9cbade 717 dp_phy: video-phy {
77899d53 718 compatible = "samsung,exynos5250-dp-video-phy";
e93e5454 719 samsung,pmu-syscon = <&pmu_system_controller>;
77899d53
VS		 720 #phy-cells = <0>;
721 };
722
f408f9db
NKC		 723 adc: adc@12D10000 {
724 compatible = "samsung,exynos-adc-v1";
db9bf4d6 725 reg = <0x12D10000 0x100>;
f408f9db 726 interrupts = <0 106 0>;
fe273c3e 727 clocks = <&clock CLK_ADC>;
f408f9db
NKC		 728 clock-names = "adc";
729 #io-channel-cells = <1>;
730 io-channel-ranges;
db9bf4d6 731 samsung,syscon-phandle = <&pmu_system_controller>;
f408f9db
NKC		 732 status = "disabled";
733 };
183af252
NKC		 734
735 sss@10830000 {
736 compatible = "samsung,exynos4210-secss";
cb4f2d75 737 reg = <0x10830000 0x300>;
183af252 738 interrupts = <0 112 0>;
e06e1067 739 clocks = <&clock CLK_SSS>;
183af252
NKC		 740 clock-names = "secss";
741 };
6cbfdd73
MS		 742
743 sysmmu_g2d: sysmmu@10A60000 {
744 compatible = "samsung,exynos-sysmmu";
745 reg = <0x10A60000 0x1000>;
746 interrupt-parent = <&combiner>;
747 interrupts = <24 5>;
748 clock-names = "sysmmu", "master";
749 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
750 #iommu-cells = <0>;
751 };
752
753 sysmmu_mfc_r: sysmmu@11200000 {
754 compatible = "samsung,exynos-sysmmu";
755 reg = <0x11200000 0x1000>;
756 interrupt-parent = <&combiner>;
757 interrupts = <6 2>;
758 power-domains = <&pd_mfc>;
759 clock-names = "sysmmu", "master";
760 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
761 #iommu-cells = <0>;
762 };
763
764 sysmmu_mfc_l: sysmmu@11210000 {
765 compatible = "samsung,exynos-sysmmu";
766 reg = <0x11210000 0x1000>;
767 interrupt-parent = <&combiner>;
768 interrupts = <8 5>;
769 power-domains = <&pd_mfc>;
770 clock-names = "sysmmu", "master";
771 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
772 #iommu-cells = <0>;
773 };
774
775 sysmmu_rotator: sysmmu@11D40000 {
776 compatible = "samsung,exynos-sysmmu";
777 reg = <0x11D40000 0x1000>;
778 interrupt-parent = <&combiner>;
779 interrupts = <4 0>;
780 clock-names = "sysmmu", "master";
781 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
782 #iommu-cells = <0>;
783 };
784
785 sysmmu_jpeg: sysmmu@11F20000 {
786 compatible = "samsung,exynos-sysmmu";
787 reg = <0x11F20000 0x1000>;
788 interrupt-parent = <&combiner>;
789 interrupts = <4 2>;
790 power-domains = <&pd_gsc>;
791 clock-names = "sysmmu", "master";
792 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
793 #iommu-cells = <0>;
794 };
795
796 sysmmu_fimc_isp: sysmmu@13260000 {
797 compatible = "samsung,exynos-sysmmu";
798 reg = <0x13260000 0x1000>;
799 interrupt-parent = <&combiner>;
800 interrupts = <10 6>;
801 clock-names = "sysmmu";
802 clocks = <&clock CLK_SMMU_FIMC_ISP>;
803 #iommu-cells = <0>;
804 };
805
806 sysmmu_fimc_drc: sysmmu@13270000 {
807 compatible = "samsung,exynos-sysmmu";
808 reg = <0x13270000 0x1000>;
809 interrupt-parent = <&combiner>;
810 interrupts = <11 6>;
811 clock-names = "sysmmu";
812 clocks = <&clock CLK_SMMU_FIMC_DRC>;
813 #iommu-cells = <0>;
814 };
815
816 sysmmu_fimc_fd: sysmmu@132A0000 {
817 compatible = "samsung,exynos-sysmmu";
818 reg = <0x132A0000 0x1000>;
819 interrupt-parent = <&combiner>;
820 interrupts = <5 0>;
821 clock-names = "sysmmu";
822 clocks = <&clock CLK_SMMU_FIMC_FD>;
823 #iommu-cells = <0>;
824 };
825
826 sysmmu_fimc_scc: sysmmu@13280000 {
827 compatible = "samsung,exynos-sysmmu";
828 reg = <0x13280000 0x1000>;
829 interrupt-parent = <&combiner>;
830 interrupts = <5 2>;
831 clock-names = "sysmmu";
832 clocks = <&clock CLK_SMMU_FIMC_SCC>;
833 #iommu-cells = <0>;
834 };
835
836 sysmmu_fimc_scp: sysmmu@13290000 {
837 compatible = "samsung,exynos-sysmmu";
838 reg = <0x13290000 0x1000>;
839 interrupt-parent = <&combiner>;
840 interrupts = <3 6>;
841 clock-names = "sysmmu";
842 clocks = <&clock CLK_SMMU_FIMC_SCP>;
843 #iommu-cells = <0>;
844 };
845
846 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
847 compatible = "samsung,exynos-sysmmu";
848 reg = <0x132B0000 0x1000>;
849 interrupt-parent = <&combiner>;
850 interrupts = <5 4>;
851 clock-names = "sysmmu";
852 clocks = <&clock CLK_SMMU_FIMC_MCU>;
853 #iommu-cells = <0>;
854 };
855
856 sysmmu_fimc_odc: sysmmu@132C0000 {
857 compatible = "samsung,exynos-sysmmu";
858 reg = <0x132C0000 0x1000>;
859 interrupt-parent = <&combiner>;
860 interrupts = <11 0>;
861 clock-names = "sysmmu";
862 clocks = <&clock CLK_SMMU_FIMC_ODC>;
863 #iommu-cells = <0>;
864 };
865
866 sysmmu_fimc_dis0: sysmmu@132D0000 {
867 compatible = "samsung,exynos-sysmmu";
868 reg = <0x132D0000 0x1000>;
869 interrupt-parent = <&combiner>;
870 interrupts = <10 4>;
871 clock-names = "sysmmu";
872 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
873 #iommu-cells = <0>;
874 };
875
876 sysmmu_fimc_dis1: sysmmu@132E0000{
877 compatible = "samsung,exynos-sysmmu";
878 reg = <0x132E0000 0x1000>;
879 interrupt-parent = <&combiner>;
880 interrupts = <9 4>;
881 clock-names = "sysmmu";
882 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
883 #iommu-cells = <0>;
884 };
885
886 sysmmu_fimc_3dnr: sysmmu@132F0000 {
887 compatible = "samsung,exynos-sysmmu";
888 reg = <0x132F0000 0x1000>;
889 interrupt-parent = <&combiner>;
890 interrupts = <5 6>;
891 clock-names = "sysmmu";
892 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
893 #iommu-cells = <0>;
894 };
895
896 sysmmu_fimc_lite0: sysmmu@13C40000 {
897 compatible = "samsung,exynos-sysmmu";
898 reg = <0x13C40000 0x1000>;
899 interrupt-parent = <&combiner>;
900 interrupts = <3 4>;
901 power-domains = <&pd_gsc>;
902 clock-names = "sysmmu", "master";
903 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
904 #iommu-cells = <0>;
905 };
906
907 sysmmu_fimc_lite1: sysmmu@13C50000 {
908 compatible = "samsung,exynos-sysmmu";
909 reg = <0x13C50000 0x1000>;
910 interrupt-parent = <&combiner>;
911 interrupts = <24 1>;
912 power-domains = <&pd_gsc>;
913 clock-names = "sysmmu", "master";
914 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
915 #iommu-cells = <0>;
916 };
917
918 sysmmu_gsc0: sysmmu@13E80000 {
919 compatible = "samsung,exynos-sysmmu";
920 reg = <0x13E80000 0x1000>;
921 interrupt-parent = <&combiner>;
922 interrupts = <2 0>;
923 power-domains = <&pd_gsc>;
924 clock-names = "sysmmu", "master";
925 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
926 #iommu-cells = <0>;
927 };
928
929 sysmmu_gsc1: sysmmu@13E90000 {
930 compatible = "samsung,exynos-sysmmu";
931 reg = <0x13E90000 0x1000>;
932 interrupt-parent = <&combiner>;
933 interrupts = <2 2>;
934 power-domains = <&pd_gsc>;
935 clock-names = "sysmmu", "master";
936 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
937 #iommu-cells = <0>;
938 };
939
940 sysmmu_gsc2: sysmmu@13EA0000 {
941 compatible = "samsung,exynos-sysmmu";
942 reg = <0x13EA0000 0x1000>;
943 interrupt-parent = <&combiner>;
944 interrupts = <2 4>;
945 power-domains = <&pd_gsc>;
946 clock-names = "sysmmu", "master";
947 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
948 #iommu-cells = <0>;
949 };
950
951 sysmmu_gsc3: sysmmu@13EB0000 {
952 compatible = "samsung,exynos-sysmmu";
953 reg = <0x13EB0000 0x1000>;
954 interrupt-parent = <&combiner>;
955 interrupts = <2 6>;
956 power-domains = <&pd_gsc>;
957 clock-names = "sysmmu", "master";
958 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
959 #iommu-cells = <0>;
960 };
961
962 sysmmu_fimd1: sysmmu@14640000 {
963 compatible = "samsung,exynos-sysmmu";
964 reg = <0x14640000 0x1000>;
965 interrupt-parent = <&combiner>;
966 interrupts = <3 2>;
967 power-domains = <&pd_disp1>;
968 clock-names = "sysmmu", "master";
969 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
970 #iommu-cells = <0>;
971 };
972
973 sysmmu_tv: sysmmu@14650000 {
974 compatible = "samsung,exynos-sysmmu";
975 reg = <0x14650000 0x1000>;
976 interrupt-parent = <&combiner>;
977 interrupts = <7 4>;
978 power-domains = <&pd_disp1>;
979 clock-names = "sysmmu", "master";
980 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
981 #iommu-cells = <0>;
982 };
b074abb7 983};
e9a2f409
KK		 984
985&dp {
986 power-domains = <&pd_disp1>;
987 clocks = <&clock CLK_DP>;
988 clock-names = "dp";
989 phys = <&dp_phy>;
990 phy-names = "dp";
991};
992
993&fimd {
994 power-domains = <&pd_disp1>;
995 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
996 clock-names = "sclk_fimd", "fimd";
6cbfdd73 997 iommus = <&sysmmu_fimd1>;
e9a2f409
KK		 998};
999
5a124fe0
KK		 1000&i2c_0 {
1001 clocks = <&clock CLK_I2C0>;
1002 clock-names = "i2c";
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&i2c0_bus>;
1005};
1006
1007&i2c_1 {
1008 clocks = <&clock CLK_I2C1>;
1009 clock-names = "i2c";
1010 pinctrl-names = "default";
1011 pinctrl-0 = <&i2c1_bus>;
1012};
1013
1014&i2c_2 {
1015 clocks = <&clock CLK_I2C2>;
1016 clock-names = "i2c";
1017 pinctrl-names = "default";
1018 pinctrl-0 = <&i2c2_bus>;
1019};
1020
1021&i2c_3 {
1022 clocks = <&clock CLK_I2C3>;
1023 clock-names = "i2c";
1024 pinctrl-names = "default";
1025 pinctrl-0 = <&i2c3_bus>;
1026};
1027
1028&pwm {
1029 clocks = <&clock CLK_PWM>;
1030 clock-names = "timers";
1031};
1032
e9a2f409
KK		 1033&rtc {
1034 clocks = <&clock CLK_RTC>;
1035 clock-names = "rtc";
1036 interrupt-parent = <&pmu_system_controller>;
1037 status = "disabled";
1038};
1039
1040&serial_0 {
1041 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1042 clock-names = "uart", "clk_uart_baud0";
1043};
1044
1045&serial_1 {
1046 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1047 clock-names = "uart", "clk_uart_baud0";
1048};
1049
1050&serial_2 {
1051 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1052 clock-names = "uart", "clk_uart_baud0";
1053};
1054
1055&serial_3 {
1056 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1057 clock-names = "uart", "clk_uart_baud0";
1058};
dc561797
JMC		 1059
1060#include "exynos5250-pinctrl.dtsi"
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