[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / exynos5260.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * SAMSUNG EXYNOS5260 SoC device tree source
 *
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 */

#include <dt-bindings/clock/exynos5260-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "samsung,exynos5260", "samsung,exynos5";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;
			cci-control-port = <&cci_control1>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x1>;
			cci-control-port = <&cci_control1>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x100>;
			cci-control-port = <&cci_control0>;
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x101>;
			cci-control-port = <&cci_control0>;
		};

		cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x102>;
			cci-control-port = <&cci_control0>;
		};

		cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x103>;
			cci-control-port = <&cci_control0>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		clock_top: clock-controller@10010000 {
			compatible = "samsung,exynos5260-clock-top";
			reg = <0x10010000 0x10000>;
			#clock-cells = <1>;
		};

		clock_peri: clock-controller@10200000 {
			compatible = "samsung,exynos5260-clock-peri";
			reg = <0x10200000 0x10000>;
			#clock-cells = <1>;
		};

		clock_egl: clock-controller@10600000 {
			compatible = "samsung,exynos5260-clock-egl";
			reg = <0x10600000 0x10000>;
			#clock-cells = <1>;
		};

		clock_kfc: clock-controller@10700000 {
			compatible = "samsung,exynos5260-clock-kfc";
			reg = <0x10700000 0x10000>;
			#clock-cells = <1>;
		};

		clock_g2d: clock-controller@10a00000 {
			compatible = "samsung,exynos5260-clock-g2d";
			reg = <0x10A00000 0x10000>;
			#clock-cells = <1>;
		};

		clock_mif: clock-controller@10ce0000 {
			compatible = "samsung,exynos5260-clock-mif";
			reg = <0x10CE0000 0x10000>;
			#clock-cells = <1>;
		};

		clock_mfc: clock-controller@11090000 {
			compatible = "samsung,exynos5260-clock-mfc";
			reg = <0x11090000 0x10000>;
			#clock-cells = <1>;
		};

		clock_g3d: clock-controller@11830000 {
			compatible = "samsung,exynos5260-clock-g3d";
			reg = <0x11830000 0x10000>;
			#clock-cells = <1>;
		};

		clock_fsys: clock-controller@122e0000 {
			compatible = "samsung,exynos5260-clock-fsys";
			reg = <0x122E0000 0x10000>;
			#clock-cells = <1>;
		};

		clock_aud: clock-controller@128c0000 {
			compatible = "samsung,exynos5260-clock-aud";
			reg = <0x128C0000 0x10000>;
			#clock-cells = <1>;
		};

		clock_isp: clock-controller@133c0000 {
			compatible = "samsung,exynos5260-clock-isp";
			reg = <0x133C0000 0x10000>;
			#clock-cells = <1>;
		};

		clock_gscl: clock-controller@13f00000 {
			compatible = "samsung,exynos5260-clock-gscl";
			reg = <0x13F00000 0x10000>;
			#clock-cells = <1>;
		};

		clock_disp: clock-controller@14550000 {
			compatible = "samsung,exynos5260-clock-disp";
			reg = <0x14550000 0x10000>;
			#clock-cells = <1>;
		};

		gic: interrupt-controller@10481000 {
			compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-controller;
			reg = <0x10481000 0x1000>,
				<0x10482000 0x2000>,
				<0x10484000 0x2000>,
				<0x10486000 0x2000>;
			interrupts = <GIC_PPI 9
					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		chipid: chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		mct: mct@100b0000 {
			compatible = "samsung,exynos4210-mct";
			reg = <0x100B0000 0x1000>;
			clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
			clock-names = "fin_pll", "mct";
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
		};

		cci: cci@10f00000 {
			compatible = "arm,cci-400";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x10F00000 0x1000>;
			ranges = <0x0 0x10F00000 0x6000>;

			cci_control0: slave-if@4000 {
				compatible = "arm,cci-400-ctrl-if";
				interface-type = "ace";
				reg = <0x4000 0x1000>;
			};

			cci_control1: slave-if@5000 {
				compatible = "arm,cci-400-ctrl-if";
				interface-type = "ace";
				reg = <0x5000 0x1000>;
			};
		};

		pinctrl_0: pinctrl@11600000 {
			compatible = "samsung,exynos5260-pinctrl";
			reg = <0x11600000 0x1000>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos4210-wakeup-eint";
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		pinctrl_1: pinctrl@12290000 {
			compatible = "samsung,exynos5260-pinctrl";
			reg = <0x12290000 0x1000>;
			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_2: pinctrl@128b0000 {
			compatible = "samsung,exynos5260-pinctrl";
			reg = <0x128B0000 0x1000>;
			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
		};

		pmu_system_controller: system-controller@10d50000 {
			compatible = "samsung,exynos5260-pmu", "syscon";
			reg = <0x10D50000 0x10000>;
		};

		uart0: serial@12c00000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12C00000 0x100>;
			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		uart1: serial@12c10000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12C10000 0x100>;
			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		uart2: serial@12c20000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12C20000 0x100>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		uart3: serial@12860000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12860000 0x100>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		mmc_0: mmc@12140000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12140000 0x2000>;
			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <64>;
			status = "disabled";
		};

		mmc_1: mmc@12150000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12150000 0x2000>;
			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <64>;
			status = "disabled";
		};

		mmc_2: mmc@12160000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12160000 0x2000>;
			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
			clock-names = "biu", "ciu";
			fifo-depth = <64>;
			status = "disabled";
		};
	};
};

#include "exynos5260-pinctrl.dtsi"
Commit	Line	Data
cc4637f7	1	// SPDX-License-Identifier: GPL-2.0
16d7ff26 RS	2	/*
	3	* SAMSUNG EXYNOS5260 SoC device tree source
	4	*
	5	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	6	* http://www.samsung.com
cc4637f7	7	*/
16d7ff26	8
16d7ff26	9	#include <dt-bindings/clock/exynos5260-clk.h>
7184c42c	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
eb87868a	11	#include <dt-bindings/interrupt-controller/irq.h>
16d7ff26 RS	12
	13	/ {
	14	compatible = "samsung,exynos5260", "samsung,exynos5";
	15	interrupt-parent = <&gic>;
12676ee1 JMC	16	#address-cells = <1>;
12676ee1 JMC	17	#size-cells = <1>;
16d7ff26 RS	18
	19	aliases {
	20	pinctrl0 = &pinctrl_0;
	21	pinctrl1 = &pinctrl_1;
	22	pinctrl2 = &pinctrl_2;
1e64f48e TF	23	serial0 = &uart0;
	24	serial1 = &uart1;
	25	serial2 = &uart2;
	26	serial3 = &uart3;
16d7ff26 RS	27	};
	28
	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	cpu@0 {
	34	device_type = "cpu";
	35	compatible = "arm,cortex-a15";
	36	reg = <0x0>;
	37	cci-control-port = <&cci_control1>;
	38	};
	39
	40	cpu@1 {
	41	device_type = "cpu";
	42	compatible = "arm,cortex-a15";
	43	reg = <0x1>;
	44	cci-control-port = <&cci_control1>;
	45	};
	46
	47	cpu@100 {
	48	device_type = "cpu";
	49	compatible = "arm,cortex-a7";
	50	reg = <0x100>;
	51	cci-control-port = <&cci_control0>;
	52	};
	53
	54	cpu@101 {
	55	device_type = "cpu";
	56	compatible = "arm,cortex-a7";
	57	reg = <0x101>;
	58	cci-control-port = <&cci_control0>;
	59	};
	60
	61	cpu@102 {
	62	device_type = "cpu";
	63	compatible = "arm,cortex-a7";
	64	reg = <0x102>;
	65	cci-control-port = <&cci_control0>;
	66	};
	67
	68	cpu@103 {
	69	device_type = "cpu";
	70	compatible = "arm,cortex-a7";
	71	reg = <0x103>;
	72	cci-control-port = <&cci_control0>;
	73	};
	74	};
	75
	76	soc: soc {
	77	compatible = "simple-bus";
	78	#address-cells = <1>;
	79	#size-cells = <1>;
	80	ranges;
	81
	82	clock_top: clock-controller@10010000 {
	83	compatible = "samsung,exynos5260-clock-top";
	84	reg = <0x10010000 0x10000>;
	85	#clock-cells = <1>;
	86	};
	87
	88	clock_peri: clock-controller@10200000 {
	89	compatible = "samsung,exynos5260-clock-peri";
	90	reg = <0x10200000 0x10000>;
91	#clock-cells = <1>;
92	};
93
94	clock_egl: clock-controller@10600000 {
95	compatible = "samsung,exynos5260-clock-egl";
96	reg = <0x10600000 0x10000>;
97	#clock-cells = <1>;
98	};
99
100	clock_kfc: clock-controller@10700000 {
101	compatible = "samsung,exynos5260-clock-kfc";
102	reg = <0x10700000 0x10000>;
103	#clock-cells = <1>;
104	};
105
3be1ecf2	106	clock_g2d: clock-controller@10a00000 {
16d7ff26 RS	107	compatible = "samsung,exynos5260-clock-g2d";
	108	reg = <0x10A00000 0x10000>;
	109	#clock-cells = <1>;
	110	};
	111
3be1ecf2	112	clock_mif: clock-controller@10ce0000 {
16d7ff26 RS	113	compatible = "samsung,exynos5260-clock-mif";
	114	reg = <0x10CE0000 0x10000>;
	115	#clock-cells = <1>;
	116	};
	117
	118	clock_mfc: clock-controller@11090000 {
	119	compatible = "samsung,exynos5260-clock-mfc";
	120	reg = <0x11090000 0x10000>;
	121	#clock-cells = <1>;
	122	};
	123
	124	clock_g3d: clock-controller@11830000 {
	125	compatible = "samsung,exynos5260-clock-g3d";
	126	reg = <0x11830000 0x10000>;
	127	#clock-cells = <1>;
	128	};
	129
3be1ecf2	130	clock_fsys: clock-controller@122e0000 {
16d7ff26 RS	131	compatible = "samsung,exynos5260-clock-fsys";
	132	reg = <0x122E0000 0x10000>;
	133	#clock-cells = <1>;
	134	};
	135
3be1ecf2	136	clock_aud: clock-controller@128c0000 {
16d7ff26 RS	137	compatible = "samsung,exynos5260-clock-aud";
	138	reg = <0x128C0000 0x10000>;
	139	#clock-cells = <1>;
	140	};
	141
3be1ecf2	142	clock_isp: clock-controller@133c0000 {
16d7ff26 RS	143	compatible = "samsung,exynos5260-clock-isp";
	144	reg = <0x133C0000 0x10000>;
	145	#clock-cells = <1>;
	146	};
	147
3be1ecf2	148	clock_gscl: clock-controller@13f00000 {
16d7ff26 RS	149	compatible = "samsung,exynos5260-clock-gscl";
	150	reg = <0x13F00000 0x10000>;
	151	#clock-cells = <1>;
	152	};
	153
	154	clock_disp: clock-controller@14550000 {
	155	compatible = "samsung,exynos5260-clock-disp";
	156	reg = <0x14550000 0x10000>;
	157	#clock-cells = <1>;
	158	};
	159
	160	gic: interrupt-controller@10481000 {
	161	compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
	162	#interrupt-cells = <3>;
	163	#address-cells = <0>;
	164	#size-cells = <0>;
	165	interrupt-controller;
	166	reg = <0x10481000 0x1000>,
387720c9	167	<0x10482000 0x2000>,
16d7ff26 RS	168	<0x10484000 0x2000>,
16d7ff26 RS	169	<0x10486000 0x2000>;
7184c42c KK	170	interrupts = <GIC_PPI 9
7184c42c KK	171	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
16d7ff26 RS	172	};
	173
	174	chipid: chipid@10000000 {
	175	compatible = "samsung,exynos4210-chipid";
	176	reg = <0x10000000 0x100>;
	177	};
	178
3be1ecf2	179	mct: mct@100b0000 {
16d7ff26 RS	180	compatible = "samsung,exynos4210-mct";
	181	reg = <0x100B0000 0x1000>;
	182	clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
	183	clock-names = "fin_pll", "mct";
7184c42c KK	184	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	185	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	186	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	187	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	188	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	189	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	190	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	191	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	192	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	193	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
	194	<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	195	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	196	};
16d7ff26 RS	197
3be1ecf2	198	cci: cci@10f00000 {
16d7ff26 RS	199	compatible = "arm,cci-400";
	200	#address-cells = <1>;
	201	#size-cells = <1>;
	202	reg = <0x10F00000 0x1000>;
	203	ranges = <0x0 0x10F00000 0x6000>;
	204
	205	cci_control0: slave-if@4000 {
	206	compatible = "arm,cci-400-ctrl-if";
	207	interface-type = "ace";
	208	reg = <0x4000 0x1000>;
	209	};
	210
	211	cci_control1: slave-if@5000 {
	212	compatible = "arm,cci-400-ctrl-if";
	213	interface-type = "ace";
	214	reg = <0x5000 0x1000>;
	215	};
	216	};
	217
	218	pinctrl_0: pinctrl@11600000 {
	219	compatible = "samsung,exynos5260-pinctrl";
	220	reg = <0x11600000 0x1000>;
7184c42c	221	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	222
	223	wakeup-interrupt-controller {
	224	compatible = "samsung,exynos4210-wakeup-eint";
	225	interrupt-parent = <&gic>;
7184c42c	226	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	227	};
	228	};
	229
	230	pinctrl_1: pinctrl@12290000 {
	231	compatible = "samsung,exynos5260-pinctrl";
	232	reg = <0x12290000 0x1000>;
7184c42c	233	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	234	};
16d7ff26 RS	235
3be1ecf2	236	pinctrl_2: pinctrl@128b0000 {
16d7ff26 RS	237	compatible = "samsung,exynos5260-pinctrl";
16d7ff26 RS	238	reg = <0x128B0000 0x1000>;
7184c42c	239	interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	240	};
16d7ff26 RS	241
3be1ecf2	242	pmu_system_controller: system-controller@10d50000 {
fbe4e9f5 VS	243	compatible = "samsung,exynos5260-pmu", "syscon";
	244	reg = <0x10D50000 0x10000>;
	245	};
	246
3be1ecf2	247	uart0: serial@12c00000 {
16d7ff26 RS	248	compatible = "samsung,exynos4210-uart";
16d7ff26 RS	249	reg = <0x12C00000 0x100>;
7184c42c	250	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	251	clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
	252	clock-names = "uart", "clk_uart_baud0";
	253	status = "disabled";
	254	};
	255
3be1ecf2	256	uart1: serial@12c10000 {
16d7ff26 RS	257	compatible = "samsung,exynos4210-uart";
16d7ff26 RS	258	reg = <0x12C10000 0x100>;
7184c42c	259	interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	260	clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
	261	clock-names = "uart", "clk_uart_baud0";
	262	status = "disabled";
	263	};
	264
3be1ecf2	265	uart2: serial@12c20000 {
16d7ff26 RS	266	compatible = "samsung,exynos4210-uart";
16d7ff26 RS	267	reg = <0x12C20000 0x100>;
7184c42c	268	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	269	clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
	270	clock-names = "uart", "clk_uart_baud0";
	271	status = "disabled";
	272	};
	273
	274	uart3: serial@12860000 {
	275	compatible = "samsung,exynos4210-uart";
	276	reg = <0x12860000 0x100>;
7184c42c	277	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	278	clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
	279	clock-names = "uart", "clk_uart_baud0";
	280	status = "disabled";
	281	};
	282
	283	mmc_0: mmc@12140000 {
	284	compatible = "samsung,exynos5250-dw-mshc";
	285	reg = <0x12140000 0x2000>;
7184c42c	286	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	287	#address-cells = <1>;
	288	#size-cells = <0>;
	289	clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
	290	clock-names = "biu", "ciu";
	291	fifo-depth = <64>;
	292	status = "disabled";
	293	};
	294
	295	mmc_1: mmc@12150000 {
	296	compatible = "samsung,exynos5250-dw-mshc";
	297	reg = <0x12150000 0x2000>;
7184c42c	298	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	299	#address-cells = <1>;
	300	#size-cells = <0>;
	301	clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
	302	clock-names = "biu", "ciu";
	303	fifo-depth = <64>;
	304	status = "disabled";
	305	};
	306
	307	mmc_2: mmc@12160000 {
	308	compatible = "samsung,exynos5250-dw-mshc";
	309	reg = <0x12160000 0x2000>;
7184c42c	310	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
16d7ff26 RS	311	#address-cells = <1>;
	312	#size-cells = <0>;
	313	clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
	314	clock-names = "biu", "ciu";
	315	fifo-depth = <64>;
	316	status = "disabled";
	317	};
	318	};
	319	};
	320
	321	#include "exynos5260-pinctrl.dtsi"