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cc4637f7 | 1 | // SPDX-License-Identifier: GPL-2.0 |
16d7ff26 RS |
2 | /* |
3 | * SAMSUNG EXYNOS5260 SoC device tree source | |
4 | * | |
5 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
6 | * http://www.samsung.com | |
cc4637f7 | 7 | */ |
16d7ff26 | 8 | |
16d7ff26 | 9 | #include <dt-bindings/clock/exynos5260-clk.h> |
7184c42c | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
eb87868a | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
16d7ff26 RS |
12 | |
13 | / { | |
14 | compatible = "samsung,exynos5260", "samsung,exynos5"; | |
15 | interrupt-parent = <&gic>; | |
12676ee1 JMC |
16 | #address-cells = <1>; |
17 | #size-cells = <1>; | |
16d7ff26 RS |
18 | |
19 | aliases { | |
c5432b1d SM |
20 | i2c0 = &hsi2c_0; |
21 | i2c1 = &hsi2c_1; | |
22 | i2c2 = &hsi2c_2; | |
23 | i2c3 = &hsi2c_3; | |
16d7ff26 RS |
24 | pinctrl0 = &pinctrl_0; |
25 | pinctrl1 = &pinctrl_1; | |
26 | pinctrl2 = &pinctrl_2; | |
1e64f48e TF |
27 | serial0 = &uart0; |
28 | serial1 = &uart1; | |
29 | serial2 = &uart2; | |
30 | serial3 = &uart3; | |
16d7ff26 RS |
31 | }; |
32 | ||
33 | cpus { | |
34 | #address-cells = <1>; | |
35 | #size-cells = <0>; | |
36 | ||
37 | cpu@0 { | |
38 | device_type = "cpu"; | |
39 | compatible = "arm,cortex-a15"; | |
40 | reg = <0x0>; | |
41 | cci-control-port = <&cci_control1>; | |
42 | }; | |
43 | ||
44 | cpu@1 { | |
45 | device_type = "cpu"; | |
46 | compatible = "arm,cortex-a15"; | |
47 | reg = <0x1>; | |
48 | cci-control-port = <&cci_control1>; | |
49 | }; | |
50 | ||
51 | cpu@100 { | |
52 | device_type = "cpu"; | |
53 | compatible = "arm,cortex-a7"; | |
54 | reg = <0x100>; | |
55 | cci-control-port = <&cci_control0>; | |
56 | }; | |
57 | ||
58 | cpu@101 { | |
59 | device_type = "cpu"; | |
60 | compatible = "arm,cortex-a7"; | |
61 | reg = <0x101>; | |
62 | cci-control-port = <&cci_control0>; | |
63 | }; | |
64 | ||
65 | cpu@102 { | |
66 | device_type = "cpu"; | |
67 | compatible = "arm,cortex-a7"; | |
68 | reg = <0x102>; | |
69 | cci-control-port = <&cci_control0>; | |
70 | }; | |
71 | ||
72 | cpu@103 { | |
73 | device_type = "cpu"; | |
74 | compatible = "arm,cortex-a7"; | |
75 | reg = <0x103>; | |
76 | cci-control-port = <&cci_control0>; | |
77 | }; | |
78 | }; | |
79 | ||
80 | soc: soc { | |
81 | compatible = "simple-bus"; | |
82 | #address-cells = <1>; | |
83 | #size-cells = <1>; | |
84 | ranges; | |
85 | ||
86 | clock_top: clock-controller@10010000 { | |
87 | compatible = "samsung,exynos5260-clock-top"; | |
88 | reg = <0x10010000 0x10000>; | |
89 | #clock-cells = <1>; | |
90 | }; | |
91 | ||
92 | clock_peri: clock-controller@10200000 { | |
93 | compatible = "samsung,exynos5260-clock-peri"; | |
94 | reg = <0x10200000 0x10000>; | |
95 | #clock-cells = <1>; | |
96 | }; | |
97 | ||
98 | clock_egl: clock-controller@10600000 { | |
99 | compatible = "samsung,exynos5260-clock-egl"; | |
100 | reg = <0x10600000 0x10000>; | |
101 | #clock-cells = <1>; | |
102 | }; | |
103 | ||
104 | clock_kfc: clock-controller@10700000 { | |
105 | compatible = "samsung,exynos5260-clock-kfc"; | |
106 | reg = <0x10700000 0x10000>; | |
107 | #clock-cells = <1>; | |
108 | }; | |
109 | ||
3be1ecf2 | 110 | clock_g2d: clock-controller@10a00000 { |
16d7ff26 RS |
111 | compatible = "samsung,exynos5260-clock-g2d"; |
112 | reg = <0x10A00000 0x10000>; | |
113 | #clock-cells = <1>; | |
114 | }; | |
115 | ||
3be1ecf2 | 116 | clock_mif: clock-controller@10ce0000 { |
16d7ff26 RS |
117 | compatible = "samsung,exynos5260-clock-mif"; |
118 | reg = <0x10CE0000 0x10000>; | |
119 | #clock-cells = <1>; | |
120 | }; | |
121 | ||
122 | clock_mfc: clock-controller@11090000 { | |
123 | compatible = "samsung,exynos5260-clock-mfc"; | |
124 | reg = <0x11090000 0x10000>; | |
125 | #clock-cells = <1>; | |
126 | }; | |
127 | ||
128 | clock_g3d: clock-controller@11830000 { | |
129 | compatible = "samsung,exynos5260-clock-g3d"; | |
130 | reg = <0x11830000 0x10000>; | |
131 | #clock-cells = <1>; | |
132 | }; | |
133 | ||
3be1ecf2 | 134 | clock_fsys: clock-controller@122e0000 { |
16d7ff26 RS |
135 | compatible = "samsung,exynos5260-clock-fsys"; |
136 | reg = <0x122E0000 0x10000>; | |
137 | #clock-cells = <1>; | |
138 | }; | |
139 | ||
3be1ecf2 | 140 | clock_aud: clock-controller@128c0000 { |
16d7ff26 RS |
141 | compatible = "samsung,exynos5260-clock-aud"; |
142 | reg = <0x128C0000 0x10000>; | |
143 | #clock-cells = <1>; | |
144 | }; | |
145 | ||
3be1ecf2 | 146 | clock_isp: clock-controller@133c0000 { |
16d7ff26 RS |
147 | compatible = "samsung,exynos5260-clock-isp"; |
148 | reg = <0x133C0000 0x10000>; | |
149 | #clock-cells = <1>; | |
150 | }; | |
151 | ||
3be1ecf2 | 152 | clock_gscl: clock-controller@13f00000 { |
16d7ff26 RS |
153 | compatible = "samsung,exynos5260-clock-gscl"; |
154 | reg = <0x13F00000 0x10000>; | |
155 | #clock-cells = <1>; | |
156 | }; | |
157 | ||
158 | clock_disp: clock-controller@14550000 { | |
159 | compatible = "samsung,exynos5260-clock-disp"; | |
160 | reg = <0x14550000 0x10000>; | |
161 | #clock-cells = <1>; | |
162 | }; | |
163 | ||
164 | gic: interrupt-controller@10481000 { | |
165 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | |
166 | #interrupt-cells = <3>; | |
167 | #address-cells = <0>; | |
168 | #size-cells = <0>; | |
169 | interrupt-controller; | |
170 | reg = <0x10481000 0x1000>, | |
387720c9 | 171 | <0x10482000 0x2000>, |
16d7ff26 RS |
172 | <0x10484000 0x2000>, |
173 | <0x10486000 0x2000>; | |
7184c42c KK |
174 | interrupts = <GIC_PPI 9 |
175 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
16d7ff26 RS |
176 | }; |
177 | ||
178 | chipid: chipid@10000000 { | |
179 | compatible = "samsung,exynos4210-chipid"; | |
180 | reg = <0x10000000 0x100>; | |
181 | }; | |
182 | ||
3be1ecf2 | 183 | mct: mct@100b0000 { |
16d7ff26 RS |
184 | compatible = "samsung,exynos4210-mct"; |
185 | reg = <0x100B0000 0x1000>; | |
186 | clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; | |
187 | clock-names = "fin_pll", "mct"; | |
7184c42c KK |
188 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
189 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
190 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
191 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
192 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
193 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
194 | <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, | |
195 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, | |
196 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, | |
197 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, | |
198 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
199 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; | |
16d7ff26 RS |
200 | }; |
201 | ||
3be1ecf2 | 202 | cci: cci@10f00000 { |
16d7ff26 RS |
203 | compatible = "arm,cci-400"; |
204 | #address-cells = <1>; | |
205 | #size-cells = <1>; | |
206 | reg = <0x10F00000 0x1000>; | |
207 | ranges = <0x0 0x10F00000 0x6000>; | |
208 | ||
209 | cci_control0: slave-if@4000 { | |
210 | compatible = "arm,cci-400-ctrl-if"; | |
211 | interface-type = "ace"; | |
212 | reg = <0x4000 0x1000>; | |
213 | }; | |
214 | ||
215 | cci_control1: slave-if@5000 { | |
216 | compatible = "arm,cci-400-ctrl-if"; | |
217 | interface-type = "ace"; | |
218 | reg = <0x5000 0x1000>; | |
219 | }; | |
220 | }; | |
221 | ||
222 | pinctrl_0: pinctrl@11600000 { | |
223 | compatible = "samsung,exynos5260-pinctrl"; | |
224 | reg = <0x11600000 0x1000>; | |
7184c42c | 225 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
16d7ff26 RS |
226 | |
227 | wakeup-interrupt-controller { | |
228 | compatible = "samsung,exynos4210-wakeup-eint"; | |
229 | interrupt-parent = <&gic>; | |
b7ed69d6 | 230 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
16d7ff26 RS |
231 | }; |
232 | }; | |
233 | ||
234 | pinctrl_1: pinctrl@12290000 { | |
235 | compatible = "samsung,exynos5260-pinctrl"; | |
236 | reg = <0x12290000 0x1000>; | |
7184c42c | 237 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
16d7ff26 RS |
238 | }; |
239 | ||
3be1ecf2 | 240 | pinctrl_2: pinctrl@128b0000 { |
16d7ff26 RS |
241 | compatible = "samsung,exynos5260-pinctrl"; |
242 | reg = <0x128B0000 0x1000>; | |
7184c42c | 243 | interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; |
16d7ff26 RS |
244 | }; |
245 | ||
3be1ecf2 | 246 | pmu_system_controller: system-controller@10d50000 { |
fbe4e9f5 VS |
247 | compatible = "samsung,exynos5260-pmu", "syscon"; |
248 | reg = <0x10D50000 0x10000>; | |
249 | }; | |
250 | ||
3be1ecf2 | 251 | uart0: serial@12c00000 { |
16d7ff26 RS |
252 | compatible = "samsung,exynos4210-uart"; |
253 | reg = <0x12C00000 0x100>; | |
7184c42c | 254 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
16d7ff26 RS |
255 | clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; |
256 | clock-names = "uart", "clk_uart_baud0"; | |
257 | status = "disabled"; | |
258 | }; | |
259 | ||
3be1ecf2 | 260 | uart1: serial@12c10000 { |
16d7ff26 RS |
261 | compatible = "samsung,exynos4210-uart"; |
262 | reg = <0x12C10000 0x100>; | |
7184c42c | 263 | interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; |
16d7ff26 RS |
264 | clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; |
265 | clock-names = "uart", "clk_uart_baud0"; | |
266 | status = "disabled"; | |
267 | }; | |
268 | ||
3be1ecf2 | 269 | uart2: serial@12c20000 { |
16d7ff26 RS |
270 | compatible = "samsung,exynos4210-uart"; |
271 | reg = <0x12C20000 0x100>; | |
7184c42c | 272 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
16d7ff26 RS |
273 | clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; |
274 | clock-names = "uart", "clk_uart_baud0"; | |
275 | status = "disabled"; | |
276 | }; | |
277 | ||
278 | uart3: serial@12860000 { | |
279 | compatible = "samsung,exynos4210-uart"; | |
280 | reg = <0x12860000 0x100>; | |
7184c42c | 281 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
16d7ff26 RS |
282 | clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; |
283 | clock-names = "uart", "clk_uart_baud0"; | |
284 | status = "disabled"; | |
285 | }; | |
286 | ||
287 | mmc_0: mmc@12140000 { | |
288 | compatible = "samsung,exynos5250-dw-mshc"; | |
289 | reg = <0x12140000 0x2000>; | |
7184c42c | 290 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
16d7ff26 RS |
291 | #address-cells = <1>; |
292 | #size-cells = <0>; | |
293 | clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; | |
294 | clock-names = "biu", "ciu"; | |
17c130a1 SM |
295 | assigned-clocks = |
296 | <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>, | |
297 | <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>, | |
298 | <&clock_top TOP_SCLK_MMC0>; | |
299 | assigned-clock-parents = | |
300 | <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, | |
301 | <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>; | |
302 | assigned-clock-rates = <0>, <0>, <800000000>; | |
16d7ff26 RS |
303 | fifo-depth = <64>; |
304 | status = "disabled"; | |
305 | }; | |
306 | ||
307 | mmc_1: mmc@12150000 { | |
308 | compatible = "samsung,exynos5250-dw-mshc"; | |
309 | reg = <0x12150000 0x2000>; | |
7184c42c | 310 | interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; |
16d7ff26 RS |
311 | #address-cells = <1>; |
312 | #size-cells = <0>; | |
313 | clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; | |
314 | clock-names = "biu", "ciu"; | |
17c130a1 SM |
315 | assigned-clocks = |
316 | <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>, | |
317 | <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>, | |
318 | <&clock_top TOP_SCLK_MMC1>; | |
319 | assigned-clock-parents = | |
320 | <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, | |
321 | <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>; | |
322 | assigned-clock-rates = <0>, <0>, <800000000>; | |
16d7ff26 RS |
323 | fifo-depth = <64>; |
324 | status = "disabled"; | |
325 | }; | |
326 | ||
327 | mmc_2: mmc@12160000 { | |
328 | compatible = "samsung,exynos5250-dw-mshc"; | |
329 | reg = <0x12160000 0x2000>; | |
7184c42c | 330 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
16d7ff26 RS |
331 | #address-cells = <1>; |
332 | #size-cells = <0>; | |
333 | clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; | |
334 | clock-names = "biu", "ciu"; | |
17c130a1 SM |
335 | assigned-clocks = |
336 | <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>, | |
337 | <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>, | |
338 | <&clock_top TOP_SCLK_MMC2>; | |
339 | assigned-clock-parents = | |
340 | <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, | |
341 | <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>; | |
342 | assigned-clock-rates = <0>, <0>, <800000000>; | |
16d7ff26 RS |
343 | fifo-depth = <64>; |
344 | status = "disabled"; | |
345 | }; | |
c5432b1d SM |
346 | |
347 | hsi2c_0: hsi2c@12da0000 { | |
348 | compatible = "samsung,exynos5260-hsi2c"; | |
349 | reg = <0x12DA0000 0x1000>; | |
350 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
351 | #address-cells = <1>; | |
352 | #size-cells = <0>; | |
353 | pinctrl-names = "default"; | |
354 | pinctrl-0 = <&i2c0_hs_bus>; | |
355 | clocks = <&clock_peri PERI_CLK_HSIC0>; | |
356 | clock-names = "hsi2c"; | |
357 | status = "disabled"; | |
358 | }; | |
359 | ||
360 | hsi2c_1: hsi2c@12db0000 { | |
361 | compatible = "samsung,exynos5260-hsi2c"; | |
362 | reg = <0x12DB0000 0x1000>; | |
363 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
364 | #address-cells = <1>; | |
365 | #size-cells = <0>; | |
366 | pinctrl-names = "default"; | |
367 | pinctrl-0 = <&i2c1_hs_bus>; | |
368 | clocks = <&clock_peri PERI_CLK_HSIC1>; | |
369 | clock-names = "hsi2c"; | |
370 | status = "disabled"; | |
371 | }; | |
372 | ||
373 | hsi2c_2: hsi2c@12dc0000 { | |
374 | compatible = "samsung,exynos5260-hsi2c"; | |
375 | reg = <0x12DC0000 0x1000>; | |
376 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
377 | #address-cells = <1>; | |
378 | #size-cells = <0>; | |
379 | pinctrl-names = "default"; | |
380 | pinctrl-0 = <&i2c2_hs_bus>; | |
381 | clocks = <&clock_peri PERI_CLK_HSIC2>; | |
382 | clock-names = "hsi2c"; | |
383 | status = "disabled"; | |
384 | }; | |
385 | ||
386 | hsi2c_3: hsi2c@12dd0000 { | |
387 | compatible = "samsung,exynos5260-hsi2c"; | |
388 | reg = <0x12DD0000 0x1000>; | |
389 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
390 | #address-cells = <1>; | |
391 | #size-cells = <0>; | |
392 | pinctrl-names = "default"; | |
393 | pinctrl-0 = <&i2c3_hs_bus>; | |
394 | clocks = <&clock_peri PERI_CLK_HSIC3>; | |
395 | clock-names = "hsi2c"; | |
396 | status = "disabled"; | |
397 | }; | |
16d7ff26 RS |
398 | }; |
399 | }; | |
400 | ||
401 | #include "exynos5260-pinctrl.dtsi" |