[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / exynos5410.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * SAMSUNG EXYNOS5410 SoC device tree source
 *
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
 * EXYNOS5410 based board files can include this file and provide
 * values for board specfic bindings.
 */

#include "exynos54xx.dtsi"
#include <dt-bindings/clock/exynos5410.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "samsung,exynos5410", "samsung,exynos5";
	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
		pinctrl3 = &pinctrl_3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;
			clock-frequency = <1600000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x1>;
			clock-frequency = <1600000000>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x2>;
			clock-frequency = <1600000000>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x3>;
			clock-frequency = <1600000000>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		pmu_system_controller: system-controller@10040000 {
			compatible = "samsung,exynos5410-pmu", "syscon";
			reg = <0x10040000 0x5000>;
			clock-names = "clkout16";
			clocks = <&fin_pll>;
			#clock-cells = <1>;
		};

		clock: clock-controller@10010000 {
			compatible = "samsung,exynos5410-clock";
			reg = <0x10010000 0x30000>;
			#clock-cells = <1>;
		};

		clock_audss: audss-clock-controller@3810000 {
			compatible = "samsung,exynos5410-audss-clock";
			reg = <0x03810000 0x0C>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
			clock-names = "pll_ref", "pll_in";
		};

		tmu_cpu0: tmu@10060000 {
			compatible = "samsung,exynos5420-tmu";
			reg = <0x10060000 0x100>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock CLK_TMU>;
			clock-names = "tmu_apbif";
			#include "exynos4412-tmu-sensor-conf.dtsi"
		};

		tmu_cpu1: tmu@10064000 {
			compatible = "samsung,exynos5420-tmu";
			reg = <0x10064000 0x100>;
			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock CLK_TMU>;
			clock-names = "tmu_apbif";
			#include "exynos4412-tmu-sensor-conf.dtsi"
		};

		tmu_cpu2: tmu@10068000 {
			compatible = "samsung,exynos5420-tmu";
			reg = <0x10068000 0x100>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock CLK_TMU>;
			clock-names = "tmu_apbif";
			#include "exynos4412-tmu-sensor-conf.dtsi"
		};

		tmu_cpu3: tmu@1006c000 {
			compatible = "samsung,exynos5420-tmu";
			reg = <0x1006c000 0x100>;
			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock CLK_TMU>;
			clock-names = "tmu_apbif";
			#include "exynos4412-tmu-sensor-conf.dtsi"
		};

		mmc_0: mmc@12200000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12200000 0x1000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			status = "disabled";
		};

		mmc_1: mmc@12210000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12210000 0x1000>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			status = "disabled";
		};

		mmc_2: mmc@12220000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12220000 0x1000>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			status = "disabled";
		};

		pinctrl_0: pinctrl@13400000 {
			compatible = "samsung,exynos5410-pinctrl";
			reg = <0x13400000 0x1000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos4210-wakeup-eint";
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		pinctrl_1: pinctrl@14000000 {
			compatible = "samsung,exynos5410-pinctrl";
			reg = <0x14000000 0x1000>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_2: pinctrl@10d10000 {
			compatible = "samsung,exynos5410-pinctrl";
			reg = <0x10d10000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_3: pinctrl@3860000 {
			compatible = "samsung,exynos5410-pinctrl";
			reg = <0x03860000 0x1000>;
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
		};

		amba {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			interrupt-parent = <&gic>;
			ranges;

			pdma0: pdma@121a0000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x121a0000 0x1000>;
				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clock CLK_PDMA0>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};

			pdma1: pdma@121b0000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x121b0000 0x1000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clock CLK_PDMA1>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};
		};

		audi2s0: i2s@3830000 {
			compatible = "samsung,exynos5420-i2s";
			reg = <0x03830000 0x100>;
			dmas = <&pdma0 10
				&pdma0 9
				&pdma0 8>;
			dma-names = "tx", "rx", "tx-sec";
			clocks = <&clock_audss EXYNOS_I2S_BUS>,
				<&clock_audss EXYNOS_I2S_BUS>,
				<&clock_audss EXYNOS_SCLK_I2S>;
			clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
			#clock-cells = <1>;
			clock-output-names = "i2s_cdclk0";
			#sound-dai-cells = <1>;
			samsung,idma-addr = <0x03000000>;
			pinctrl-names = "default";
			pinctrl-0 = <&audi2s0_bus>;
			status = "disabled";
		};
	};

	thermal-zones {
		cpu0_thermal: cpu0-thermal {
			thermal-sensors = <&tmu_cpu0>;
			#include "exynos5420-trip-points.dtsi"
		};
		cpu1_thermal: cpu1-thermal {
		       thermal-sensors = <&tmu_cpu1>;
		       #include "exynos5420-trip-points.dtsi"
		};
		cpu2_thermal: cpu2-thermal {
		       thermal-sensors = <&tmu_cpu2>;
		       #include "exynos5420-trip-points.dtsi"
		};
		cpu3_thermal: cpu3-thermal {
		       thermal-sensors = <&tmu_cpu3>;
		       #include "exynos5420-trip-points.dtsi"
		};
	};
};

&arm_a15_pmu {
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	status = "okay";
};

&i2c_0 {
	clocks = <&clock CLK_I2C0>;
	clock-names = "i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_bus>;
};

&i2c_1 {
	clocks = <&clock CLK_I2C1>;
	clock-names = "i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_bus>;
};

&i2c_2 {
	clocks = <&clock CLK_I2C2>;
	clock-names = "i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_bus>;
};

&i2c_3 {
	clocks = <&clock CLK_I2C3>;
	clock-names = "i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_bus>;
};

&hsi2c_4 {
	clocks = <&clock CLK_USI0>;
	clock-names = "hsi2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_hs_bus>;
};

&hsi2c_5 {
	clocks = <&clock CLK_USI1>;
	clock-names = "hsi2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c5_hs_bus>;
};

&hsi2c_6 {
	clocks = <&clock CLK_USI2>;
	clock-names = "hsi2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c6_hs_bus>;
};

&hsi2c_7 {
	clocks = <&clock CLK_USI3>;
	clock-names = "hsi2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c7_hs_bus>;
};

&mct {
	clocks = <&fin_pll>, <&clock CLK_MCT>;
	clock-names = "fin_pll", "mct";
};

&prng {
	clocks = <&clock CLK_SSS>;
	clock-names = "secss";
};

&pwm {
	clocks = <&clock CLK_PWM>;
	clock-names = "timers";
};

&rtc {
	clocks = <&clock CLK_RTC>;
	clock-names = "rtc";
	status = "disabled";
};

&serial_0 {
	clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
	clock-names = "uart", "clk_uart_baud0";
	dmas = <&pdma0 13>, <&pdma0 14>;
	dma-names = "rx", "tx";
};

&serial_1 {
	clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
	clock-names = "uart", "clk_uart_baud0";
	dmas = <&pdma1 15>, <&pdma1 16>;
	dma-names = "rx", "tx";
};

&serial_2 {
	clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
	clock-names = "uart", "clk_uart_baud0";
	dmas = <&pdma0 15>, <&pdma0 16>;
	dma-names = "rx", "tx";
};

&serial_3 {
	clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
	clock-names = "uart", "clk_uart_baud0";
	dmas = <&pdma1 17>, <&pdma1 18>;
	dma-names = "rx", "tx";
};

&sss {
	clocks = <&clock CLK_SSS>;
	clock-names = "secss";
};

&sromc {
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x04000000 0x20000
		  1 0 0x05000000 0x20000
		  2 0 0x06000000 0x20000
		  3 0 0x07000000 0x20000>;
};

&trng {
	clocks = <&clock CLK_SSS>;
	clock-names = "secss";
};

&usbdrd3_0 {
	clocks = <&clock CLK_USBD300>;
	clock-names = "usbdrd30";
};

&usbdrd_phy0 {
	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
	clock-names = "phy", "ref";
	samsung,pmu-syscon = <&pmu_system_controller>;
};

&usbdrd3_1 {
	clocks = <&clock CLK_USBD301>;
	clock-names = "usbdrd30";
};

&usbdrd_dwc3_1 {
	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
};

&usbdrd_phy1 {
	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
	clock-names = "phy", "ref";
	samsung,pmu-syscon = <&pmu_system_controller>;
};

&usbhost1 {
	clocks = <&clock CLK_USBH20>;
	clock-names = "usbhost";
};

&usbhost2 {
	clocks = <&clock CLK_USBH20>;
	clock-names = "usbhost";
};

&usb2_phy {
	clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
	clock-names = "phy", "ref";
	samsung,sysreg-phandle = <&sysreg_system_controller>;
	samsung,pmureg-phandle = <&pmu_system_controller>;
};

&watchdog {
	clocks = <&clock CLK_WDT>;
	clock-names = "watchdog";
	samsung,syscon-phandle = <&pmu_system_controller>;
};

#include "exynos5410-pinctrl.dtsi"
#include "exynos-syscon-restart.dtsi"
Commit	Line	Data
cc4637f7	1	// SPDX-License-Identifier: GPL-2.0
107e6aad TD	2	/*
	3	* SAMSUNG EXYNOS5410 SoC device tree source
	4	*
	5	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	6	* http://www.samsung.com
	7	*
	8	* SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
	9	* EXYNOS5410 based board files can include this file and provide
	10	* values for board specfic bindings.
107e6aad TD	11	*/
107e6aad TD	12
c9cf996d	13	#include "exynos54xx.dtsi"
107e6aad	14	#include <dt-bindings/clock/exynos5410.h>
ad3b5ef7	15	#include <dt-bindings/clock/exynos-audss-clk.h>
e5995e6d	16	#include <dt-bindings/interrupt-controller/arm-gic.h>
107e6aad TD	17
	18	/ {
	19	compatible = "samsung,exynos5410", "samsung,exynos5";
	20	interrupt-parent = <&gic>;
	21
1e64f48e	22	aliases {
1eca825f HK	23	pinctrl0 = &pinctrl_0;
	24	pinctrl1 = &pinctrl_1;
	25	pinctrl2 = &pinctrl_2;
	26	pinctrl3 = &pinctrl_3;
1e64f48e TF	27	};
1e64f48e TF	28
107e6aad TD	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
c37ccce1	33	cpu0: cpu@0 {
107e6aad TD	34	device_type = "cpu";
	35	compatible = "arm,cortex-a15";
	36	reg = <0x0>;
22298d6a	37	clock-frequency = <1600000000>;
107e6aad TD	38	};
107e6aad TD	39
c37ccce1	40	cpu1: cpu@1 {
107e6aad TD	41	device_type = "cpu";
	42	compatible = "arm,cortex-a15";
	43	reg = <0x1>;
22298d6a	44	clock-frequency = <1600000000>;
107e6aad TD	45	};
107e6aad TD	46
c37ccce1	47	cpu2: cpu@2 {
107e6aad TD	48	device_type = "cpu";
	49	compatible = "arm,cortex-a15";
	50	reg = <0x2>;
22298d6a	51	clock-frequency = <1600000000>;
107e6aad TD	52	};
107e6aad TD	53
c37ccce1	54	cpu3: cpu@3 {
107e6aad TD	55	device_type = "cpu";
	56	compatible = "arm,cortex-a15";
	57	reg = <0x3>;
22298d6a	58	clock-frequency = <1600000000>;
107e6aad TD	59	};
	60	};
	61
	62	soc: soc {
	63	compatible = "simple-bus";
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	ranges;
	67
0a8f5941 AF	68	pmu_system_controller: system-controller@10040000 {
	69	compatible = "samsung,exynos5410-pmu", "syscon";
	70	reg = <0x10040000 0x5000>;
2cbc0de1 KK	71	clock-names = "clkout16";
	72	clocks = <&fin_pll>;
	73	#clock-cells = <1>;
0a8f5941 AF	74	};
0a8f5941 AF	75
107e6aad TD	76	clock: clock-controller@10010000 {
	77	compatible = "samsung,exynos5410-clock";
	78	reg = <0x10010000 0x30000>;
	79	#clock-cells = <1>;
	80	};
	81
ad3b5ef7 SN	82	clock_audss: audss-clock-controller@3810000 {
	83	compatible = "samsung,exynos5410-audss-clock";
	84	reg = <0x03810000 0x0C>;
	85	#clock-cells = <1>;
	86	clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
	87	clock-names = "pll_ref", "pll_in";
	88	};
	89
c1a3b068 KK	90	tmu_cpu0: tmu@10060000 {
	91	compatible = "samsung,exynos5420-tmu";
	92	reg = <0x10060000 0x100>;
6abdf8d1	93	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
c1a3b068 KK	94	clocks = <&clock CLK_TMU>;
	95	clock-names = "tmu_apbif";
	96	#include "exynos4412-tmu-sensor-conf.dtsi"
	97	};
	98
	99	tmu_cpu1: tmu@10064000 {
	100	compatible = "samsung,exynos5420-tmu";
	101	reg = <0x10064000 0x100>;
6abdf8d1	102	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
c1a3b068 KK	103	clocks = <&clock CLK_TMU>;
	104	clock-names = "tmu_apbif";
	105	#include "exynos4412-tmu-sensor-conf.dtsi"
	106	};
	107
	108	tmu_cpu2: tmu@10068000 {
	109	compatible = "samsung,exynos5420-tmu";
	110	reg = <0x10068000 0x100>;
6abdf8d1	111	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
c1a3b068 KK	112	clocks = <&clock CLK_TMU>;
	113	clock-names = "tmu_apbif";
	114	#include "exynos4412-tmu-sensor-conf.dtsi"
	115	};
	116
	117	tmu_cpu3: tmu@1006c000 {
	118	compatible = "samsung,exynos5420-tmu";
	119	reg = <0x1006c000 0x100>;
6abdf8d1	120	interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
c1a3b068 KK	121	clocks = <&clock CLK_TMU>;
	122	clock-names = "tmu_apbif";
	123	#include "exynos4412-tmu-sensor-conf.dtsi"
	124	};
	125
107e6aad TD	126	mmc_0: mmc@12200000 {
	127	compatible = "samsung,exynos5250-dw-mshc";
	128	reg = <0x12200000 0x1000>;
888950b0	129	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
107e6aad TD	130	#address-cells = <1>;
	131	#size-cells = <0>;
	132	clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
	133	clock-names = "biu", "ciu";
	134	fifo-depth = <0x80>;
	135	status = "disabled";
	136	};
	137
	138	mmc_1: mmc@12210000 {
	139	compatible = "samsung,exynos5250-dw-mshc";
	140	reg = <0x12210000 0x1000>;
888950b0	141	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
107e6aad TD	142	#address-cells = <1>;
	143	#size-cells = <0>;
	144	clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
	145	clock-names = "biu", "ciu";
	146	fifo-depth = <0x80>;
	147	status = "disabled";
	148	};
	149
	150	mmc_2: mmc@12220000 {
	151	compatible = "samsung,exynos5250-dw-mshc";
	152	reg = <0x12220000 0x1000>;
888950b0	153	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
107e6aad TD	154	#address-cells = <1>;
	155	#size-cells = <0>;
	156	clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
	157	clock-names = "biu", "ciu";
	158	fifo-depth = <0x80>;
	159	status = "disabled";
	160	};
	161
1eca825f HK	162	pinctrl_0: pinctrl@13400000 {
	163	compatible = "samsung,exynos5410-pinctrl";
	164	reg = <0x13400000 0x1000>;
888950b0	165	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1eca825f HK	166
	167	wakeup-interrupt-controller {
	168	compatible = "samsung,exynos4210-wakeup-eint";
	169	interrupt-parent = <&gic>;
888950b0	170	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1eca825f HK	171	};
	172	};
	173
	174	pinctrl_1: pinctrl@14000000 {
	175	compatible = "samsung,exynos5410-pinctrl";
	176	reg = <0x14000000 0x1000>;
888950b0	177	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1eca825f HK	178	};
	179
	180	pinctrl_2: pinctrl@10d10000 {
	181	compatible = "samsung,exynos5410-pinctrl";
	182	reg = <0x10d10000 0x1000>;
888950b0	183	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1eca825f HK	184	};
1eca825f HK	185
8dccafaa	186	pinctrl_3: pinctrl@3860000 {
1eca825f HK	187	compatible = "samsung,exynos5410-pinctrl";
1eca825f HK	188	reg = <0x03860000 0x1000>;
888950b0	189	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1eca825f	190	};
ad3b5ef7 SN	191
	192	amba {
	193	#address-cells = <1>;
	194	#size-cells = <1>;
	195	compatible = "simple-bus";
	196	interrupt-parent = <&gic>;
	197	ranges;
	198
11d9d51d	199	pdma0: pdma@121a0000 {
ad3b5ef7	200	compatible = "arm,pl330", "arm,primecell";
11d9d51d	201	reg = <0x121a0000 0x1000>;
8e35c48e	202	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
ad3b5ef7 SN	203	clocks = <&clock CLK_PDMA0>;
	204	clock-names = "apb_pclk";
	205	#dma-cells = <1>;
	206	#dma-channels = <8>;
	207	#dma-requests = <32>;
	208	};
	209
11d9d51d	210	pdma1: pdma@121b0000 {
ad3b5ef7	211	compatible = "arm,pl330", "arm,primecell";
11d9d51d	212	reg = <0x121b0000 0x1000>;
8e35c48e	213	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
ad3b5ef7 SN	214	clocks = <&clock CLK_PDMA1>;
	215	clock-names = "apb_pclk";
	216	#dma-cells = <1>;
	217	#dma-channels = <8>;
	218	#dma-requests = <32>;
	219	};
	220	};
	221
8dccafaa	222	audi2s0: i2s@3830000 {
ad3b5ef7 SN	223	compatible = "samsung,exynos5420-i2s";
	224	reg = <0x03830000 0x100>;
	225	dmas = <&pdma0 10
	226	&pdma0 9
	227	&pdma0 8>;
	228	dma-names = "tx", "rx", "tx-sec";
	229	clocks = <&clock_audss EXYNOS_I2S_BUS>,
	230	<&clock_audss EXYNOS_I2S_BUS>,
	231	<&clock_audss EXYNOS_SCLK_I2S>;
	232	clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
	233	#clock-cells = <1>;
	234	clock-output-names = "i2s_cdclk0";
	235	#sound-dai-cells = <1>;
	236	samsung,idma-addr = <0x03000000>;
	237	pinctrl-names = "default";
	238	pinctrl-0 = <&audi2s0_bus>;
	239	status = "disabled";
	240	};
88ad58ba	241	};
c1a3b068 KK	242
	243	thermal-zones {
	244	cpu0_thermal: cpu0-thermal {
	245	thermal-sensors = <&tmu_cpu0>;
	246	#include "exynos5420-trip-points.dtsi"
	247	};
	248	cpu1_thermal: cpu1-thermal {
	249	thermal-sensors = <&tmu_cpu1>;
	250	#include "exynos5420-trip-points.dtsi"
	251	};
	252	cpu2_thermal: cpu2-thermal {
	253	thermal-sensors = <&tmu_cpu2>;
	254	#include "exynos5420-trip-points.dtsi"
	255	};
	256	cpu3_thermal: cpu3-thermal {
	257	thermal-sensors = <&tmu_cpu3>;
	258	#include "exynos5420-trip-points.dtsi"
	259	};
	260	};
88ad58ba	261	};
1eca825f	262
c4f2fc00 MM	263	&arm_a15_pmu {
	264	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	265	status = "okay";
	266	};
	267
e1e146b1 KK	268	&i2c_0 {
	269	clocks = <&clock CLK_I2C0>;
	270	clock-names = "i2c";
	271	pinctrl-names = "default";
	272	pinctrl-0 = <&i2c0_bus>;
	273	};
	274
	275	&i2c_1 {
	276	clocks = <&clock CLK_I2C1>;
	277	clock-names = "i2c";
	278	pinctrl-names = "default";
	279	pinctrl-0 = <&i2c1_bus>;
	280	};
	281
	282	&i2c_2 {
	283	clocks = <&clock CLK_I2C2>;
	284	clock-names = "i2c";
	285	pinctrl-names = "default";
	286	pinctrl-0 = <&i2c2_bus>;
	287	};
	288
	289	&i2c_3 {
	290	clocks = <&clock CLK_I2C3>;
	291	clock-names = "i2c";
	292	pinctrl-names = "default";
	293	pinctrl-0 = <&i2c3_bus>;
	294	};
	295
	296	&hsi2c_4 {
	297	clocks = <&clock CLK_USI0>;
	298	clock-names = "hsi2c";
	299	pinctrl-names = "default";
	300	pinctrl-0 = <&i2c4_hs_bus>;
	301	};
	302
	303	&hsi2c_5 {
	304	clocks = <&clock CLK_USI1>;
	305	clock-names = "hsi2c";
	306	pinctrl-names = "default";
	307	pinctrl-0 = <&i2c5_hs_bus>;
	308	};
	309
	310	&hsi2c_6 {
	311	clocks = <&clock CLK_USI2>;
	312	clock-names = "hsi2c";
	313	pinctrl-names = "default";
	314	pinctrl-0 = <&i2c6_hs_bus>;
	315	};
	316
	317	&hsi2c_7 {
	318	clocks = <&clock CLK_USI3>;
	319	clock-names = "hsi2c";
	320	pinctrl-names = "default";
	321	pinctrl-0 = <&i2c7_hs_bus>;
	322	};
	323
c9cf996d KK	324	&mct {
	325	clocks = <&fin_pll>, <&clock CLK_MCT>;
	326	clock-names = "fin_pll", "mct";
	327	};
	328
465def2a ŁS	329	&prng {
	330	clocks = <&clock CLK_SSS>;
	331	clock-names = "secss";
	332	};
	333
88ad58ba KK	334	&pwm {
	335	clocks = <&clock CLK_PWM>;
	336	clock-names = "timers";
	337	};
107e6aad	338
e1e146b1 KK	339	&rtc {
	340	clocks = <&clock CLK_RTC>;
	341	clock-names = "rtc";
e1e146b1 KK	342	status = "disabled";
	343	};
	344
88ad58ba KK	345	&serial_0 {
	346	clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
	347	clock-names = "uart", "clk_uart_baud0";
3590312f MS	348	dmas = <&pdma0 13>, <&pdma0 14>;
3590312f MS	349	dma-names = "rx", "tx";
88ad58ba	350	};
107e6aad	351
88ad58ba KK	352	&serial_1 {
	353	clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
	354	clock-names = "uart", "clk_uart_baud0";
3590312f MS	355	dmas = <&pdma1 15>, <&pdma1 16>;
3590312f MS	356	dma-names = "rx", "tx";
88ad58ba KK	357	};
	358
	359	&serial_2 {
	360	clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
	361	clock-names = "uart", "clk_uart_baud0";
3590312f MS	362	dmas = <&pdma0 15>, <&pdma0 16>;
3590312f MS	363	dma-names = "rx", "tx";
88ad58ba KK	364	};
	365
	366	&serial_3 {
594127ad KK	367	clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
594127ad KK	368	clock-names = "uart", "clk_uart_baud0";
3590312f MS	369	dmas = <&pdma1 17>, <&pdma1 18>;
3590312f MS	370	dma-names = "rx", "tx";
88ad58ba KK	371	};
88ad58ba KK	372
b8bd7e23 KK	373	&sss {
	374	clocks = <&clock CLK_SSS>;
	375	clock-names = "secss";
	376	};
	377
88ad58ba KK	378	&sromc {
	379	#address-cells = <2>;
	380	#size-cells = <1>;
	381	ranges = <0 0 0x04000000 0x20000
	382	1 0 0x05000000 0x20000
	383	2 0 0x06000000 0x20000
	384	3 0 0x07000000 0x20000>;
107e6aad	385	};
1eca825f	386
9dc314f6 ŁS	387	&trng {
	388	clocks = <&clock CLK_SSS>;
	389	clock-names = "secss";
	390	};
	391
cb089656 KK	392	&usbdrd3_0 {
	393	clocks = <&clock CLK_USBD300>;
	394	clock-names = "usbdrd30";
	395	};
	396
	397	&usbdrd_phy0 {
	398	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
	399	clock-names = "phy", "ref";
	400	samsung,pmu-syscon = <&pmu_system_controller>;
	401	};
	402
	403	&usbdrd3_1 {
	404	clocks = <&clock CLK_USBD301>;
	405	clock-names = "usbdrd30";
	406	};
	407
e5995e6d	408	&usbdrd_dwc3_1 {
6abdf8d1	409	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
e5995e6d KK	410	};
e5995e6d KK	411
cb089656 KK	412	&usbdrd_phy1 {
	413	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
	414	clock-names = "phy", "ref";
	415	samsung,pmu-syscon = <&pmu_system_controller>;
	416	};
	417
	418	&usbhost1 {
	419	clocks = <&clock CLK_USBH20>;
	420	clock-names = "usbhost";
	421	};
	422
	423	&usbhost2 {
	424	clocks = <&clock CLK_USBH20>;
	425	clock-names = "usbhost";
	426	};
	427
	428	&usb2_phy {
	429	clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
	430	clock-names = "phy", "ref";
	431	samsung,sysreg-phandle = <&sysreg_system_controller>;
	432	samsung,pmureg-phandle = <&pmu_system_controller>;
	433	};
	434
b8bd7e23 KK	435	&watchdog {
	436	clocks = <&clock CLK_WDT>;
	437	clock-names = "watchdog";
	438	samsung,syscon-phandle = <&pmu_system_controller>;
	439	};
	440
1eca825f	441	#include "exynos5410-pinctrl.dtsi"
a03e9dac	442	#include "exynos-syscon-restart.dtsi"