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cc4637f7 | 1 | // SPDX-License-Identifier: GPL-2.0 |
4f0d20ec KK |
2 | /* |
3 | * SAMSUNG EXYNOS5420 SoC cpu device tree source | |
4 | * | |
5 | * Copyright (c) 2015 Samsung Electronics Co., Ltd. | |
6 | * http://www.samsung.com | |
7 | * | |
8 | * This file provides desired ordering for Exynos5420 and Exynos5800 | |
9 | * boards: CPU[0123] being the A15. | |
10 | * | |
11 | * The Exynos5420, 5422 and 5800 actually share the same CPU configuration | |
12 | * but particular boards choose different booting order. | |
13 | * | |
14 | * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 | |
15 | * booting cluster (big or LITTLE) is chosen by IROM code by reading | |
16 | * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting | |
17 | * from the LITTLE: Cortex-A7. | |
4f0d20ec KK |
18 | */ |
19 | ||
20 | / { | |
21 | cpus { | |
22 | #address-cells = <1>; | |
23 | #size-cells = <0>; | |
24 | ||
25 | cpu0: cpu@0 { | |
26 | device_type = "cpu"; | |
27 | compatible = "arm,cortex-a15"; | |
28 | reg = <0x0>; | |
66a4a1fb | 29 | clocks = <&clock CLK_ARM_CLK>; |
4f0d20ec KK |
30 | clock-frequency = <1800000000>; |
31 | cci-control-port = <&cci_control1>; | |
66a4a1fb | 32 | operating-points-v2 = <&cluster_a15_opp_table>; |
65ebf53f | 33 | #cooling-cells = <2>; /* min followed by max */ |
45bfc2a3 | 34 | capacity-dmips-mhz = <1024>; |
4f0d20ec KK |
35 | }; |
36 | ||
37 | cpu1: cpu@1 { | |
38 | device_type = "cpu"; | |
39 | compatible = "arm,cortex-a15"; | |
40 | reg = <0x1>; | |
41 | clock-frequency = <1800000000>; | |
42 | cci-control-port = <&cci_control1>; | |
66a4a1fb | 43 | operating-points-v2 = <&cluster_a15_opp_table>; |
65ebf53f | 44 | #cooling-cells = <2>; /* min followed by max */ |
45bfc2a3 | 45 | capacity-dmips-mhz = <1024>; |
4f0d20ec KK |
46 | }; |
47 | ||
48 | cpu2: cpu@2 { | |
49 | device_type = "cpu"; | |
50 | compatible = "arm,cortex-a15"; | |
51 | reg = <0x2>; | |
52 | clock-frequency = <1800000000>; | |
53 | cci-control-port = <&cci_control1>; | |
66a4a1fb | 54 | operating-points-v2 = <&cluster_a15_opp_table>; |
65ebf53f | 55 | #cooling-cells = <2>; /* min followed by max */ |
45bfc2a3 | 56 | capacity-dmips-mhz = <1024>; |
4f0d20ec KK |
57 | }; |
58 | ||
59 | cpu3: cpu@3 { | |
60 | device_type = "cpu"; | |
61 | compatible = "arm,cortex-a15"; | |
62 | reg = <0x3>; | |
63 | clock-frequency = <1800000000>; | |
64 | cci-control-port = <&cci_control1>; | |
66a4a1fb | 65 | operating-points-v2 = <&cluster_a15_opp_table>; |
65ebf53f | 66 | #cooling-cells = <2>; /* min followed by max */ |
45bfc2a3 | 67 | capacity-dmips-mhz = <1024>; |
4f0d20ec KK |
68 | }; |
69 | ||
70 | cpu4: cpu@100 { | |
71 | device_type = "cpu"; | |
72 | compatible = "arm,cortex-a7"; | |
73 | reg = <0x100>; | |
66a4a1fb | 74 | clocks = <&clock CLK_KFC_CLK>; |
4f0d20ec KK |
75 | clock-frequency = <1000000000>; |
76 | cci-control-port = <&cci_control0>; | |
66a4a1fb | 77 | operating-points-v2 = <&cluster_a7_opp_table>; |
65ebf53f | 78 | #cooling-cells = <2>; /* min followed by max */ |
45bfc2a3 | 79 | capacity-dmips-mhz = <539>; |
4f0d20ec KK |
80 | }; |
81 | ||
82 | cpu5: cpu@101 { | |
83 | device_type = "cpu"; | |
84 | compatible = "arm,cortex-a7"; | |
85 | reg = <0x101>; | |
86 | clock-frequency = <1000000000>; | |
87 | cci-control-port = <&cci_control0>; | |
66a4a1fb | 88 | operating-points-v2 = <&cluster_a7_opp_table>; |
65ebf53f | 89 | #cooling-cells = <2>; /* min followed by max */ |
45bfc2a3 | 90 | capacity-dmips-mhz = <539>; |
4f0d20ec KK |
91 | }; |
92 | ||
93 | cpu6: cpu@102 { | |
94 | device_type = "cpu"; | |
95 | compatible = "arm,cortex-a7"; | |
96 | reg = <0x102>; | |
97 | clock-frequency = <1000000000>; | |
98 | cci-control-port = <&cci_control0>; | |
66a4a1fb | 99 | operating-points-v2 = <&cluster_a7_opp_table>; |
65ebf53f | 100 | #cooling-cells = <2>; /* min followed by max */ |
45bfc2a3 | 101 | capacity-dmips-mhz = <539>; |
4f0d20ec KK |
102 | }; |
103 | ||
104 | cpu7: cpu@103 { | |
105 | device_type = "cpu"; | |
106 | compatible = "arm,cortex-a7"; | |
107 | reg = <0x103>; | |
108 | clock-frequency = <1000000000>; | |
109 | cci-control-port = <&cci_control0>; | |
66a4a1fb | 110 | operating-points-v2 = <&cluster_a7_opp_table>; |
65ebf53f | 111 | #cooling-cells = <2>; /* min followed by max */ |
45bfc2a3 | 112 | capacity-dmips-mhz = <539>; |
4f0d20ec KK |
113 | }; |
114 | }; | |
115 | }; | |
c4f2fc00 MM |
116 | |
117 | &arm_a7_pmu { | |
118 | interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; | |
119 | status = "okay"; | |
120 | }; | |
121 | ||
122 | &arm_a15_pmu { | |
123 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; | |
124 | status = "okay"; | |
125 | }; |