projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 3528dd34 AK |
1 | /* |
| 2 | * Google Peach Pit Rev 6+ board device tree source | |
| 3 | * | |
| 4 | * Copyright (c) 2014 Google, Inc | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | ||
| 11 | /dts-v1/; | |
| 12 | #include <dt-bindings/input/input.h> | |
| 13 | #include <dt-bindings/gpio/gpio.h> | |
| 14 | #include "exynos5420.dtsi" | |
| 15 | ||
| 16 | / { | |
| 17 | model = "Google Peach Pit Rev 6+"; | |
| 18 | ||
| 19 | compatible = "google,pit-rev16", | |
| 20 | "google,pit-rev15", "google,pit-rev14", | |
| 21 | "google,pit-rev13", "google,pit-rev12", | |
| 22 | "google,pit-rev11", "google,pit-rev10", | |
| 23 | "google,pit-rev9", "google,pit-rev8", | |
| 24 | "google,pit-rev7", "google,pit-rev6", | |
| 25 | "google,pit", "google,peach","samsung,exynos5420", | |
| 26 | "samsung,exynos5"; | |
| 27 | ||
| 28 | memory { | |
| 29 | reg = <0x20000000 0x80000000>; | |
| 30 | }; | |
| 31 | ||
| 32 | fixed-rate-clocks { | |
| 33 | oscclk { | |
| 34 | compatible = "samsung,exynos5420-oscclk"; | |
| 35 | clock-frequency = <24000000>; | |
| 36 | }; | |
| 37 | }; | |
| 38 | ||
| 39 | gpio-keys { | |
| 40 | compatible = "gpio-keys"; | |
| 41 | ||
| 42 | pinctrl-names = "default"; | |
| 43 | pinctrl-0 = <&power_key_irq>; | |
| 44 | ||
| 45 | power { | |
| 46 | label = "Power"; | |
| 47 | gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; | |
| 48 | linux,code = <KEY_POWER>; | |
| 49 | gpio-key,wakeup; | |
| 50 | }; | |
| 51 | }; | |
| 52 | ||
| 53 | backlight { | |
| 54 | compatible = "pwm-backlight"; | |
| 55 | pwms = <&pwm 0 1000000 0>; | |
| 56 | brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; | |
| 57 | default-brightness-level = <7>; | |
| 58 | pinctrl-0 = <&pwm0_out>; | |
| 59 | pinctrl-names = "default"; | |
| 60 | }; | |
| 61 | }; | |
| 62 | ||
| 63 | &pinctrl_0 { | |
| 64 | tpm_irq: tpm-irq { | |
| 65 | samsung,pins = "gpx1-0"; | |
| 66 | samsung,pin-function = <0>; | |
| 67 | samsung,pin-pud = <0>; | |
| 68 | samsung,pin-drv = <0>; | |
| 69 | }; | |
| 70 | ||
| 71 | power_key_irq: power-key-irq { | |
| 72 | samsung,pins = "gpx1-2"; | |
| 73 | samsung,pin-function = <0>; | |
| 74 | samsung,pin-pud = <0>; | |
| 75 | samsung,pin-drv = <0>; | |
| 76 | }; | |
| 77 | }; | |
| 78 | ||
| 79 | &rtc { | |
| 80 | status = "okay"; | |
| 81 | }; | |
| 82 | ||
| 83 | &uart_3 { | |
| 84 | status = "okay"; | |
| 85 | }; | |
| 86 | ||
| 87 | &mmc_0 { | |
| 88 | status = "okay"; | |
| 89 | num-slots = <1>; | |
| 90 | broken-cd; | |
| 91 | caps2-mmc-hs200-1_8v; | |
| 92 | supports-highspeed; | |
| 93 | non-removable; | |
| 94 | card-detect-delay = <200>; | |
| 95 | clock-frequency = <400000000>; | |
| 96 | samsung,dw-mshc-ciu-div = <3>; | |
| 97 | samsung,dw-mshc-sdr-timing = <0 4>; | |
| 98 | samsung,dw-mshc-ddr-timing = <0 2>; | |
| 99 | pinctrl-names = "default"; | |
| 100 | pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; | |
| 101 | ||
| 102 | slot@0 { | |
| 103 | reg = <0>; | |
| 104 | bus-width = <8>; | |
| 105 | }; | |
| 106 | }; | |
| 107 | ||
| 108 | &mmc_2 { | |
| 109 | status = "okay"; | |
| 110 | num-slots = <1>; | |
| 111 | supports-highspeed; | |
| 112 | card-detect-delay = <200>; | |
| 113 | clock-frequency = <400000000>; | |
| 114 | samsung,dw-mshc-ciu-div = <3>; | |
| 115 | samsung,dw-mshc-sdr-timing = <2 3>; | |
| 116 | samsung,dw-mshc-ddr-timing = <1 2>; | |
| 117 | pinctrl-names = "default"; | |
| 118 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; | |
| 119 | ||
| 120 | slot@0 { | |
| 121 | reg = <0>; | |
| 122 | bus-width = <4>; | |
| 123 | }; | |
| 124 | }; | |
| 125 | ||
| 126 | &hsi2c_9 { | |
| 127 | status = "okay"; | |
| 128 | clock-frequency = <400000>; | |
| 129 | ||
| 130 | tpm@20 { | |
| 131 | compatible = "infineon,slb9645tt"; | |
| 132 | reg = <0x20>; | |
| 133 | ||
| 134 | /* Unused irq; but still need to configure the pins */ | |
| 135 | pinctrl-names = "default"; | |
| 136 | pinctrl-0 = <&tpm_irq>; | |
| 137 | }; | |
| 138 | }; | |
| 139 | ||
| 140 | /* | |
| 141 | * Use longest HW watchdog in SoC (32 seconds) since the hardware | |
| 142 | * watchdog provides no debugging information (compared to soft/hard | |
| 143 | * lockup detectors) and so should be last resort. | |
| 144 | */ | |
| 145 | &watchdog { | |
| 146 | timeout-sec = <32>; | |
| 147 | }; |