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Merge tag 'topic/designware-baytrail-2017-03-02' of git://anongit.freedesktop.org...
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / exynos5420.dtsi
CommitLineData
34dcedfb
CK		 1/*
2 * SAMSUNG EXYNOS5420 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
c9cf996d 16#include "exynos54xx.dtsi"
1dd4e599 17#include <dt-bindings/clock/exynos5420.h>
602408e3 18#include <dt-bindings/clock/exynos-audss-clk.h>
e5995e6d 19#include <dt-bindings/interrupt-controller/arm-gic.h>
35e82775 20
34dcedfb 21/ {
8bdb31b4 22 compatible = "samsung,exynos5420", "samsung,exynos5";
34dcedfb 23
d81c6cbe 24 aliases {
0e2c5915
YK		 25 mshc0 = &mmc_0;
26 mshc1 = &mmc_1;
27 mshc2 = &mmc_2;
d81c6cbe
LKA		 28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 pinctrl2 = &pinctrl_2;
31 pinctrl3 = &pinctrl_3;
32 pinctrl4 = &pinctrl_4;
1a9110d6
SK		 33 i2c8 = &hsi2c_8;
34 i2c9 = &hsi2c_9;
35 i2c10 = &hsi2c_10;
01eb4636
LKA		 36 gsc0 = &gsc_0;
37 gsc1 = &gsc_1;
e84a2d91
LKA		 38 spi0 = &spi_0;
39 spi1 = &spi_1;
40 spi2 = &spi_2;
66a4a1fb
TA		 41 };
42
4f0d20ec
KK		 43 /*
44 * The 'cpus' node is not present here but instead it is provided
45 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
46 */
5b56642b 47
5d99cc59
KK		 48 soc: soc {
49 cluster_a15_opp_table: opp_table0 {
50 compatible = "operating-points-v2";
51 opp-shared;
52 opp@1800000000 {
53 opp-hz = /bits/ 64 <1800000000>;
54 opp-microvolt = <1250000>;
55 clock-latency-ns = <140000>;
56 };
57 opp@1700000000 {
58 opp-hz = /bits/ 64 <1700000000>;
59 opp-microvolt = <1212500>;
60 clock-latency-ns = <140000>;
61 };
62 opp@1600000000 {
63 opp-hz = /bits/ 64 <1600000000>;
64 opp-microvolt = <1175000>;
65 clock-latency-ns = <140000>;
66 };
67 opp@1500000000 {
68 opp-hz = /bits/ 64 <1500000000>;
69 opp-microvolt = <1137500>;
70 clock-latency-ns = <140000>;
71 };
72 opp@1400000000 {
73 opp-hz = /bits/ 64 <1400000000>;
74 opp-microvolt = <1112500>;
75 clock-latency-ns = <140000>;
76 };
77 opp@1300000000 {
78 opp-hz = /bits/ 64 <1300000000>;
79 opp-microvolt = <1062500>;
80 clock-latency-ns = <140000>;
81 };
82 opp@1200000000 {
83 opp-hz = /bits/ 64 <1200000000>;
84 opp-microvolt = <1037500>;
85 clock-latency-ns = <140000>;
86 };
87 opp@1100000000 {
88 opp-hz = /bits/ 64 <1100000000>;
89 opp-microvolt = <1012500>;
90 clock-latency-ns = <140000>;
91 };
92 opp@1000000000 {
93 opp-hz = /bits/ 64 <1000000000>;
94 opp-microvolt = < 987500>;
95 clock-latency-ns = <140000>;
96 };
97 opp@900000000 {
98 opp-hz = /bits/ 64 <900000000>;
99 opp-microvolt = < 962500>;
100 clock-latency-ns = <140000>;
101 };
102 opp@800000000 {
103 opp-hz = /bits/ 64 <800000000>;
104 opp-microvolt = < 937500>;
105 clock-latency-ns = <140000>;
106 };
107 opp@700000000 {
108 opp-hz = /bits/ 64 <700000000>;
109 opp-microvolt = < 912500>;
110 clock-latency-ns = <140000>;
111 };
112 };
113
114 cluster_a7_opp_table: opp_table1 {
115 compatible = "operating-points-v2";
116 opp-shared;
117 opp@1300000000 {
118 opp-hz = /bits/ 64 <1300000000>;
119 opp-microvolt = <1275000>;
120 clock-latency-ns = <140000>;
121 };
122 opp@1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <1212500>;
125 clock-latency-ns = <140000>;
126 };
127 opp@1100000000 {
128 opp-hz = /bits/ 64 <1100000000>;
129 opp-microvolt = <1162500>;
130 clock-latency-ns = <140000>;
131 };
132 opp@1000000000 {
133 opp-hz = /bits/ 64 <1000000000>;
134 opp-microvolt = <1112500>;
135 clock-latency-ns = <140000>;
136 };
137 opp@900000000 {
138 opp-hz = /bits/ 64 <900000000>;
139 opp-microvolt = <1062500>;
140 clock-latency-ns = <140000>;
141 };
142 opp@800000000 {
143 opp-hz = /bits/ 64 <800000000>;
144 opp-microvolt = <1025000>;
145 clock-latency-ns = <140000>;
146 };
147 opp@700000000 {
148 opp-hz = /bits/ 64 <700000000>;
149 opp-microvolt = <975000>;
150 clock-latency-ns = <140000>;
151 };
152 opp@600000000 {
153 opp-hz = /bits/ 64 <600000000>;
154 opp-microvolt = <937500>;
155 clock-latency-ns = <140000>;
156 };
157 };
158
159 cci: cci@10d20000 {
160 compatible = "arm,cci-400";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 reg = <0x10d20000 0x1000>;
164 ranges = <0x0 0x10d20000 0x6000>;
165
166 cci_control0: slave-if@4000 {
167 compatible = "arm,cci-400-ctrl-if";
168 interface-type = "ace";
169 reg = <0x4000 0x1000>;
170 };
171 cci_control1: slave-if@5000 {
172 compatible = "arm,cci-400-ctrl-if";
173 interface-type = "ace";
174 reg = <0x5000 0x1000>;
175 };
176 };
177
5d99cc59
KK		 178 clock: clock-controller@10010000 {
179 compatible = "samsung,exynos5420-clock";
180 reg = <0x10010000 0x30000>;
181 #clock-cells = <1>;
182 };
183
184 clock_audss: audss-clock-controller@3810000 {
185 compatible = "samsung,exynos5420-audss-clock";
186 reg = <0x03810000 0x0C>;
187 #clock-cells = <1>;
188 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
189 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
190 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
191 };
192
193 mfc: codec@11000000 {
194 compatible = "samsung,mfc-v7";
195 reg = <0x11000000 0x10000>;
6abdf8d1 196 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 197 clocks = <&clock CLK_MFC>;
198 clock-names = "mfc";
199 power-domains = <&mfc_pd>;
200 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
201 iommu-names = "left", "right";
202 };
203
204 mmc_0: mmc@12200000 {
205 compatible = "samsung,exynos5420-dw-mshc-smu";
6abdf8d1 206 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 207 #address-cells = <1>;
208 #size-cells = <0>;
209 reg = <0x12200000 0x2000>;
210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
211 clock-names = "biu", "ciu";
212 fifo-depth = <0x40>;
213 status = "disabled";
1c0e0854 214 };
b3205dea 215
5d99cc59
KK		 216 mmc_1: mmc@12210000 {
217 compatible = "samsung,exynos5420-dw-mshc-smu";
6abdf8d1 218 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 219 #address-cells = <1>;
220 #size-cells = <0>;
221 reg = <0x12210000 0x2000>;
222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
223 clock-names = "biu", "ciu";
224 fifo-depth = <0x40>;
225 status = "disabled";
b3205dea
SK		 226 };
227
5d99cc59
KK		 228 mmc_2: mmc@12220000 {
229 compatible = "samsung,exynos5420-dw-mshc";
6abdf8d1 230 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 231 #address-cells = <1>;
232 #size-cells = <0>;
233 reg = <0x12220000 0x1000>;
234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
235 clock-names = "biu", "ciu";
236 fifo-depth = <0x40>;
237 status = "disabled";
1c0e0854 238 };
34dcedfb 239
5d99cc59
KK		 240 nocp_mem0_0: nocp@10CA1000 {
241 compatible = "samsung,exynos5420-nocp";
242 reg = <0x10CA1000 0x200>;
243 status = "disabled";
34dcedfb 244 };
f09d062f 245
5d99cc59
KK		 246 nocp_mem0_1: nocp@10CA1400 {
247 compatible = "samsung,exynos5420-nocp";
248 reg = <0x10CA1400 0x200>;
249 status = "disabled";
d81c6cbe 250 };
0e2c5915 251
5d99cc59
KK		 252 nocp_mem1_0: nocp@10CA1800 {
253 compatible = "samsung,exynos5420-nocp";
254 reg = <0x10CA1800 0x200>;
e6015c1f 255 status = "disabled";
e3188533 256 };
0e2c5915 257
5d99cc59
KK		 258 nocp_mem1_1: nocp@10CA1C00 {
259 compatible = "samsung,exynos5420-nocp";
260 reg = <0x10CA1C00 0x200>;
261 status = "disabled";
9843a223 262 };
0e2c5915 263
5d99cc59
KK		 264 nocp_g3d_0: nocp@11A51000 {
265 compatible = "samsung,exynos5420-nocp";
266 reg = <0x11A51000 0x200>;
267 status = "disabled";
34dcedfb 268 };
34dcedfb 269
5d99cc59
KK		 270 nocp_g3d_1: nocp@11A51400 {
271 compatible = "samsung,exynos5420-nocp";
272 reg = <0x11A51400 0x200>;
273 status = "disabled";
f070267b 274 };
f018c987 275
5d99cc59
KK		 276 gsc_pd: power-domain@10044000 {
277 compatible = "samsung,exynos4210-pd";
278 reg = <0x10044000 0x20>;
279 #power-domain-cells = <0>;
55d74adf 280 label = "GSC";
5d99cc59
KK		 281 clocks = <&clock CLK_FIN_PLL>,
282 <&clock CLK_MOUT_USER_ACLK300_GSCL>,
283 <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
284 clock-names = "oscclk", "clk0", "asb0", "asb1";
6674fd92 285 };
f018c987 286
5d99cc59
KK		 287 isp_pd: power-domain@10044020 {
288 compatible = "samsung,exynos4210-pd";
289 reg = <0x10044020 0x20>;
290 #power-domain-cells = <0>;
55d74adf 291 label = "ISP";
6674fd92 292 };
f018c987 293
5d99cc59
KK		 294 mfc_pd: power-domain@10044060 {
295 compatible = "samsung,exynos4210-pd";
296 reg = <0x10044060 0x20>;
95eb940c
OJ		 297 clocks = <&clock CLK_FIN_PLL>,
298 <&clock CLK_MOUT_USER_ACLK333>,
299 <&clock CLK_ACLK333>;
300 clock-names = "oscclk", "clk0","asb0";
5d99cc59 301 #power-domain-cells = <0>;
55d74adf 302 label = "MFC";
b04a62d3 303 };
f018c987 304
5d99cc59
KK		 305 msc_pd: power-domain@10044120 {
306 compatible = "samsung,exynos4210-pd";
307 reg = <0x10044120 0x20>;
308 #power-domain-cells = <0>;
55d74adf 309 label = "MSC";
b04a62d3 310 };
f018c987 311
5d99cc59
KK		 312 disp_pd: power-domain@100440C0 {
313 compatible = "samsung,exynos4210-pd";
314 reg = <0x100440C0 0x20>;
315 #power-domain-cells = <0>;
55d74adf 316 label = "DISP";
5d99cc59
KK		 317 clocks = <&clock CLK_FIN_PLL>,
318 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
319 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
320 <&clock CLK_MOUT_USER_ACLK400_DISP1>,
321 <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
322 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
b04a62d3 323 };
f018c987 324
5d99cc59
KK		 325 pinctrl_0: pinctrl@13400000 {
326 compatible = "samsung,exynos5420-pinctrl";
327 reg = <0x13400000 0x1000>;
6abdf8d1 328 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
dcfca2cc 329
5d99cc59
KK		 330 wakeup-interrupt-controller {
331 compatible = "samsung,exynos4210-wakeup-eint";
332 interrupt-parent = <&gic>;
6abdf8d1 333 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 334 };
b04a62d3 335 };
dcfca2cc 336
5d99cc59
KK		 337 pinctrl_1: pinctrl@13410000 {
338 compatible = "samsung,exynos5420-pinctrl";
339 reg = <0x13410000 0x1000>;
6abdf8d1 340 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
b04a62d3 341 };
dcfca2cc 342
5d99cc59
KK		 343 pinctrl_2: pinctrl@14000000 {
344 compatible = "samsung,exynos5420-pinctrl";
345 reg = <0x14000000 0x1000>;
6abdf8d1 346 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
b04a62d3 347 };
dcfca2cc 348
5d99cc59
KK		 349 pinctrl_3: pinctrl@14010000 {
350 compatible = "samsung,exynos5420-pinctrl";
351 reg = <0x14010000 0x1000>;
6abdf8d1 352 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
b04a62d3 353 };
dcfca2cc 354
5d99cc59
KK		 355 pinctrl_4: pinctrl@03860000 {
356 compatible = "samsung,exynos5420-pinctrl";
357 reg = <0x03860000 0x1000>;
6abdf8d1 358 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
b04a62d3 359 };
d81c6cbe 360
5d99cc59
KK		 361 amba {
362 #address-cells = <1>;
363 #size-cells = <1>;
364 compatible = "simple-bus";
d81c6cbe 365 interrupt-parent = <&gic>;
5d99cc59
KK		 366 ranges;
367
368 adma: adma@03880000 {
369 compatible = "arm,pl330", "arm,primecell";
370 reg = <0x03880000 0x1000>;
6abdf8d1 371 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 372 clocks = <&clock_audss EXYNOS_ADMA>;
373 clock-names = "apb_pclk";
374 #dma-cells = <1>;
375 #dma-channels = <6>;
376 #dma-requests = <16>;
377 };
378
379 pdma0: pdma@121A0000 {
380 compatible = "arm,pl330", "arm,primecell";
381 reg = <0x121A0000 0x1000>;
6abdf8d1 382 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 383 clocks = <&clock CLK_PDMA0>;
384 clock-names = "apb_pclk";
385 #dma-cells = <1>;
386 #dma-channels = <8>;
387 #dma-requests = <32>;
388 };
389
390 pdma1: pdma@121B0000 {
391 compatible = "arm,pl330", "arm,primecell";
392 reg = <0x121B0000 0x1000>;
6abdf8d1 393 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 394 clocks = <&clock CLK_PDMA1>;
395 clock-names = "apb_pclk";
396 #dma-cells = <1>;
397 #dma-channels = <8>;
398 #dma-requests = <32>;
399 };
400
401 mdma0: mdma@10800000 {
402 compatible = "arm,pl330", "arm,primecell";
403 reg = <0x10800000 0x1000>;
6abdf8d1 404 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 405 clocks = <&clock CLK_MDMA0>;
406 clock-names = "apb_pclk";
407 #dma-cells = <1>;
408 #dma-channels = <8>;
409 #dma-requests = <1>;
410 };
411
412 mdma1: mdma@11C10000 {
413 compatible = "arm,pl330", "arm,primecell";
414 reg = <0x11C10000 0x1000>;
6abdf8d1 415 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 416 clocks = <&clock CLK_MDMA1>;
417 clock-names = "apb_pclk";
418 #dma-cells = <1>;
419 #dma-channels = <8>;
420 #dma-requests = <1>;
421 /*
422 * MDMA1 can support both secure and non-secure
423 * AXI transactions. When this is enabled in
424 * the kernel for boards that run in secure
425 * mode, we are getting imprecise external
426 * aborts causing the kernel to oops.
427 */
428 status = "disabled";
429 };
430 };
431
432 i2s0: i2s@03830000 {
433 compatible = "samsung,exynos5420-i2s";
434 reg = <0x03830000 0x100>;
435 dmas = <&adma 0
436 &adma 2
437 &adma 1>;
438 dma-names = "tx", "rx", "tx-sec";
439 clocks = <&clock_audss EXYNOS_I2S_BUS>,
440 <&clock_audss EXYNOS_I2S_BUS>,
441 <&clock_audss EXYNOS_SCLK_I2S>;
442 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
443 #clock-cells = <1>;
444 clock-output-names = "i2s_cdclk0";
445 #sound-dai-cells = <1>;
446 samsung,idma-addr = <0x03000000>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&i2s0_bus>;
449 status = "disabled";
d81c6cbe 450 };
d81c6cbe 451
5d99cc59
KK		 452 i2s1: i2s@12D60000 {
453 compatible = "samsung,exynos5420-i2s";
454 reg = <0x12D60000 0x100>;
455 dmas = <&pdma1 12
456 &pdma1 11>;
457 dma-names = "tx", "rx";
458 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
459 clock-names = "iis", "i2s_opclk0";
460 #clock-cells = <1>;
461 clock-output-names = "i2s_cdclk1";
462 #sound-dai-cells = <1>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&i2s1_bus>;
e6015c1f 465 status = "disabled";
e3188533 466 };
b0e505ce 467
5d99cc59
KK		 468 i2s2: i2s@12D70000 {
469 compatible = "samsung,exynos5420-i2s";
470 reg = <0x12D70000 0x100>;
471 dmas = <&pdma0 12
472 &pdma0 11>;
473 dma-names = "tx", "rx";
474 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
475 clock-names = "iis", "i2s_opclk0";
476 #clock-cells = <1>;
477 clock-output-names = "i2s_cdclk2";
478 #sound-dai-cells = <1>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&i2s2_bus>;
481 status = "disabled";
9843a223 482 };
1d287620 483
5d99cc59
KK		 484 spi_0: spi@12d20000 {
485 compatible = "samsung,exynos4210-spi";
486 reg = <0x12d20000 0x100>;
6abdf8d1 487 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 488 dmas = <&pdma0 5
489 &pdma0 4>;
490 dma-names = "tx", "rx";
491 #address-cells = <1>;
492 #size-cells = <0>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&spi0_bus>;
495 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
496 clock-names = "spi", "spi_busclk0";
497 status = "disabled";
f070267b 498 };
3cb7d1cd 499
5d99cc59
KK		 500 spi_1: spi@12d30000 {
501 compatible = "samsung,exynos4210-spi";
502 reg = <0x12d30000 0x100>;
6abdf8d1 503 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 504 dmas = <&pdma1 5
505 &pdma1 4>;
506 dma-names = "tx", "rx";
507 #address-cells = <1>;
508 #size-cells = <0>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&spi1_bus>;
511 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
512 clock-names = "spi", "spi_busclk0";
513 status = "disabled";
f070267b 514 };
6674fd92 515
5d99cc59
KK		 516 spi_2: spi@12d40000 {
517 compatible = "samsung,exynos4210-spi";
518 reg = <0x12d40000 0x100>;
6abdf8d1 519 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 520 dmas = <&pdma0 7
521 &pdma0 6>;
522 dma-names = "tx", "rx";
523 #address-cells = <1>;
524 #size-cells = <0>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&spi2_bus>;
527 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
528 clock-names = "spi", "spi_busclk0";
529 status = "disabled";
6674fd92 530 };
6674fd92 531
5d99cc59
KK		 532 dp_phy: dp-video-phy {
533 compatible = "samsung,exynos5420-dp-video-phy";
534 samsung,pmu-syscon = <&pmu_system_controller>;
535 #phy-cells = <0>;
6674fd92 536 };
b7004516 537
5d99cc59
KK		 538 mipi_phy: mipi-video-phy {
539 compatible = "samsung,s5pv210-mipi-video-phy";
540 syscon = <&pmu_system_controller>;
541 #phy-cells = <1>;
b04a62d3 542 };
b04a62d3 543
5d99cc59
KK		 544 dsi@14500000 {
545 compatible = "samsung,exynos5410-mipi-dsi";
546 reg = <0x14500000 0x10000>;
6abdf8d1 547 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 548 phys = <&mipi_phy 1>;
549 phy-names = "dsim";
550 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
551 clock-names = "bus_clk", "pll_clk";
552 #address-cells = <1>;
553 #size-cells = <0>;
554 status = "disabled";
b04a62d3 555 };
b04a62d3 556
5d99cc59
KK		 557 adc: adc@12D10000 {
558 compatible = "samsung,exynos-adc-v2";
559 reg = <0x12D10000 0x100>;
6abdf8d1 560 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 561 clocks = <&clock CLK_TSADC>;
562 clock-names = "adc";
563 #io-channel-cells = <1>;
564 io-channel-ranges;
565 samsung,syscon-phandle = <&pmu_system_controller>;
566 status = "disabled";
b04a62d3 567 };
b04a62d3 568
5d99cc59
KK		 569 hsi2c_8: i2c@12E00000 {
570 compatible = "samsung,exynos5250-hsi2c";
571 reg = <0x12E00000 0x1000>;
6abdf8d1 572 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 573 #address-cells = <1>;
574 #size-cells = <0>;
575 pinctrl-names = "default";
576 pinctrl-0 = <&i2c8_hs_bus>;
577 clocks = <&clock CLK_USI4>;
578 clock-names = "hsi2c";
579 status = "disabled";
b04a62d3 580 };
b04a62d3 581
5d99cc59
KK		 582 hsi2c_9: i2c@12E10000 {
583 compatible = "samsung,exynos5250-hsi2c";
584 reg = <0x12E10000 0x1000>;
6abdf8d1 585 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 586 #address-cells = <1>;
587 #size-cells = <0>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&i2c9_hs_bus>;
590 clocks = <&clock CLK_USI5>;
591 clock-names = "hsi2c";
592 status = "disabled";
b04a62d3 593 };
b04a62d3 594
5d99cc59
KK		 595 hsi2c_10: i2c@12E20000 {
596 compatible = "samsung,exynos5250-hsi2c";
597 reg = <0x12E20000 0x1000>;
6abdf8d1 598 interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 599 #address-cells = <1>;
600 #size-cells = <0>;
601 pinctrl-names = "default";
602 pinctrl-0 = <&i2c10_hs_bus>;
603 clocks = <&clock CLK_USI6>;
604 clock-names = "hsi2c";
605 status = "disabled";
b04a62d3 606 };
b04a62d3 607
5d99cc59
KK		 608 hdmi: hdmi@14530000 {
609 compatible = "samsung,exynos5420-hdmi";
610 reg = <0x14530000 0x70000>;
6abdf8d1 611 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 612 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
613 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
614 <&clock CLK_MOUT_HDMI>;
615 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
616 "sclk_hdmiphy", "mout_hdmi";
617 phy = <&hdmiphy>;
618 samsung,syscon-phandle = <&pmu_system_controller>;
619 status = "disabled";
620 power-domains = <&disp_pd>;
621 };
622
623 hdmiphy: hdmiphy@145D0000 {
624 reg = <0x145D0000 0x20>;
625 };
626
627 mixer: mixer@14450000 {
628 compatible = "samsung,exynos5420-mixer";
629 reg = <0x14450000 0x10000>;
6abdf8d1 630 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 631 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
632 <&clock CLK_SCLK_HDMI>;
633 clock-names = "mixer", "hdmi", "sclk_hdmi";
634 power-domains = <&disp_pd>;
635 iommus = <&sysmmu_tv>;
636 };
637
638 rotator: rotator@11C00000 {
639 compatible = "samsung,exynos5250-rotator";
640 reg = <0x11C00000 0x64>;
6abdf8d1 641 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 642 clocks = <&clock CLK_ROTATOR>;
643 clock-names = "rotator";
644 iommus = <&sysmmu_rotator>;
645 };
646
647 gsc_0: video-scaler@13e00000 {
648 compatible = "samsung,exynos5-gsc";
649 reg = <0x13e00000 0x1000>;
6abdf8d1 650 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 651 clocks = <&clock CLK_GSCL0>;
652 clock-names = "gscl";
653 power-domains = <&gsc_pd>;
654 iommus = <&sysmmu_gscl0>;
655 };
656
657 gsc_1: video-scaler@13e10000 {
658 compatible = "samsung,exynos5-gsc";
659 reg = <0x13e10000 0x1000>;
6abdf8d1 660 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 661 clocks = <&clock CLK_GSCL1>;
662 clock-names = "gscl";
663 power-domains = <&gsc_pd>;
664 iommus = <&sysmmu_gscl1>;
665 };
666
667 jpeg_0: jpeg@11F50000 {
668 compatible = "samsung,exynos5420-jpeg";
669 reg = <0x11F50000 0x1000>;
6abdf8d1 670 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 671 clock-names = "jpeg";
672 clocks = <&clock CLK_JPEG>;
673 iommus = <&sysmmu_jpeg0>;
674 };
675
676 jpeg_1: jpeg@11F60000 {
677 compatible = "samsung,exynos5420-jpeg";
678 reg = <0x11F60000 0x1000>;
6abdf8d1 679 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 680 clock-names = "jpeg";
681 clocks = <&clock CLK_JPEG2>;
682 iommus = <&sysmmu_jpeg1>;
683 };
684
685 pmu_system_controller: system-controller@10040000 {
686 compatible = "samsung,exynos5420-pmu", "syscon";
687 reg = <0x10040000 0x5000>;
688 clock-names = "clkout16";
689 clocks = <&clock CLK_FIN_PLL>;
690 #clock-cells = <1>;
691 interrupt-controller;
692 #interrupt-cells = <3>;
693 interrupt-parent = <&gic>;
b04a62d3 694 };
b04a62d3 695
5d99cc59
KK		 696 tmu_cpu0: tmu@10060000 {
697 compatible = "samsung,exynos5420-tmu";
698 reg = <0x10060000 0x100>;
6abdf8d1 699 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 700 clocks = <&clock CLK_TMU>;
701 clock-names = "tmu_apbif";
702 #include "exynos4412-tmu-sensor-conf.dtsi"
703 };
704
705 tmu_cpu1: tmu@10064000 {
706 compatible = "samsung,exynos5420-tmu";
707 reg = <0x10064000 0x100>;
6abdf8d1 708 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 709 clocks = <&clock CLK_TMU>;
710 clock-names = "tmu_apbif";
711 #include "exynos4412-tmu-sensor-conf.dtsi"
712 };
713
714 tmu_cpu2: tmu@10068000 {
715 compatible = "samsung,exynos5420-tmu-ext-triminfo";
716 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
6abdf8d1 717 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 718 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
719 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
720 #include "exynos4412-tmu-sensor-conf.dtsi"
721 };
722
723 tmu_cpu3: tmu@1006c000 {
724 compatible = "samsung,exynos5420-tmu-ext-triminfo";
725 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
6abdf8d1 726 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 727 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
728 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
729 #include "exynos4412-tmu-sensor-conf.dtsi"
730 };
731
732 tmu_gpu: tmu@100a0000 {
733 compatible = "samsung,exynos5420-tmu-ext-triminfo";
734 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
6abdf8d1 735 interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 736 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
737 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
738 #include "exynos4412-tmu-sensor-conf.dtsi"
739 };
740
5d99cc59
KK		 741 sysmmu_g2dr: sysmmu@0x10A60000 {
742 compatible = "samsung,exynos-sysmmu";
743 reg = <0x10A60000 0x1000>;
744 interrupt-parent = <&combiner>;
745 interrupts = <24 5>;
746 clock-names = "sysmmu", "master";
747 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
748 #iommu-cells = <0>;
749 };
750
751 sysmmu_g2dw: sysmmu@0x10A70000 {
752 compatible = "samsung,exynos-sysmmu";
753 reg = <0x10A70000 0x1000>;
754 interrupt-parent = <&combiner>;
755 interrupts = <22 2>;
756 clock-names = "sysmmu", "master";
757 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
758 #iommu-cells = <0>;
759 };
760
761 sysmmu_tv: sysmmu@0x14650000 {
762 compatible = "samsung,exynos-sysmmu";
763 reg = <0x14650000 0x1000>;
764 interrupt-parent = <&combiner>;
765 interrupts = <7 4>;
766 clock-names = "sysmmu", "master";
767 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
768 power-domains = <&disp_pd>;
769 #iommu-cells = <0>;
770 };
771
772 sysmmu_gscl0: sysmmu@0x13E80000 {
773 compatible = "samsung,exynos-sysmmu";
774 reg = <0x13E80000 0x1000>;
775 interrupt-parent = <&combiner>;
776 interrupts = <2 0>;
777 clock-names = "sysmmu", "master";
778 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
779 power-domains = <&gsc_pd>;
780 #iommu-cells = <0>;
781 };
782
783 sysmmu_gscl1: sysmmu@0x13E90000 {
784 compatible = "samsung,exynos-sysmmu";
785 reg = <0x13E90000 0x1000>;
786 interrupt-parent = <&combiner>;
787 interrupts = <2 2>;
788 clock-names = "sysmmu", "master";
789 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
790 power-domains = <&gsc_pd>;
791 #iommu-cells = <0>;
792 };
793
794 sysmmu_scaler0r: sysmmu@0x12880000 {
795 compatible = "samsung,exynos-sysmmu";
796 reg = <0x12880000 0x1000>;
797 interrupt-parent = <&combiner>;
798 interrupts = <22 4>;
799 clock-names = "sysmmu", "master";
800 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
801 #iommu-cells = <0>;
802 };
803
804 sysmmu_scaler1r: sysmmu@0x12890000 {
805 compatible = "samsung,exynos-sysmmu";
806 reg = <0x12890000 0x1000>;
6abdf8d1 807 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 808 clock-names = "sysmmu", "master";
809 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
810 #iommu-cells = <0>;
811 };
812
813 sysmmu_scaler2r: sysmmu@0x128A0000 {
814 compatible = "samsung,exynos-sysmmu";
815 reg = <0x128A0000 0x1000>;
6abdf8d1 816 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 817 clock-names = "sysmmu", "master";
818 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
819 #iommu-cells = <0>;
820 };
821
822 sysmmu_scaler0w: sysmmu@0x128C0000 {
823 compatible = "samsung,exynos-sysmmu";
824 reg = <0x128C0000 0x1000>;
825 interrupt-parent = <&combiner>;
826 interrupts = <27 2>;
827 clock-names = "sysmmu", "master";
828 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
829 #iommu-cells = <0>;
830 };
831
832 sysmmu_scaler1w: sysmmu@0x128D0000 {
833 compatible = "samsung,exynos-sysmmu";
834 reg = <0x128D0000 0x1000>;
835 interrupt-parent = <&combiner>;
836 interrupts = <22 6>;
837 clock-names = "sysmmu", "master";
838 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
839 #iommu-cells = <0>;
840 };
841
842 sysmmu_scaler2w: sysmmu@0x128E0000 {
843 compatible = "samsung,exynos-sysmmu";
844 reg = <0x128E0000 0x1000>;
845 interrupt-parent = <&combiner>;
846 interrupts = <19 6>;
847 clock-names = "sysmmu", "master";
848 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
849 #iommu-cells = <0>;
850 };
851
852 sysmmu_rotator: sysmmu@0x11D40000 {
853 compatible = "samsung,exynos-sysmmu";
854 reg = <0x11D40000 0x1000>;
855 interrupt-parent = <&combiner>;
856 interrupts = <4 0>;
857 clock-names = "sysmmu", "master";
858 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
859 #iommu-cells = <0>;
860 };
861
862 sysmmu_jpeg0: sysmmu@0x11F10000 {
863 compatible = "samsung,exynos-sysmmu";
864 reg = <0x11F10000 0x1000>;
865 interrupt-parent = <&combiner>;
866 interrupts = <4 2>;
867 clock-names = "sysmmu", "master";
868 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
869 #iommu-cells = <0>;
870 };
871
872 sysmmu_jpeg1: sysmmu@0x11F20000 {
873 compatible = "samsung,exynos-sysmmu";
874 reg = <0x11F20000 0x1000>;
6abdf8d1 875 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 876 clock-names = "sysmmu", "master";
877 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
878 #iommu-cells = <0>;
879 };
880
881 sysmmu_mfc_l: sysmmu@0x11200000 {
882 compatible = "samsung,exynos-sysmmu";
883 reg = <0x11200000 0x1000>;
884 interrupt-parent = <&combiner>;
885 interrupts = <6 2>;
886 clock-names = "sysmmu", "master";
887 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
888 power-domains = <&mfc_pd>;
889 #iommu-cells = <0>;
890 };
891
892 sysmmu_mfc_r: sysmmu@0x11210000 {
893 compatible = "samsung,exynos-sysmmu";
894 reg = <0x11210000 0x1000>;
895 interrupt-parent = <&combiner>;
896 interrupts = <8 5>;
897 clock-names = "sysmmu", "master";
898 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
899 power-domains = <&mfc_pd>;
900 #iommu-cells = <0>;
901 };
902
903 sysmmu_fimd1_0: sysmmu@0x14640000 {
904 compatible = "samsung,exynos-sysmmu";
905 reg = <0x14640000 0x1000>;
906 interrupt-parent = <&combiner>;
907 interrupts = <3 2>;
908 clock-names = "sysmmu", "master";
909 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
910 power-domains = <&disp_pd>;
911 #iommu-cells = <0>;
912 };
913
914 sysmmu_fimd1_1: sysmmu@0x14680000 {
915 compatible = "samsung,exynos-sysmmu";
916 reg = <0x14680000 0x1000>;
917 interrupt-parent = <&combiner>;
918 interrupts = <3 0>;
919 clock-names = "sysmmu", "master";
920 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
921 power-domains = <&disp_pd>;
922 #iommu-cells = <0>;
923 };
924
925 bus_wcore: bus_wcore {
926 compatible = "samsung,exynos-bus";
927 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
928 clock-names = "bus";
929 operating-points-v2 = <&bus_wcore_opp_table>;
930 status = "disabled";
b04a62d3 931 };
b04a62d3 932
5d99cc59
KK		 933 bus_noc: bus_noc {
934 compatible = "samsung,exynos-bus";
935 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
936 clock-names = "bus";
937 operating-points-v2 = <&bus_noc_opp_table>;
938 status = "disabled";
b04a62d3 939 };
b04a62d3 940
5d99cc59
KK		 941 bus_fsys_apb: bus_fsys_apb {
942 compatible = "samsung,exynos-bus";
943 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
944 clock-names = "bus";
945 operating-points-v2 = <&bus_fsys_apb_opp_table>;
946 status = "disabled";
b04a62d3 947 };
b04a62d3 948
5d99cc59
KK		 949 bus_fsys: bus_fsys {
950 compatible = "samsung,exynos-bus";
951 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
952 clock-names = "bus";
953 operating-points-v2 = <&bus_fsys_apb_opp_table>;
954 status = "disabled";
b04a62d3 955 };
5d99cc59
KK		 956
957 bus_fsys2: bus_fsys2 {
958 compatible = "samsung,exynos-bus";
959 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
960 clock-names = "bus";
961 operating-points-v2 = <&bus_fsys2_opp_table>;
962 status = "disabled";
b04a62d3 963 };
5d99cc59
KK		 964
965 bus_mfc: bus_mfc {
966 compatible = "samsung,exynos-bus";
967 clocks = <&clock CLK_DOUT_ACLK333>;
968 clock-names = "bus";
969 operating-points-v2 = <&bus_mfc_opp_table>;
970 status = "disabled";
b04a62d3 971 };
b04a62d3 972
5d99cc59
KK		 973 bus_gen: bus_gen {
974 compatible = "samsung,exynos-bus";
975 clocks = <&clock CLK_DOUT_ACLK266>;
976 clock-names = "bus";
977 operating-points-v2 = <&bus_gen_opp_table>;
978 status = "disabled";
979 };
b04a62d3 980
5d99cc59
KK		 981 bus_peri: bus_peri {
982 compatible = "samsung,exynos-bus";
983 clocks = <&clock CLK_DOUT_ACLK66>;
984 clock-names = "bus";
985 operating-points-v2 = <&bus_peri_opp_table>;
986 status = "disabled";
b04a62d3 987 };
5d99cc59
KK		 988
989 bus_g2d: bus_g2d {
990 compatible = "samsung,exynos-bus";
991 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
992 clock-names = "bus";
993 operating-points-v2 = <&bus_g2d_opp_table>;
994 status = "disabled";
b04a62d3 995 };
b04a62d3 996
5d99cc59
KK		 997 bus_g2d_acp: bus_g2d_acp {
998 compatible = "samsung,exynos-bus";
999 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1000 clock-names = "bus";
1001 operating-points-v2 = <&bus_g2d_acp_opp_table>;
1002 status = "disabled";
1003 };
b04a62d3 1004
5d99cc59
KK		 1005 bus_jpeg: bus_jpeg {
1006 compatible = "samsung,exynos-bus";
1007 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1008 clock-names = "bus";
1009 operating-points-v2 = <&bus_jpeg_opp_table>;
1010 status = "disabled";
b04a62d3 1011 };
5d99cc59
KK		 1012
1013 bus_jpeg_apb: bus_jpeg_apb {
1014 compatible = "samsung,exynos-bus";
1015 clocks = <&clock CLK_DOUT_ACLK166>;
1016 clock-names = "bus";
1017 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1018 status = "disabled";
b04a62d3 1019 };
5d99cc59
KK		 1020
1021 bus_disp1_fimd: bus_disp1_fimd {
1022 compatible = "samsung,exynos-bus";
1023 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1024 clock-names = "bus";
1025 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1026 status = "disabled";
b04a62d3 1027 };
b04a62d3 1028
5d99cc59
KK		 1029 bus_disp1: bus_disp1 {
1030 compatible = "samsung,exynos-bus";
1031 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1032 clock-names = "bus";
1033 operating-points-v2 = <&bus_disp1_opp_table>;
1034 status = "disabled";
1035 };
b04a62d3 1036
5d99cc59
KK		 1037 bus_gscl_scaler: bus_gscl_scaler {
1038 compatible = "samsung,exynos-bus";
1039 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1040 clock-names = "bus";
1041 operating-points-v2 = <&bus_gscl_opp_table>;
1042 status = "disabled";
b04a62d3 1043 };
5d99cc59
KK		 1044
1045 bus_mscl: bus_mscl {
1046 compatible = "samsung,exynos-bus";
1047 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1048 clock-names = "bus";
1049 operating-points-v2 = <&bus_mscl_opp_table>;
1050 status = "disabled";
b04a62d3 1051 };
5d99cc59
KK		 1052
1053 bus_wcore_opp_table: opp_table2 {
1054 compatible = "operating-points-v2";
1055
1056 opp00 {
1057 opp-hz = /bits/ 64 <84000000>;
1058 opp-microvolt = <925000>;
1059 };
1060 opp01 {
1061 opp-hz = /bits/ 64 <111000000>;
1062 opp-microvolt = <950000>;
1063 };
1064 opp02 {
1065 opp-hz = /bits/ 64 <222000000>;
1066 opp-microvolt = <950000>;
1067 };
1068 opp03 {
1069 opp-hz = /bits/ 64 <333000000>;
1070 opp-microvolt = <950000>;
1071 };
1072 opp04 {
1073 opp-hz = /bits/ 64 <400000000>;
1074 opp-microvolt = <987500>;
1075 };
1076 };
1077
1078 bus_noc_opp_table: opp_table3 {
1079 compatible = "operating-points-v2";
1080
1081 opp00 {
1082 opp-hz = /bits/ 64 <67000000>;
1083 };
1084 opp01 {
1085 opp-hz = /bits/ 64 <75000000>;
1086 };
1087 opp02 {
1088 opp-hz = /bits/ 64 <86000000>;
1089 };
1090 opp03 {
1091 opp-hz = /bits/ 64 <100000000>;
1092 };
1093 };
1094
1095 bus_fsys_apb_opp_table: opp_table4 {
1096 compatible = "operating-points-v2";
1097 opp-shared;
1098
1099 opp00 {
1100 opp-hz = /bits/ 64 <100000000>;
1101 };
1102 opp01 {
1103 opp-hz = /bits/ 64 <200000000>;
1104 };
1105 };
1106
1107 bus_fsys2_opp_table: opp_table5 {
1108 compatible = "operating-points-v2";
1109
1110 opp00 {
1111 opp-hz = /bits/ 64 <75000000>;
1112 };
1113 opp01 {
1114 opp-hz = /bits/ 64 <100000000>;
1115 };
1116 opp02 {
1117 opp-hz = /bits/ 64 <150000000>;
1118 };
1119 };
1120
1121 bus_mfc_opp_table: opp_table6 {
1122 compatible = "operating-points-v2";
1123
1124 opp00 {
1125 opp-hz = /bits/ 64 <96000000>;
1126 };
1127 opp01 {
1128 opp-hz = /bits/ 64 <111000000>;
1129 };
1130 opp02 {
1131 opp-hz = /bits/ 64 <167000000>;
1132 };
1133 opp03 {
1134 opp-hz = /bits/ 64 <222000000>;
1135 };
1136 opp04 {
1137 opp-hz = /bits/ 64 <333000000>;
1138 };
1139 };
1140
1141 bus_gen_opp_table: opp_table7 {
1142 compatible = "operating-points-v2";
1143
1144 opp00 {
1145 opp-hz = /bits/ 64 <89000000>;
1146 };
1147 opp01 {
1148 opp-hz = /bits/ 64 <133000000>;
1149 };
1150 opp02 {
1151 opp-hz = /bits/ 64 <178000000>;
1152 };
1153 opp03 {
1154 opp-hz = /bits/ 64 <267000000>;
1155 };
1156 };
1157
1158 bus_peri_opp_table: opp_table8 {
1159 compatible = "operating-points-v2";
1160
1161 opp00 {
1162 opp-hz = /bits/ 64 <67000000>;
1163 };
1164 };
1165
1166 bus_g2d_opp_table: opp_table9 {
1167 compatible = "operating-points-v2";
1168
1169 opp00 {
1170 opp-hz = /bits/ 64 <84000000>;
1171 };
1172 opp01 {
1173 opp-hz = /bits/ 64 <167000000>;
1174 };
1175 opp02 {
1176 opp-hz = /bits/ 64 <222000000>;
1177 };
1178 opp03 {
1179 opp-hz = /bits/ 64 <300000000>;
1180 };
1181 opp04 {
1182 opp-hz = /bits/ 64 <333000000>;
1183 };
1184 };
1185
1186 bus_g2d_acp_opp_table: opp_table10 {
1187 compatible = "operating-points-v2";
1188
1189 opp00 {
1190 opp-hz = /bits/ 64 <67000000>;
1191 };
1192 opp01 {
1193 opp-hz = /bits/ 64 <133000000>;
1194 };
1195 opp02 {
1196 opp-hz = /bits/ 64 <178000000>;
1197 };
1198 opp03 {
1199 opp-hz = /bits/ 64 <267000000>;
1200 };
1201 };
1202
1203 bus_jpeg_opp_table: opp_table11 {
1204 compatible = "operating-points-v2";
1205
1206 opp00 {
1207 opp-hz = /bits/ 64 <75000000>;
1208 };
1209 opp01 {
1210 opp-hz = /bits/ 64 <150000000>;
1211 };
1212 opp02 {
1213 opp-hz = /bits/ 64 <200000000>;
1214 };
1215 opp03 {
1216 opp-hz = /bits/ 64 <300000000>;
1217 };
1218 };
1219
1220 bus_jpeg_apb_opp_table: opp_table12 {
1221 compatible = "operating-points-v2";
1222
1223 opp00 {
1224 opp-hz = /bits/ 64 <84000000>;
1225 };
1226 opp01 {
1227 opp-hz = /bits/ 64 <111000000>;
1228 };
1229 opp02 {
1230 opp-hz = /bits/ 64 <134000000>;
1231 };
1232 opp03 {
1233 opp-hz = /bits/ 64 <167000000>;
1234 };
1235 };
1236
1237 bus_disp1_fimd_opp_table: opp_table13 {
1238 compatible = "operating-points-v2";
1239
1240 opp00 {
1241 opp-hz = /bits/ 64 <120000000>;
1242 };
1243 opp01 {
1244 opp-hz = /bits/ 64 <200000000>;
1245 };
1246 };
1247
1248 bus_disp1_opp_table: opp_table14 {
1249 compatible = "operating-points-v2";
1250
1251 opp00 {
1252 opp-hz = /bits/ 64 <120000000>;
1253 };
1254 opp01 {
1255 opp-hz = /bits/ 64 <200000000>;
1256 };
1257 opp02 {
1258 opp-hz = /bits/ 64 <300000000>;
1259 };
1260 };
1261
1262 bus_gscl_opp_table: opp_table15 {
1263 compatible = "operating-points-v2";
1264
1265 opp00 {
1266 opp-hz = /bits/ 64 <150000000>;
1267 };
1268 opp01 {
1269 opp-hz = /bits/ 64 <200000000>;
1270 };
1271 opp02 {
1272 opp-hz = /bits/ 64 <300000000>;
1273 };
1274 };
1275
1276 bus_mscl_opp_table: opp_table16 {
1277 compatible = "operating-points-v2";
1278
1279 opp00 {
1280 opp-hz = /bits/ 64 <84000000>;
1281 };
1282 opp01 {
1283 opp-hz = /bits/ 64 <167000000>;
1284 };
1285 opp02 {
1286 opp-hz = /bits/ 64 <222000000>;
1287 };
1288 opp03 {
1289 opp-hz = /bits/ 64 <333000000>;
1290 };
1291 opp04 {
1292 opp-hz = /bits/ 64 <400000000>;
1293 };
b04a62d3
CC		 1294 };
1295 };
1296
5d99cc59
KK		 1297 thermal-zones {
1298 cpu0_thermal: cpu0-thermal {
1299 thermal-sensors = <&tmu_cpu0>;
1300 #include "exynos5420-trip-points.dtsi"
b04a62d3 1301 };
5d99cc59
KK		 1302 cpu1_thermal: cpu1-thermal {
1303 thermal-sensors = <&tmu_cpu1>;
1304 #include "exynos5420-trip-points.dtsi"
b04a62d3 1305 };
5d99cc59
KK		 1306 cpu2_thermal: cpu2-thermal {
1307 thermal-sensors = <&tmu_cpu2>;
1308 #include "exynos5420-trip-points.dtsi"
b04a62d3 1309 };
5d99cc59
KK		 1310 cpu3_thermal: cpu3-thermal {
1311 thermal-sensors = <&tmu_cpu3>;
1312 #include "exynos5420-trip-points.dtsi"
b04a62d3 1313 };
5d99cc59
KK		 1314 gpu_thermal: gpu-thermal {
1315 thermal-sensors = <&tmu_gpu>;
1316 #include "exynos5420-trip-points.dtsi"
b04a62d3
CC		 1317 };
1318 };
34dcedfb 1319};
3a3cf6c4
KK		 1320
1321&dp {
1322 clocks = <&clock CLK_DP1>;
1323 clock-names = "dp";
1324 phys = <&dp_phy>;
1325 phy-names = "dp";
1326 power-domains = <&disp_pd>;
1327};
1328
1329&fimd {
6dc62f12 1330 compatible = "samsung,exynos5420-fimd";
3a3cf6c4
KK		 1331 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1332 clock-names = "sclk_fimd", "fimd";
1333 power-domains = <&disp_pd>;
b7004516
MS		 1334 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1335 iommu-names = "m0", "m1";
3a3cf6c4
KK		 1336};
1337
5a124fe0
KK		 1338&i2c_0 {
1339 clocks = <&clock CLK_I2C0>;
1340 clock-names = "i2c";
1341 pinctrl-names = "default";
1342 pinctrl-0 = <&i2c0_bus>;
1343};
1344
1345&i2c_1 {
1346 clocks = <&clock CLK_I2C1>;
1347 clock-names = "i2c";
1348 pinctrl-names = "default";
1349 pinctrl-0 = <&i2c1_bus>;
1350};
1351
1352&i2c_2 {
1353 clocks = <&clock CLK_I2C2>;
1354 clock-names = "i2c";
1355 pinctrl-names = "default";
1356 pinctrl-0 = <&i2c2_bus>;
1357};
1358
1359&i2c_3 {
1360 clocks = <&clock CLK_I2C3>;
1361 clock-names = "i2c";
1362 pinctrl-names = "default";
1363 pinctrl-0 = <&i2c3_bus>;
1364};
1365
538fc7ad
KK		 1366&hsi2c_4 {
1367 clocks = <&clock CLK_USI0>;
1368 clock-names = "hsi2c";
1369 pinctrl-names = "default";
1370 pinctrl-0 = <&i2c4_hs_bus>;
1371};
1372
1373&hsi2c_5 {
1374 clocks = <&clock CLK_USI1>;
1375 clock-names = "hsi2c";
1376 pinctrl-names = "default";
1377 pinctrl-0 = <&i2c5_hs_bus>;
1378};
1379
1380&hsi2c_6 {
1381 clocks = <&clock CLK_USI2>;
1382 clock-names = "hsi2c";
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&i2c6_hs_bus>;
1385};
1386
1387&hsi2c_7 {
1388 clocks = <&clock CLK_USI3>;
1389 clock-names = "hsi2c";
1390 pinctrl-names = "default";
1391 pinctrl-0 = <&i2c7_hs_bus>;
1392};
1393
c9cf996d
KK		 1394&mct {
1395 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1396 clock-names = "fin_pll", "mct";
1397};
1398
5a124fe0
KK		 1399&pwm {
1400 clocks = <&clock CLK_PWM>;
1401 clock-names = "timers";
1402};
1403
3a3cf6c4
KK		 1404&rtc {
1405 clocks = <&clock CLK_RTC>;
1406 clock-names = "rtc";
1407 interrupt-parent = <&pmu_system_controller>;
1408 status = "disabled";
1409};
1410
1411&serial_0 {
1412 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1413 clock-names = "uart", "clk_uart_baud0";
3590312f
MS		 1414 dmas = <&pdma0 13>, <&pdma0 14>;
1415 dma-names = "rx", "tx";
3a3cf6c4
KK		 1416};
1417
1418&serial_1 {
1419 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1420 clock-names = "uart", "clk_uart_baud0";
3590312f
MS		 1421 dmas = <&pdma1 15>, <&pdma1 16>;
1422 dma-names = "rx", "tx";
3a3cf6c4
KK		 1423};
1424
1425&serial_2 {
1426 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1427 clock-names = "uart", "clk_uart_baud0";
3590312f
MS		 1428 dmas = <&pdma0 15>, <&pdma0 16>;
1429 dma-names = "rx", "tx";
3a3cf6c4
KK		 1430};
1431
1432&serial_3 {
1433 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1434 clock-names = "uart", "clk_uart_baud0";
3590312f
MS		 1435 dmas = <&pdma1 17>, <&pdma1 18>;
1436 dma-names = "rx", "tx";
3a3cf6c4 1437};
c07f8270 1438
b8bd7e23
KK		 1439&sss {
1440 clocks = <&clock CLK_SSS>;
1441 clock-names = "secss";
1442};
1443
cb089656
KK		 1444&usbdrd3_0 {
1445 clocks = <&clock CLK_USBD300>;
1446 clock-names = "usbdrd30";
1447};
1448
1449&usbdrd_phy0 {
1450 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1451 clock-names = "phy", "ref";
1452 samsung,pmu-syscon = <&pmu_system_controller>;
1453};
1454
1455&usbdrd3_1 {
1456 clocks = <&clock CLK_USBD301>;
1457 clock-names = "usbdrd30";
1458};
1459
e5995e6d 1460&usbdrd_dwc3_1 {
6abdf8d1 1461 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
e5995e6d
KK		 1462};
1463
cb089656
KK		 1464&usbdrd_phy1 {
1465 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1466 clock-names = "phy", "ref";
1467 samsung,pmu-syscon = <&pmu_system_controller>;
1468};
1469
1470&usbhost1 {
1471 clocks = <&clock CLK_USBH20>;
1472 clock-names = "usbhost";
1473};
1474
1475&usbhost2 {
1476 clocks = <&clock CLK_USBH20>;
1477 clock-names = "usbhost";
1478};
1479
1480&usb2_phy {
1481 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1482 clock-names = "phy", "ref";
1483 samsung,sysreg-phandle = <&sysreg_system_controller>;
1484 samsung,pmureg-phandle = <&pmu_system_controller>;
1485};
1486
b8bd7e23
KK		 1487&watchdog {
1488 clocks = <&clock CLK_WDT>;
1489 clock-names = "watchdog";
1490 samsung,syscon-phandle = <&pmu_system_controller>;
1491};
1492
c07f8270 1493#include "exynos5420-pinctrl.dtsi"
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