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ARM: dts: Use labels for overriding nodes in exynos542x
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / exynos5420.dtsi
CommitLineData
34dcedfb
CK		 1/*
2 * SAMSUNG EXYNOS5420 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
1dd4e599 16#include <dt-bindings/clock/exynos5420.h>
34dcedfb 17#include "exynos5.dtsi"
0bd03f6f 18#include "exynos5420-pinctrl.dtsi"
35e82775 19
602408e3 20#include <dt-bindings/clock/exynos-audss-clk.h>
35e82775 21
34dcedfb 22/ {
8bdb31b4 23 compatible = "samsung,exynos5420", "samsung,exynos5";
34dcedfb 24
d81c6cbe 25 aliases {
0e2c5915
YK		 26 mshc0 = &mmc_0;
27 mshc1 = &mmc_1;
28 mshc2 = &mmc_2;
d81c6cbe
LKA		 29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
f49e347b
AB		 34 i2c0 = &i2c_0;
35 i2c1 = &i2c_1;
36 i2c2 = &i2c_2;
37 i2c3 = &i2c_3;
1a9110d6
SK		 38 i2c4 = &hsi2c_4;
39 i2c5 = &hsi2c_5;
40 i2c6 = &hsi2c_6;
41 i2c7 = &hsi2c_7;
42 i2c8 = &hsi2c_8;
43 i2c9 = &hsi2c_9;
44 i2c10 = &hsi2c_10;
01eb4636
LKA		 45 gsc0 = &gsc_0;
46 gsc1 = &gsc_1;
e84a2d91
LKA		 47 spi0 = &spi_0;
48 spi1 = &spi_1;
49 spi2 = &spi_2;
3cb7d1cd
VG		 50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
d81c6cbe
LKA		 52 };
53
34dcedfb
CK		 54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu0: cpu@0 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a15";
61 reg = <0x0>;
62 clock-frequency = <1800000000>;
5b56642b 63 cci-control-port = <&cci_control1>;
34dcedfb
CK		 64 };
65
66 cpu1: cpu@1 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a15";
69 reg = <0x1>;
70 clock-frequency = <1800000000>;
5b56642b 71 cci-control-port = <&cci_control1>;
34dcedfb
CK		 72 };
73
74 cpu2: cpu@2 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a15";
77 reg = <0x2>;
78 clock-frequency = <1800000000>;
5b56642b 79 cci-control-port = <&cci_control1>;
34dcedfb
CK		 80 };
81
82 cpu3: cpu@3 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <0x3>;
86 clock-frequency = <1800000000>;
5b56642b 87 cci-control-port = <&cci_control1>;
34dcedfb 88 };
1c0e0854
CK		 89
90 cpu4: cpu@100 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a7";
93 reg = <0x100>;
94 clock-frequency = <1000000000>;
5b56642b 95 cci-control-port = <&cci_control0>;
1c0e0854
CK		 96 };
97
98 cpu5: cpu@101 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a7";
101 reg = <0x101>;
102 clock-frequency = <1000000000>;
5b56642b 103 cci-control-port = <&cci_control0>;
1c0e0854
CK		 104 };
105
106 cpu6: cpu@102 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a7";
109 reg = <0x102>;
110 clock-frequency = <1000000000>;
5b56642b 111 cci-control-port = <&cci_control0>;
1c0e0854
CK		 112 };
113
114 cpu7: cpu@103 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a7";
117 reg = <0x103>;
118 clock-frequency = <1000000000>;
5b56642b
AB		 119 cci-control-port = <&cci_control0>;
120 };
121 };
122
25217fef 123 cci: cci@10d20000 {
5b56642b
AB		 124 compatible = "arm,cci-400";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>;
129
130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace";
133 reg = <0x4000 0x1000>;
134 };
135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace";
138 reg = <0x5000 0x1000>;
1c0e0854 139 };
34dcedfb
CK		 140 };
141
b3205dea
SK		 142 sysram@02020000 {
143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>;
146 #size-cells = <1>;
147 ranges = <0 0x02020000 0x54000>;
148
149 smp-sysram@0 {
150 compatible = "samsung,exynos4210-sysram";
151 reg = <0x0 0x1000>;
152 };
153
154 smp-sysram@53000 {
155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>;
1c0e0854 157 };
34dcedfb
CK		 158 };
159
92040bd6 160 clock: clock-controller@10010000 {
34dcedfb
CK		 161 compatible = "samsung,exynos5420-clock";
162 reg = <0x10010000 0x30000>;
163 #clock-cells = <1>;
164 };
165
35e82775
AB		 166 clock_audss: audss-clock-controller@3810000 {
167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>;
169 #clock-cells = <1>;
be0b420a 170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
1dd4e599 171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
59d711e9 172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
35e82775
AB		 173 };
174
8e371a91 175 mfc: codec@11000000 {
f09d062f
AK		 176 compatible = "samsung,mfc-v7";
177 reg = <0x11000000 0x10000>;
178 interrupts = <0 96 0>;
1dd4e599 179 clocks = <&clock CLK_MFC>;
f09d062f 180 clock-names = "mfc";
0da65870 181 power-domains = <&mfc_pd>;
f09d062f
AK		 182 };
183
0e2c5915
YK		 184 mmc_0: mmc@12200000 {
185 compatible = "samsung,exynos5420-dw-mshc-smu";
186 interrupts = <0 75 0>;
187 #address-cells = <1>;
188 #size-cells = <0>;
189 reg = <0x12200000 0x2000>;
1dd4e599 190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
0e2c5915
YK		 191 clock-names = "biu", "ciu";
192 fifo-depth = <0x40>;
193 status = "disabled";
194 };
195
196 mmc_1: mmc@12210000 {
197 compatible = "samsung,exynos5420-dw-mshc-smu";
198 interrupts = <0 76 0>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201 reg = <0x12210000 0x2000>;
1dd4e599 202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
0e2c5915
YK		 203 clock-names = "biu", "ciu";
204 fifo-depth = <0x40>;
205 status = "disabled";
206 };
207
208 mmc_2: mmc@12220000 {
209 compatible = "samsung,exynos5420-dw-mshc";
210 interrupts = <0 77 0>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 reg = <0x12220000 0x1000>;
1dd4e599 214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
0e2c5915
YK		 215 clock-names = "biu", "ciu";
216 fifo-depth = <0x40>;
217 status = "disabled";
218 };
219
8e371a91 220 mct: mct@101C0000 {
34dcedfb
CK		 221 compatible = "samsung,exynos4210-mct";
222 reg = <0x101C0000 0x800>;
223 interrupt-controller;
f27b9075 224 #interrupt-cells = <1>;
34dcedfb 225 interrupt-parent = <&mct_map>;
6c16dedf
CK		 226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
227 <8>, <9>, <10>, <11>;
1dd4e599 228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
34dcedfb
CK		 229 clock-names = "fin_pll", "mct";
230
231 mct_map: mct-map {
232 #interrupt-cells = <1>;
233 #address-cells = <0>;
234 #size-cells = <0>;
235 interrupt-map = <0 &combiner 23 3>,
236 <1 &combiner 23 4>,
237 <2 &combiner 25 2>,
238 <3 &combiner 25 3>,
239 <4 &gic 0 120 0>,
240 <5 &gic 0 121 0>,
241 <6 &gic 0 122 0>,
6c16dedf
CK		 242 <7 &gic 0 123 0>,
243 <8 &gic 0 128 0>,
244 <9 &gic 0 129 0>,
245 <10 &gic 0 130 0>,
246 <11 &gic 0 131 0>;
34dcedfb
CK		 247 };
248 };
249
dcfca2cc
YSB		 250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>;
0da65870 253 #power-domain-cells = <0>;
fa87bd43
AH		 254 clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
255 clock-names = "asb0", "asb1";
dcfca2cc
YSB		 256 };
257
258 isp_pd: power-domain@10044020 {
259 compatible = "samsung,exynos4210-pd";
260 reg = <0x10044020 0x20>;
0da65870 261 #power-domain-cells = <0>;
dcfca2cc
YSB		 262 };
263
264 mfc_pd: power-domain@10044060 {
265 compatible = "samsung,exynos4210-pd";
266 reg = <0x10044060 0x20>;
8d9321fb
KK		 267 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
268 clock-names = "oscclk", "clk0";
0da65870 269 #power-domain-cells = <0>;
dcfca2cc
YSB		 270 };
271
dcfca2cc
YSB		 272 msc_pd: power-domain@10044120 {
273 compatible = "samsung,exynos4210-pd";
274 reg = <0x10044120 0x20>;
0da65870 275 #power-domain-cells = <0>;
dcfca2cc
YSB		 276 };
277
ea08de16
JMC		 278 disp_pd: power-domain@100440C0 {
279 compatible = "samsung,exynos4210-pd";
280 reg = <0x100440C0 0x20>;
281 #power-domain-cells = <0>;
8d9321fb 282 clocks = <&clock CLK_FIN_PLL>,
ea08de16 283 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
ea08de16 284 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
ffb8b1ee
AH		 285 <&clock CLK_MOUT_USER_ACLK400_DISP1>,
286 <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
8d9321fb 287 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
dcfca2cc
YSB		 288 };
289
d81c6cbe
LKA		 290 pinctrl_0: pinctrl@13400000 {
291 compatible = "samsung,exynos5420-pinctrl";
292 reg = <0x13400000 0x1000>;
293 interrupts = <0 45 0>;
294
295 wakeup-interrupt-controller {
296 compatible = "samsung,exynos4210-wakeup-eint";
297 interrupt-parent = <&gic>;
298 interrupts = <0 32 0>;
299 };
300 };
301
302 pinctrl_1: pinctrl@13410000 {
303 compatible = "samsung,exynos5420-pinctrl";
304 reg = <0x13410000 0x1000>;
305 interrupts = <0 78 0>;
306 };
307
308 pinctrl_2: pinctrl@14000000 {
309 compatible = "samsung,exynos5420-pinctrl";
310 reg = <0x14000000 0x1000>;
311 interrupts = <0 46 0>;
312 };
313
314 pinctrl_3: pinctrl@14010000 {
315 compatible = "samsung,exynos5420-pinctrl";
316 reg = <0x14010000 0x1000>;
317 interrupts = <0 50 0>;
318 };
319
320 pinctrl_4: pinctrl@03860000 {
321 compatible = "samsung,exynos5420-pinctrl";
322 reg = <0x03860000 0x1000>;
323 interrupts = <0 47 0>;
324 };
325
e3188533
PV		 326 amba {
327 #address-cells = <1>;
328 #size-cells = <1>;
329 compatible = "arm,amba-bus";
330 interrupt-parent = <&gic>;
331 ranges;
332
6dd2f1c4
SK		 333 adma: adma@03880000 {
334 compatible = "arm,pl330", "arm,primecell";
335 reg = <0x03880000 0x1000>;
336 interrupts = <0 110 0>;
337 clocks = <&clock_audss EXYNOS_ADMA>;
338 clock-names = "apb_pclk";
339 #dma-cells = <1>;
340 #dma-channels = <6>;
341 #dma-requests = <16>;
342 };
343
e3188533
PV		 344 pdma0: pdma@121A0000 {
345 compatible = "arm,pl330", "arm,primecell";
346 reg = <0x121A0000 0x1000>;
347 interrupts = <0 34 0>;
1dd4e599 348 clocks = <&clock CLK_PDMA0>;
e3188533
PV		 349 clock-names = "apb_pclk";
350 #dma-cells = <1>;
351 #dma-channels = <8>;
352 #dma-requests = <32>;
353 };
354
355 pdma1: pdma@121B0000 {
356 compatible = "arm,pl330", "arm,primecell";
357 reg = <0x121B0000 0x1000>;
358 interrupts = <0 35 0>;
1dd4e599 359 clocks = <&clock CLK_PDMA1>;
e3188533
PV		 360 clock-names = "apb_pclk";
361 #dma-cells = <1>;
362 #dma-channels = <8>;
363 #dma-requests = <32>;
364 };
365
366 mdma0: mdma@10800000 {
367 compatible = "arm,pl330", "arm,primecell";
368 reg = <0x10800000 0x1000>;
369 interrupts = <0 33 0>;
1dd4e599 370 clocks = <&clock CLK_MDMA0>;
e3188533
PV		 371 clock-names = "apb_pclk";
372 #dma-cells = <1>;
373 #dma-channels = <8>;
374 #dma-requests = <1>;
375 };
376
377 mdma1: mdma@11C10000 {
378 compatible = "arm,pl330", "arm,primecell";
379 reg = <0x11C10000 0x1000>;
380 interrupts = <0 124 0>;
1dd4e599 381 clocks = <&clock CLK_MDMA1>;
e3188533
PV		 382 clock-names = "apb_pclk";
383 #dma-cells = <1>;
384 #dma-channels = <8>;
385 #dma-requests = <1>;
e6015c1f
SJ		 386 /*
387 * MDMA1 can support both secure and non-secure
388 * AXI transactions. When this is enabled in the kernel
389 * for boards that run in secure mode, we are getting
390 * imprecise external aborts causing the kernel to oops.
391 */
392 status = "disabled";
e3188533
PV		 393 };
394 };
395
98bcb547
SK		 396 i2s0: i2s@03830000 {
397 compatible = "samsung,exynos5420-i2s";
398 reg = <0x03830000 0x100>;
399 dmas = <&adma 0
400 &adma 2
401 &adma 1>;
402 dma-names = "tx", "rx", "tx-sec";
403 clocks = <&clock_audss EXYNOS_I2S_BUS>,
404 <&clock_audss EXYNOS_I2S_BUS>,
405 <&clock_audss EXYNOS_SCLK_I2S>;
406 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
7a548b1f
IS		 407 #clock-cells = <1>;
408 clock-output-names = "i2s_cdclk0";
409 #sound-dai-cells = <1>;
98bcb547
SK		 410 samsung,idma-addr = <0x03000000>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&i2s0_bus>;
413 status = "disabled";
414 };
415
416 i2s1: i2s@12D60000 {
417 compatible = "samsung,exynos5420-i2s";
418 reg = <0x12D60000 0x100>;
419 dmas = <&pdma1 12
420 &pdma1 11>;
421 dma-names = "tx", "rx";
1dd4e599 422 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
98bcb547 423 clock-names = "iis", "i2s_opclk0";
7a548b1f
IS		 424 #clock-cells = <1>;
425 clock-output-names = "i2s_cdclk1";
426 #sound-dai-cells = <1>;
98bcb547
SK		 427 pinctrl-names = "default";
428 pinctrl-0 = <&i2s1_bus>;
429 status = "disabled";
430 };
431
432 i2s2: i2s@12D70000 {
433 compatible = "samsung,exynos5420-i2s";
434 reg = <0x12D70000 0x100>;
435 dmas = <&pdma0 12
436 &pdma0 11>;
437 dma-names = "tx", "rx";
1dd4e599 438 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
98bcb547 439 clock-names = "iis", "i2s_opclk0";
7a548b1f
IS		 440 #clock-cells = <1>;
441 clock-output-names = "i2s_cdclk2";
442 #sound-dai-cells = <1>;
98bcb547
SK		 443 pinctrl-names = "default";
444 pinctrl-0 = <&i2s2_bus>;
445 status = "disabled";
446 };
447
e84a2d91
LKA		 448 spi_0: spi@12d20000 {
449 compatible = "samsung,exynos4210-spi";
450 reg = <0x12d20000 0x100>;
e3b6c271 451 interrupts = <0 68 0>;
e84a2d91
LKA		 452 dmas = <&pdma0 5
453 &pdma0 4>;
454 dma-names = "tx", "rx";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&spi0_bus>;
1dd4e599 459 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
e84a2d91
LKA		 460 clock-names = "spi", "spi_busclk0";
461 status = "disabled";
462 };
463
464 spi_1: spi@12d30000 {
465 compatible = "samsung,exynos4210-spi";
466 reg = <0x12d30000 0x100>;
e3b6c271 467 interrupts = <0 69 0>;
e84a2d91
LKA		 468 dmas = <&pdma1 5
469 &pdma1 4>;
470 dma-names = "tx", "rx";
471 #address-cells = <1>;
472 #size-cells = <0>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&spi1_bus>;
1dd4e599 475 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
e84a2d91
LKA		 476 clock-names = "spi", "spi_busclk0";
477 status = "disabled";
478 };
479
480 spi_2: spi@12d40000 {
481 compatible = "samsung,exynos4210-spi";
482 reg = <0x12d40000 0x100>;
e3b6c271 483 interrupts = <0 70 0>;
e84a2d91
LKA		 484 dmas = <&pdma0 7
485 &pdma0 6>;
486 dma-names = "tx", "rx";
487 #address-cells = <1>;
488 #size-cells = <0>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&spi2_bus>;
1dd4e599 491 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
e84a2d91
LKA		 492 clock-names = "spi", "spi_busclk0";
493 status = "disabled";
494 };
495
022cf308
LKA		 496 pwm: pwm@12dd0000 {
497 compatible = "samsung,exynos4210-pwm";
498 reg = <0x12dd0000 0x100>;
499 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
500 #pwm-cells = <3>;
1dd4e599 501 clocks = <&clock CLK_PWM>;
022cf308
LKA		 502 clock-names = "timers";
503 };
504
1339d33a 505 dp_phy: video-phy@10040728 {
e93e5454
VG		 506 compatible = "samsung,exynos5420-dp-video-phy";
507 samsung,pmu-syscon = <&pmu_system_controller>;
1339d33a
VS		 508 #phy-cells = <0>;
509 };
510
dc9ec8cd
YC		 511 mipi_phy: video-phy@10040714 {
512 compatible = "samsung,s5pv210-mipi-video-phy";
d1ed0d21 513 syscon = <&pmu_system_controller>;
dc9ec8cd
YC		 514 #phy-cells = <1>;
515 };
516
5a8da524
YC		 517 dsi@14500000 {
518 compatible = "samsung,exynos5410-mipi-dsi";
519 reg = <0x14500000 0x10000>;
520 interrupts = <0 82 0>;
5a8da524
YC		 521 phys = <&mipi_phy 1>;
522 phy-names = "dsim";
523 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
524 clock-names = "bus_clk", "pll_clk";
525 #address-cells = <1>;
526 #size-cells = <0>;
527 status = "disabled";
528 };
529
f408f9db
NKC		 530 adc: adc@12D10000 {
531 compatible = "samsung,exynos-adc-v2";
db9bf4d6 532 reg = <0x12D10000 0x100>;
f408f9db 533 interrupts = <0 106 0>;
1dd4e599 534 clocks = <&clock CLK_TSADC>;
f408f9db
NKC		 535 clock-names = "adc";
536 #io-channel-cells = <1>;
537 io-channel-ranges;
db9bf4d6 538 samsung,syscon-phandle = <&pmu_system_controller>;
f408f9db
NKC		 539 status = "disabled";
540 };
f49e347b
AB		 541
542 i2c_0: i2c@12C60000 {
543 compatible = "samsung,s3c2440-i2c";
544 reg = <0x12C60000 0x100>;
545 interrupts = <0 56 0>;
546 #address-cells = <1>;
547 #size-cells = <0>;
1dd4e599 548 clocks = <&clock CLK_I2C0>;
f49e347b
AB		 549 clock-names = "i2c";
550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c0_bus>;
1888eb75 552 samsung,sysreg-phandle = <&sysreg_system_controller>;
f49e347b
AB		 553 status = "disabled";
554 };
555
556 i2c_1: i2c@12C70000 {
557 compatible = "samsung,s3c2440-i2c";
558 reg = <0x12C70000 0x100>;
559 interrupts = <0 57 0>;
560 #address-cells = <1>;
561 #size-cells = <0>;
1dd4e599 562 clocks = <&clock CLK_I2C1>;
f49e347b
AB		 563 clock-names = "i2c";
564 pinctrl-names = "default";
565 pinctrl-0 = <&i2c1_bus>;
1888eb75 566 samsung,sysreg-phandle = <&sysreg_system_controller>;
f49e347b
AB		 567 status = "disabled";
568 };
569
570 i2c_2: i2c@12C80000 {
571 compatible = "samsung,s3c2440-i2c";
572 reg = <0x12C80000 0x100>;
573 interrupts = <0 58 0>;
574 #address-cells = <1>;
575 #size-cells = <0>;
1dd4e599 576 clocks = <&clock CLK_I2C2>;
f49e347b
AB		 577 clock-names = "i2c";
578 pinctrl-names = "default";
579 pinctrl-0 = <&i2c2_bus>;
1888eb75 580 samsung,sysreg-phandle = <&sysreg_system_controller>;
f49e347b
AB		 581 status = "disabled";
582 };
583
584 i2c_3: i2c@12C90000 {
585 compatible = "samsung,s3c2440-i2c";
586 reg = <0x12C90000 0x100>;
587 interrupts = <0 59 0>;
588 #address-cells = <1>;
589 #size-cells = <0>;
1dd4e599 590 clocks = <&clock CLK_I2C3>;
f49e347b
AB		 591 clock-names = "i2c";
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c3_bus>;
1888eb75 594 samsung,sysreg-phandle = <&sysreg_system_controller>;
f49e347b
AB		 595 status = "disabled";
596 };
b0e505ce 597
1a9110d6
SK		 598 hsi2c_4: i2c@12CA0000 {
599 compatible = "samsung,exynos5-hsi2c";
600 reg = <0x12CA0000 0x1000>;
601 interrupts = <0 60 0>;
602 #address-cells = <1>;
603 #size-cells = <0>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&i2c4_hs_bus>;
faec151b 606 clocks = <&clock CLK_USI0>;
1a9110d6
SK		 607 clock-names = "hsi2c";
608 status = "disabled";
609 };
610
611 hsi2c_5: i2c@12CB0000 {
612 compatible = "samsung,exynos5-hsi2c";
613 reg = <0x12CB0000 0x1000>;
614 interrupts = <0 61 0>;
615 #address-cells = <1>;
616 #size-cells = <0>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&i2c5_hs_bus>;
faec151b 619 clocks = <&clock CLK_USI1>;
1a9110d6
SK		 620 clock-names = "hsi2c";
621 status = "disabled";
622 };
623
624 hsi2c_6: i2c@12CC0000 {
625 compatible = "samsung,exynos5-hsi2c";
626 reg = <0x12CC0000 0x1000>;
627 interrupts = <0 62 0>;
628 #address-cells = <1>;
629 #size-cells = <0>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&i2c6_hs_bus>;
faec151b 632 clocks = <&clock CLK_USI2>;
1a9110d6
SK		 633 clock-names = "hsi2c";
634 status = "disabled";
635 };
636
637 hsi2c_7: i2c@12CD0000 {
638 compatible = "samsung,exynos5-hsi2c";
639 reg = <0x12CD0000 0x1000>;
640 interrupts = <0 63 0>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&i2c7_hs_bus>;
faec151b 645 clocks = <&clock CLK_USI3>;
1a9110d6
SK		 646 clock-names = "hsi2c";
647 status = "disabled";
648 };
649
650 hsi2c_8: i2c@12E00000 {
651 compatible = "samsung,exynos5-hsi2c";
652 reg = <0x12E00000 0x1000>;
653 interrupts = <0 87 0>;
654 #address-cells = <1>;
655 #size-cells = <0>;
656 pinctrl-names = "default";
657 pinctrl-0 = <&i2c8_hs_bus>;
faec151b 658 clocks = <&clock CLK_USI4>;
1a9110d6
SK		 659 clock-names = "hsi2c";
660 status = "disabled";
661 };
662
663 hsi2c_9: i2c@12E10000 {
664 compatible = "samsung,exynos5-hsi2c";
665 reg = <0x12E10000 0x1000>;
666 interrupts = <0 88 0>;
667 #address-cells = <1>;
668 #size-cells = <0>;
669 pinctrl-names = "default";
670 pinctrl-0 = <&i2c9_hs_bus>;
faec151b 671 clocks = <&clock CLK_USI5>;
1a9110d6
SK		 672 clock-names = "hsi2c";
673 status = "disabled";
674 };
675
676 hsi2c_10: i2c@12E20000 {
677 compatible = "samsung,exynos5-hsi2c";
678 reg = <0x12E20000 0x1000>;
679 interrupts = <0 203 0>;
680 #address-cells = <1>;
681 #size-cells = <0>;
682 pinctrl-names = "default";
683 pinctrl-0 = <&i2c10_hs_bus>;
faec151b 684 clocks = <&clock CLK_USI6>;
1a9110d6
SK		 685 clock-names = "hsi2c";
686 status = "disabled";
687 };
688
8e371a91 689 hdmi: hdmi@14530000 {
2963c554 690 compatible = "samsung,exynos5420-hdmi";
b0e505ce
RS		 691 reg = <0x14530000 0x70000>;
692 interrupts = <0 95 0>;
1dd4e599
AH		 693 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
694 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
695 <&clock CLK_MOUT_HDMI>;
b0e505ce
RS		 696 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
697 "sclk_hdmiphy", "mout_hdmi";
6ac189fc 698 phy = <&hdmiphy>;
3a7e5dd5 699 samsung,syscon-phandle = <&pmu_system_controller>;
b0e505ce 700 status = "disabled";
ea08de16 701 power-domains = <&disp_pd>;
b0e505ce
RS		 702 };
703
6ac189fc
RS		 704 hdmiphy: hdmiphy@145D0000 {
705 reg = <0x145D0000 0x20>;
706 };
707
8e371a91 708 mixer: mixer@14450000 {
b0e505ce
RS		 709 compatible = "samsung,exynos5420-mixer";
710 reg = <0x14450000 0x10000>;
711 interrupts = <0 94 0>;
c950ea68
MS		 712 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
713 <&clock CLK_SCLK_HDMI>;
714 clock-names = "mixer", "hdmi", "sclk_hdmi";
ea08de16 715 power-domains = <&disp_pd>;
b0e505ce 716 };
01eb4636
LKA		 717
718 gsc_0: video-scaler@13e00000 {
719 compatible = "samsung,exynos5-gsc";
720 reg = <0x13e00000 0x1000>;
721 interrupts = <0 85 0>;
1dd4e599 722 clocks = <&clock CLK_GSCL0>;
01eb4636 723 clock-names = "gscl";
0da65870 724 power-domains = <&gsc_pd>;
01eb4636
LKA		 725 };
726
727 gsc_1: video-scaler@13e10000 {
728 compatible = "samsung,exynos5-gsc";
729 reg = <0x13e10000 0x1000>;
730 interrupts = <0 86 0>;
1dd4e599 731 clocks = <&clock CLK_GSCL1>;
01eb4636 732 clock-names = "gscl";
0da65870 733 power-domains = <&gsc_pd>;
01eb4636 734 };
655de648 735
c680036a
LKA		 736 pmu_system_controller: system-controller@10040000 {
737 compatible = "samsung,exynos5420-pmu", "syscon";
738 reg = <0x10040000 0x5000>;
d19bb397
TF		 739 clock-names = "clkout16";
740 clocks = <&clock CLK_FIN_PLL>;
741 #clock-cells = <1>;
8b283c02
MZ		 742 interrupt-controller;
743 #interrupt-cells = <3>;
744 interrupt-parent = <&gic>;
c680036a
LKA		 745 };
746
dfbbdbf4
VG		 747 sysreg_system_controller: syscon@10050000 {
748 compatible = "samsung,exynos5-sysreg", "syscon";
749 reg = <0x10050000 0x5000>;
750 };
751
655de648
NKC		 752 tmu_cpu0: tmu@10060000 {
753 compatible = "samsung,exynos5420-tmu";
754 reg = <0x10060000 0x100>;
755 interrupts = <0 65 0>;
1dd4e599 756 clocks = <&clock CLK_TMU>;
655de648 757 clock-names = "tmu_apbif";
9843a223 758 #include "exynos4412-tmu-sensor-conf.dtsi"
655de648
NKC		 759 };
760
761 tmu_cpu1: tmu@10064000 {
762 compatible = "samsung,exynos5420-tmu";
763 reg = <0x10064000 0x100>;
764 interrupts = <0 183 0>;
1dd4e599 765 clocks = <&clock CLK_TMU>;
655de648 766 clock-names = "tmu_apbif";
9843a223 767 #include "exynos4412-tmu-sensor-conf.dtsi"
655de648
NKC		 768 };
769
770 tmu_cpu2: tmu@10068000 {
771 compatible = "samsung,exynos5420-tmu-ext-triminfo";
772 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
773 interrupts = <0 184 0>;
1dd4e599 774 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
655de648 775 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
9843a223 776 #include "exynos4412-tmu-sensor-conf.dtsi"
655de648
NKC		 777 };
778
779 tmu_cpu3: tmu@1006c000 {
780 compatible = "samsung,exynos5420-tmu-ext-triminfo";
781 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
782 interrupts = <0 185 0>;
1dd4e599 783 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
655de648 784 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
9843a223 785 #include "exynos4412-tmu-sensor-conf.dtsi"
655de648
NKC		 786 };
787
788 tmu_gpu: tmu@100a0000 {
789 compatible = "samsung,exynos5420-tmu-ext-triminfo";
790 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
791 interrupts = <0 215 0>;
1dd4e599 792 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
655de648 793 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
9843a223
LM		 794 #include "exynos4412-tmu-sensor-conf.dtsi"
795 };
796
797 thermal-zones {
798 cpu0_thermal: cpu0-thermal {
799 thermal-sensors = <&tmu_cpu0>;
800 #include "exynos5420-trip-points.dtsi"
801 };
802 cpu1_thermal: cpu1-thermal {
803 thermal-sensors = <&tmu_cpu1>;
804 #include "exynos5420-trip-points.dtsi"
805 };
806 cpu2_thermal: cpu2-thermal {
807 thermal-sensors = <&tmu_cpu2>;
808 #include "exynos5420-trip-points.dtsi"
809 };
810 cpu3_thermal: cpu3-thermal {
811 thermal-sensors = <&tmu_cpu3>;
812 #include "exynos5420-trip-points.dtsi"
813 };
814 gpu_thermal: gpu-thermal {
815 thermal-sensors = <&tmu_gpu>;
816 #include "exynos5420-trip-points.dtsi"
817 };
655de648 818 };
1d287620 819
8e371a91 820 watchdog: watchdog@101D0000 {
1d287620
LKA		 821 compatible = "samsung,exynos5420-wdt";
822 reg = <0x101D0000 0x100>;
823 interrupts = <0 42 0>;
1dd4e599 824 clocks = <&clock CLK_WDT>;
1d287620
LKA		 825 clock-names = "watchdog";
826 samsung,syscon-phandle = <&pmu_system_controller>;
827 };
183af252 828
8e371a91 829 sss: sss@10830000 {
183af252
NKC		 830 compatible = "samsung,exynos4210-secss";
831 reg = <0x10830000 0x10000>;
832 interrupts = <0 112 0>;
ab3a158c 833 clocks = <&clock CLK_SSS>;
183af252 834 clock-names = "secss";
183af252 835 };
3cb7d1cd 836
f070267b
VG		 837 usbdrd3_0: usb@12000000 {
838 compatible = "samsung,exynos5250-dwusb3";
839 clocks = <&clock CLK_USBD300>;
840 clock-names = "usbdrd30";
841 #address-cells = <1>;
842 #size-cells = <1>;
843 ranges;
844
e1c69efc 845 usbdrd_dwc3_0: dwc3 {
f070267b
VG		 846 compatible = "snps,dwc3";
847 reg = <0x12000000 0x10000>;
848 interrupts = <0 72 0>;
849 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
850 phy-names = "usb2-phy", "usb3-phy";
851 };
852 };
853
3cb7d1cd
VG		 854 usbdrd_phy0: phy@12100000 {
855 compatible = "samsung,exynos5420-usbdrd-phy";
856 reg = <0x12100000 0x100>;
857 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
858 clock-names = "phy", "ref";
859 samsung,pmu-syscon = <&pmu_system_controller>;
860 #phy-cells = <1>;
861 };
862
f070267b
VG		 863 usbdrd3_1: usb@12400000 {
864 compatible = "samsung,exynos5250-dwusb3";
865 clocks = <&clock CLK_USBD301>;
866 clock-names = "usbdrd30";
867 #address-cells = <1>;
868 #size-cells = <1>;
869 ranges;
870
e1c69efc 871 usbdrd_dwc3_1: dwc3 {
f070267b
VG		 872 compatible = "snps,dwc3";
873 reg = <0x12400000 0x10000>;
874 interrupts = <0 73 0>;
875 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
876 phy-names = "usb2-phy", "usb3-phy";
877 };
878 };
879
3cb7d1cd
VG		 880 usbdrd_phy1: phy@12500000 {
881 compatible = "samsung,exynos5420-usbdrd-phy";
882 reg = <0x12500000 0x100>;
883 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
884 clock-names = "phy", "ref";
885 samsung,pmu-syscon = <&pmu_system_controller>;
886 #phy-cells = <1>;
887 };
8d53526f 888
6674fd92
VG		 889 usbhost2: usb@12110000 {
890 compatible = "samsung,exynos4210-ehci";
891 reg = <0x12110000 0x100>;
892 interrupts = <0 71 0>;
893
894 clocks = <&clock CLK_USBH20>;
895 clock-names = "usbhost";
896 #address-cells = <1>;
897 #size-cells = <0>;
898 port@0 {
899 reg = <0>;
900 phys = <&usb2_phy 1>;
901 };
902 };
903
904 usbhost1: usb@12120000 {
905 compatible = "samsung,exynos4210-ohci";
906 reg = <0x12120000 0x100>;
907 interrupts = <0 71 0>;
908
909 clocks = <&clock CLK_USBH20>;
910 clock-names = "usbhost";
911 #address-cells = <1>;
912 #size-cells = <0>;
913 port@0 {
914 reg = <0>;
915 phys = <&usb2_phy 1>;
916 };
917 };
918
8d53526f
VG		 919 usb2_phy: phy@12130000 {
920 compatible = "samsung,exynos5250-usb2-phy";
921 reg = <0x12130000 0x100>;
922 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
923 clock-names = "phy", "ref";
924 #phy-cells = <1>;
925 samsung,sysreg-phandle = <&sysreg_system_controller>;
926 samsung,pmureg-phandle = <&pmu_system_controller>;
927 };
34dcedfb 928};
3a3cf6c4
KK		 929
930&dp {
931 clocks = <&clock CLK_DP1>;
932 clock-names = "dp";
933 phys = <&dp_phy>;
934 phy-names = "dp";
935 power-domains = <&disp_pd>;
936};
937
938&fimd {
939 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
940 clock-names = "sclk_fimd", "fimd";
941 power-domains = <&disp_pd>;
942};
943
944&rtc {
945 clocks = <&clock CLK_RTC>;
946 clock-names = "rtc";
947 interrupt-parent = <&pmu_system_controller>;
948 status = "disabled";
949};
950
951&serial_0 {
952 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
953 clock-names = "uart", "clk_uart_baud0";
954};
955
956&serial_1 {
957 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
958 clock-names = "uart", "clk_uart_baud0";
959};
960
961&serial_2 {
962 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
963 clock-names = "uart", "clk_uart_baud0";
964};
965
966&serial_3 {
967 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
968 clock-names = "uart", "clk_uart_baud0";
969};
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