projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 34dcedfb CK |
1 | /* |
| 2 | * SAMSUNG EXYNOS5420 SoC device tree source | |
| 3 | * | |
| 4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
| 5 | * http://www.samsung.com | |
| 6 | * | |
| 7 | * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. | |
| 8 | * EXYNOS5420 based board files can include this file and provide | |
| 9 | * values for board specfic bindings. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or modify | |
| 12 | * it under the terms of the GNU General Public License version 2 as | |
| 13 | * published by the Free Software Foundation. | |
| 14 | */ | |
| 15 | ||
| 1dd4e599 | 16 | #include <dt-bindings/clock/exynos5420.h> |
| 34dcedfb | 17 | #include "exynos5.dtsi" |
| 0bd03f6f | 18 | #include "exynos5420-pinctrl.dtsi" |
| 35e82775 | 19 | |
| 602408e3 | 20 | #include <dt-bindings/clock/exynos-audss-clk.h> |
| 35e82775 | 21 | |
| 34dcedfb | 22 | / { |
| 8bdb31b4 | 23 | compatible = "samsung,exynos5420", "samsung,exynos5"; |
| 34dcedfb | 24 | |
| d81c6cbe | 25 | aliases { |
| 0e2c5915 YK |
26 | mshc0 = &mmc_0; |
| 27 | mshc1 = &mmc_1; | |
| 28 | mshc2 = &mmc_2; | |
| d81c6cbe LKA |
29 | pinctrl0 = &pinctrl_0; |
| 30 | pinctrl1 = &pinctrl_1; | |
| 31 | pinctrl2 = &pinctrl_2; | |
| 32 | pinctrl3 = &pinctrl_3; | |
| 33 | pinctrl4 = &pinctrl_4; | |
| f49e347b AB |
34 | i2c0 = &i2c_0; |
| 35 | i2c1 = &i2c_1; | |
| 36 | i2c2 = &i2c_2; | |
| 37 | i2c3 = &i2c_3; | |
| 1a9110d6 SK |
38 | i2c4 = &hsi2c_4; |
| 39 | i2c5 = &hsi2c_5; | |
| 40 | i2c6 = &hsi2c_6; | |
| 41 | i2c7 = &hsi2c_7; | |
| 42 | i2c8 = &hsi2c_8; | |
| 43 | i2c9 = &hsi2c_9; | |
| 44 | i2c10 = &hsi2c_10; | |
| 01eb4636 LKA |
45 | gsc0 = &gsc_0; |
| 46 | gsc1 = &gsc_1; | |
| e84a2d91 LKA |
47 | spi0 = &spi_0; |
| 48 | spi1 = &spi_1; | |
| 49 | spi2 = &spi_2; | |
| 3cb7d1cd VG |
50 | usbdrdphy0 = &usbdrd_phy0; |
| 51 | usbdrdphy1 = &usbdrd_phy1; | |
| d81c6cbe LKA |
52 | }; |
| 53 | ||
| 34dcedfb CK |
54 | cpus { |
| 55 | #address-cells = <1>; | |
| 56 | #size-cells = <0>; | |
| 57 | ||
| 58 | cpu0: cpu@0 { | |
| 59 | device_type = "cpu"; | |
| 60 | compatible = "arm,cortex-a15"; | |
| 61 | reg = <0x0>; | |
| 62 | clock-frequency = <1800000000>; | |
| 5b56642b | 63 | cci-control-port = <&cci_control1>; |
| 34dcedfb CK |
64 | }; |
| 65 | ||
| 66 | cpu1: cpu@1 { | |
| 67 | device_type = "cpu"; | |
| 68 | compatible = "arm,cortex-a15"; | |
| 69 | reg = <0x1>; | |
| 70 | clock-frequency = <1800000000>; | |
| 5b56642b | 71 | cci-control-port = <&cci_control1>; |
| 34dcedfb CK |
72 | }; |
| 73 | ||
| 74 | cpu2: cpu@2 { | |
| 75 | device_type = "cpu"; | |
| 76 | compatible = "arm,cortex-a15"; | |
| 77 | reg = <0x2>; | |
| 78 | clock-frequency = <1800000000>; | |
| 5b56642b | 79 | cci-control-port = <&cci_control1>; |
| 34dcedfb CK |
80 | }; |
| 81 | ||
| 82 | cpu3: cpu@3 { | |
| 83 | device_type = "cpu"; | |
| 84 | compatible = "arm,cortex-a15"; | |
| 85 | reg = <0x3>; | |
| 86 | clock-frequency = <1800000000>; | |
| 5b56642b | 87 | cci-control-port = <&cci_control1>; |
| 34dcedfb | 88 | }; |
| 1c0e0854 CK |
89 | |
| 90 | cpu4: cpu@100 { | |
| 91 | device_type = "cpu"; | |
| 92 | compatible = "arm,cortex-a7"; | |
| 93 | reg = <0x100>; | |
| 94 | clock-frequency = <1000000000>; | |
| 5b56642b | 95 | cci-control-port = <&cci_control0>; |
| 1c0e0854 CK |
96 | }; |
| 97 | ||
| 98 | cpu5: cpu@101 { | |
| 99 | device_type = "cpu"; | |
| 100 | compatible = "arm,cortex-a7"; | |
| 101 | reg = <0x101>; | |
| 102 | clock-frequency = <1000000000>; | |
| 5b56642b | 103 | cci-control-port = <&cci_control0>; |
| 1c0e0854 CK |
104 | }; |
| 105 | ||
| 106 | cpu6: cpu@102 { | |
| 107 | device_type = "cpu"; | |
| 108 | compatible = "arm,cortex-a7"; | |
| 109 | reg = <0x102>; | |
| 110 | clock-frequency = <1000000000>; | |
| 5b56642b | 111 | cci-control-port = <&cci_control0>; |
| 1c0e0854 CK |
112 | }; |
| 113 | ||
| 114 | cpu7: cpu@103 { | |
| 115 | device_type = "cpu"; | |
| 116 | compatible = "arm,cortex-a7"; | |
| 117 | reg = <0x103>; | |
| 118 | clock-frequency = <1000000000>; | |
| 5b56642b AB |
119 | cci-control-port = <&cci_control0>; |
| 120 | }; | |
| 121 | }; | |
| 122 | ||
| 25217fef | 123 | cci: cci@10d20000 { |
| 5b56642b AB |
124 | compatible = "arm,cci-400"; |
| 125 | #address-cells = <1>; | |
| 126 | #size-cells = <1>; | |
| 127 | reg = <0x10d20000 0x1000>; | |
| 128 | ranges = <0x0 0x10d20000 0x6000>; | |
| 129 | ||
| 130 | cci_control0: slave-if@4000 { | |
| 131 | compatible = "arm,cci-400-ctrl-if"; | |
| 132 | interface-type = "ace"; | |
| 133 | reg = <0x4000 0x1000>; | |
| 134 | }; | |
| 135 | cci_control1: slave-if@5000 { | |
| 136 | compatible = "arm,cci-400-ctrl-if"; | |
| 137 | interface-type = "ace"; | |
| 138 | reg = <0x5000 0x1000>; | |
| 1c0e0854 | 139 | }; |
| 34dcedfb CK |
140 | }; |
| 141 | ||
| b3205dea SK |
142 | sysram@02020000 { |
| 143 | compatible = "mmio-sram"; | |
| 144 | reg = <0x02020000 0x54000>; | |
| 145 | #address-cells = <1>; | |
| 146 | #size-cells = <1>; | |
| 147 | ranges = <0 0x02020000 0x54000>; | |
| 148 | ||
| 149 | smp-sysram@0 { | |
| 150 | compatible = "samsung,exynos4210-sysram"; | |
| 151 | reg = <0x0 0x1000>; | |
| 152 | }; | |
| 153 | ||
| 154 | smp-sysram@53000 { | |
| 155 | compatible = "samsung,exynos4210-sysram-ns"; | |
| 156 | reg = <0x53000 0x1000>; | |
| 1c0e0854 | 157 | }; |
| 34dcedfb CK |
158 | }; |
| 159 | ||
| 92040bd6 | 160 | clock: clock-controller@10010000 { |
| 34dcedfb CK |
161 | compatible = "samsung,exynos5420-clock"; |
| 162 | reg = <0x10010000 0x30000>; | |
| 163 | #clock-cells = <1>; | |
| 164 | }; | |
| 165 | ||
| 35e82775 AB |
166 | clock_audss: audss-clock-controller@3810000 { |
| 167 | compatible = "samsung,exynos5420-audss-clock"; | |
| 168 | reg = <0x03810000 0x0C>; | |
| 169 | #clock-cells = <1>; | |
| be0b420a | 170 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, |
| 1dd4e599 | 171 | <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; |
| 59d711e9 | 172 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
| 35e82775 AB |
173 | }; |
| 174 | ||
| 8e371a91 | 175 | mfc: codec@11000000 { |
| f09d062f AK |
176 | compatible = "samsung,mfc-v7"; |
| 177 | reg = <0x11000000 0x10000>; | |
| 178 | interrupts = <0 96 0>; | |
| 1dd4e599 | 179 | clocks = <&clock CLK_MFC>; |
| f09d062f | 180 | clock-names = "mfc"; |
| 0da65870 | 181 | power-domains = <&mfc_pd>; |
| f09d062f AK |
182 | }; |
| 183 | ||
| 0e2c5915 YK |
184 | mmc_0: mmc@12200000 { |
| 185 | compatible = "samsung,exynos5420-dw-mshc-smu"; | |
| 186 | interrupts = <0 75 0>; | |
| 187 | #address-cells = <1>; | |
| 188 | #size-cells = <0>; | |
| 189 | reg = <0x12200000 0x2000>; | |
| 1dd4e599 | 190 | clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; |
| 0e2c5915 YK |
191 | clock-names = "biu", "ciu"; |
| 192 | fifo-depth = <0x40>; | |
| 193 | status = "disabled"; | |
| 194 | }; | |
| 195 | ||
| 196 | mmc_1: mmc@12210000 { | |
| 197 | compatible = "samsung,exynos5420-dw-mshc-smu"; | |
| 198 | interrupts = <0 76 0>; | |
| 199 | #address-cells = <1>; | |
| 200 | #size-cells = <0>; | |
| 201 | reg = <0x12210000 0x2000>; | |
| 1dd4e599 | 202 | clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; |
| 0e2c5915 YK |
203 | clock-names = "biu", "ciu"; |
| 204 | fifo-depth = <0x40>; | |
| 205 | status = "disabled"; | |
| 206 | }; | |
| 207 | ||
| 208 | mmc_2: mmc@12220000 { | |
| 209 | compatible = "samsung,exynos5420-dw-mshc"; | |
| 210 | interrupts = <0 77 0>; | |
| 211 | #address-cells = <1>; | |
| 212 | #size-cells = <0>; | |
| 213 | reg = <0x12220000 0x1000>; | |
| 1dd4e599 | 214 | clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; |
| 0e2c5915 YK |
215 | clock-names = "biu", "ciu"; |
| 216 | fifo-depth = <0x40>; | |
| 217 | status = "disabled"; | |
| 218 | }; | |
| 219 | ||
| 8e371a91 | 220 | mct: mct@101C0000 { |
| 34dcedfb CK |
221 | compatible = "samsung,exynos4210-mct"; |
| 222 | reg = <0x101C0000 0x800>; | |
| 223 | interrupt-controller; | |
| f27b9075 | 224 | #interrupt-cells = <1>; |
| 34dcedfb | 225 | interrupt-parent = <&mct_map>; |
| 6c16dedf CK |
226 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, |
| 227 | <8>, <9>, <10>, <11>; | |
| 1dd4e599 | 228 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
| 34dcedfb CK |
229 | clock-names = "fin_pll", "mct"; |
| 230 | ||
| 231 | mct_map: mct-map { | |
| 232 | #interrupt-cells = <1>; | |
| 233 | #address-cells = <0>; | |
| 234 | #size-cells = <0>; | |
| 235 | interrupt-map = <0 &combiner 23 3>, | |
| 236 | <1 &combiner 23 4>, | |
| 237 | <2 &combiner 25 2>, | |
| 238 | <3 &combiner 25 3>, | |
| 239 | <4 &gic 0 120 0>, | |
| 240 | <5 &gic 0 121 0>, | |
| 241 | <6 &gic 0 122 0>, | |
| 6c16dedf CK |
242 | <7 &gic 0 123 0>, |
| 243 | <8 &gic 0 128 0>, | |
| 244 | <9 &gic 0 129 0>, | |
| 245 | <10 &gic 0 130 0>, | |
| 246 | <11 &gic 0 131 0>; | |
| 34dcedfb CK |
247 | }; |
| 248 | }; | |
| 249 | ||
| dcfca2cc YSB |
250 | gsc_pd: power-domain@10044000 { |
| 251 | compatible = "samsung,exynos4210-pd"; | |
| 252 | reg = <0x10044000 0x20>; | |
| 0da65870 | 253 | #power-domain-cells = <0>; |
| fa87bd43 AH |
254 | clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; |
| 255 | clock-names = "asb0", "asb1"; | |
| dcfca2cc YSB |
256 | }; |
| 257 | ||
| 258 | isp_pd: power-domain@10044020 { | |
| 259 | compatible = "samsung,exynos4210-pd"; | |
| 260 | reg = <0x10044020 0x20>; | |
| 0da65870 | 261 | #power-domain-cells = <0>; |
| dcfca2cc YSB |
262 | }; |
| 263 | ||
| 264 | mfc_pd: power-domain@10044060 { | |
| 265 | compatible = "samsung,exynos4210-pd"; | |
| 266 | reg = <0x10044060 0x20>; | |
| cacaeb82 AK |
267 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, |
| 268 | <&clock CLK_MOUT_USER_ACLK333>; | |
| 269 | clock-names = "oscclk", "pclk0", "clk0"; | |
| 0da65870 | 270 | #power-domain-cells = <0>; |
| dcfca2cc YSB |
271 | }; |
| 272 | ||
| dcfca2cc YSB |
273 | msc_pd: power-domain@10044120 { |
| 274 | compatible = "samsung,exynos4210-pd"; | |
| 275 | reg = <0x10044120 0x20>; | |
| 0da65870 | 276 | #power-domain-cells = <0>; |
| dcfca2cc YSB |
277 | }; |
| 278 | ||
| ea08de16 JMC |
279 | disp_pd: power-domain@100440C0 { |
| 280 | compatible = "samsung,exynos4210-pd"; | |
| 281 | reg = <0x100440C0 0x20>; | |
| 282 | #power-domain-cells = <0>; | |
| 283 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>, | |
| 284 | <&clock CLK_MOUT_USER_ACLK200_DISP1>, | |
| 285 | <&clock CLK_MOUT_SW_ACLK300>, | |
| 286 | <&clock CLK_MOUT_USER_ACLK300_DISP1>, | |
| 287 | <&clock CLK_MOUT_SW_ACLK400>, | |
| ffb8b1ee AH |
288 | <&clock CLK_MOUT_USER_ACLK400_DISP1>, |
| 289 | <&clock CLK_FIMD1>, <&clock CLK_MIXER>; | |
| ea08de16 | 290 | clock-names = "oscclk", "pclk0", "clk0", |
| ffb8b1ee AH |
291 | "pclk1", "clk1", "pclk2", "clk2", |
| 292 | "asb0", "asb1"; | |
| dcfca2cc YSB |
293 | }; |
| 294 | ||
| d81c6cbe LKA |
295 | pinctrl_0: pinctrl@13400000 { |
| 296 | compatible = "samsung,exynos5420-pinctrl"; | |
| 297 | reg = <0x13400000 0x1000>; | |
| 298 | interrupts = <0 45 0>; | |
| 299 | ||
| 300 | wakeup-interrupt-controller { | |
| 301 | compatible = "samsung,exynos4210-wakeup-eint"; | |
| 302 | interrupt-parent = <&gic>; | |
| 303 | interrupts = <0 32 0>; | |
| 304 | }; | |
| 305 | }; | |
| 306 | ||
| 307 | pinctrl_1: pinctrl@13410000 { | |
| 308 | compatible = "samsung,exynos5420-pinctrl"; | |
| 309 | reg = <0x13410000 0x1000>; | |
| 310 | interrupts = <0 78 0>; | |
| 311 | }; | |
| 312 | ||
| 313 | pinctrl_2: pinctrl@14000000 { | |
| 314 | compatible = "samsung,exynos5420-pinctrl"; | |
| 315 | reg = <0x14000000 0x1000>; | |
| 316 | interrupts = <0 46 0>; | |
| 317 | }; | |
| 318 | ||
| 319 | pinctrl_3: pinctrl@14010000 { | |
| 320 | compatible = "samsung,exynos5420-pinctrl"; | |
| 321 | reg = <0x14010000 0x1000>; | |
| 322 | interrupts = <0 50 0>; | |
| 323 | }; | |
| 324 | ||
| 325 | pinctrl_4: pinctrl@03860000 { | |
| 326 | compatible = "samsung,exynos5420-pinctrl"; | |
| 327 | reg = <0x03860000 0x1000>; | |
| 328 | interrupts = <0 47 0>; | |
| 329 | }; | |
| 330 | ||
| 8e371a91 | 331 | rtc: rtc@101E0000 { |
| 1dd4e599 | 332 | clocks = <&clock CLK_RTC>; |
| a81951d9 | 333 | clock-names = "rtc"; |
| 8b283c02 | 334 | interrupt-parent = <&pmu_system_controller>; |
| 451c402b | 335 | status = "disabled"; |
| a81951d9 VS |
336 | }; |
| 337 | ||
| e3188533 PV |
338 | amba { |
| 339 | #address-cells = <1>; | |
| 340 | #size-cells = <1>; | |
| 341 | compatible = "arm,amba-bus"; | |
| 342 | interrupt-parent = <&gic>; | |
| 343 | ranges; | |
| 344 | ||
| 6dd2f1c4 SK |
345 | adma: adma@03880000 { |
| 346 | compatible = "arm,pl330", "arm,primecell"; | |
| 347 | reg = <0x03880000 0x1000>; | |
| 348 | interrupts = <0 110 0>; | |
| 349 | clocks = <&clock_audss EXYNOS_ADMA>; | |
| 350 | clock-names = "apb_pclk"; | |
| 351 | #dma-cells = <1>; | |
| 352 | #dma-channels = <6>; | |
| 353 | #dma-requests = <16>; | |
| 354 | }; | |
| 355 | ||
| e3188533 PV |
356 | pdma0: pdma@121A0000 { |
| 357 | compatible = "arm,pl330", "arm,primecell"; | |
| 358 | reg = <0x121A0000 0x1000>; | |
| 359 | interrupts = <0 34 0>; | |
| 1dd4e599 | 360 | clocks = <&clock CLK_PDMA0>; |
| e3188533 PV |
361 | clock-names = "apb_pclk"; |
| 362 | #dma-cells = <1>; | |
| 363 | #dma-channels = <8>; | |
| 364 | #dma-requests = <32>; | |
| 365 | }; | |
| 366 | ||
| 367 | pdma1: pdma@121B0000 { | |
| 368 | compatible = "arm,pl330", "arm,primecell"; | |
| 369 | reg = <0x121B0000 0x1000>; | |
| 370 | interrupts = <0 35 0>; | |
| 1dd4e599 | 371 | clocks = <&clock CLK_PDMA1>; |
| e3188533 PV |
372 | clock-names = "apb_pclk"; |
| 373 | #dma-cells = <1>; | |
| 374 | #dma-channels = <8>; | |
| 375 | #dma-requests = <32>; | |
| 376 | }; | |
| 377 | ||
| 378 | mdma0: mdma@10800000 { | |
| 379 | compatible = "arm,pl330", "arm,primecell"; | |
| 380 | reg = <0x10800000 0x1000>; | |
| 381 | interrupts = <0 33 0>; | |
| 1dd4e599 | 382 | clocks = <&clock CLK_MDMA0>; |
| e3188533 PV |
383 | clock-names = "apb_pclk"; |
| 384 | #dma-cells = <1>; | |
| 385 | #dma-channels = <8>; | |
| 386 | #dma-requests = <1>; | |
| 387 | }; | |
| 388 | ||
| 389 | mdma1: mdma@11C10000 { | |
| 390 | compatible = "arm,pl330", "arm,primecell"; | |
| 391 | reg = <0x11C10000 0x1000>; | |
| 392 | interrupts = <0 124 0>; | |
| 1dd4e599 | 393 | clocks = <&clock CLK_MDMA1>; |
| e3188533 PV |
394 | clock-names = "apb_pclk"; |
| 395 | #dma-cells = <1>; | |
| 396 | #dma-channels = <8>; | |
| 397 | #dma-requests = <1>; | |
| e6015c1f SJ |
398 | /* |
| 399 | * MDMA1 can support both secure and non-secure | |
| 400 | * AXI transactions. When this is enabled in the kernel | |
| 401 | * for boards that run in secure mode, we are getting | |
| 402 | * imprecise external aborts causing the kernel to oops. | |
| 403 | */ | |
| 404 | status = "disabled"; | |
| e3188533 PV |
405 | }; |
| 406 | }; | |
| 407 | ||
| 98bcb547 SK |
408 | i2s0: i2s@03830000 { |
| 409 | compatible = "samsung,exynos5420-i2s"; | |
| 410 | reg = <0x03830000 0x100>; | |
| 411 | dmas = <&adma 0 | |
| 412 | &adma 2 | |
| 413 | &adma 1>; | |
| 414 | dma-names = "tx", "rx", "tx-sec"; | |
| 415 | clocks = <&clock_audss EXYNOS_I2S_BUS>, | |
| 416 | <&clock_audss EXYNOS_I2S_BUS>, | |
| 417 | <&clock_audss EXYNOS_SCLK_I2S>; | |
| 418 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
| 419 | samsung,idma-addr = <0x03000000>; | |
| 420 | pinctrl-names = "default"; | |
| 421 | pinctrl-0 = <&i2s0_bus>; | |
| 422 | status = "disabled"; | |
| 423 | }; | |
| 424 | ||
| 425 | i2s1: i2s@12D60000 { | |
| 426 | compatible = "samsung,exynos5420-i2s"; | |
| 427 | reg = <0x12D60000 0x100>; | |
| 428 | dmas = <&pdma1 12 | |
| 429 | &pdma1 11>; | |
| 430 | dma-names = "tx", "rx"; | |
| 1dd4e599 | 431 | clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; |
| 98bcb547 SK |
432 | clock-names = "iis", "i2s_opclk0"; |
| 433 | pinctrl-names = "default"; | |
| 434 | pinctrl-0 = <&i2s1_bus>; | |
| 435 | status = "disabled"; | |
| 436 | }; | |
| 437 | ||
| 438 | i2s2: i2s@12D70000 { | |
| 439 | compatible = "samsung,exynos5420-i2s"; | |
| 440 | reg = <0x12D70000 0x100>; | |
| 441 | dmas = <&pdma0 12 | |
| 442 | &pdma0 11>; | |
| 443 | dma-names = "tx", "rx"; | |
| 1dd4e599 | 444 | clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; |
| 98bcb547 SK |
445 | clock-names = "iis", "i2s_opclk0"; |
| 446 | pinctrl-names = "default"; | |
| 447 | pinctrl-0 = <&i2s2_bus>; | |
| 448 | status = "disabled"; | |
| 449 | }; | |
| 450 | ||
| e84a2d91 LKA |
451 | spi_0: spi@12d20000 { |
| 452 | compatible = "samsung,exynos4210-spi"; | |
| 453 | reg = <0x12d20000 0x100>; | |
| e3b6c271 | 454 | interrupts = <0 68 0>; |
| e84a2d91 LKA |
455 | dmas = <&pdma0 5 |
| 456 | &pdma0 4>; | |
| 457 | dma-names = "tx", "rx"; | |
| 458 | #address-cells = <1>; | |
| 459 | #size-cells = <0>; | |
| 460 | pinctrl-names = "default"; | |
| 461 | pinctrl-0 = <&spi0_bus>; | |
| 1dd4e599 | 462 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
| e84a2d91 LKA |
463 | clock-names = "spi", "spi_busclk0"; |
| 464 | status = "disabled"; | |
| 465 | }; | |
| 466 | ||
| 467 | spi_1: spi@12d30000 { | |
| 468 | compatible = "samsung,exynos4210-spi"; | |
| 469 | reg = <0x12d30000 0x100>; | |
| e3b6c271 | 470 | interrupts = <0 69 0>; |
| e84a2d91 LKA |
471 | dmas = <&pdma1 5 |
| 472 | &pdma1 4>; | |
| 473 | dma-names = "tx", "rx"; | |
| 474 | #address-cells = <1>; | |
| 475 | #size-cells = <0>; | |
| 476 | pinctrl-names = "default"; | |
| 477 | pinctrl-0 = <&spi1_bus>; | |
| 1dd4e599 | 478 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
| e84a2d91 LKA |
479 | clock-names = "spi", "spi_busclk0"; |
| 480 | status = "disabled"; | |
| 481 | }; | |
| 482 | ||
| 483 | spi_2: spi@12d40000 { | |
| 484 | compatible = "samsung,exynos4210-spi"; | |
| 485 | reg = <0x12d40000 0x100>; | |
| e3b6c271 | 486 | interrupts = <0 70 0>; |
| e84a2d91 LKA |
487 | dmas = <&pdma0 7 |
| 488 | &pdma0 6>; | |
| 489 | dma-names = "tx", "rx"; | |
| 490 | #address-cells = <1>; | |
| 491 | #size-cells = <0>; | |
| 492 | pinctrl-names = "default"; | |
| 493 | pinctrl-0 = <&spi2_bus>; | |
| 1dd4e599 | 494 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
| e84a2d91 LKA |
495 | clock-names = "spi", "spi_busclk0"; |
| 496 | status = "disabled"; | |
| 497 | }; | |
| 498 | ||
| 8e371a91 | 499 | uart_0: serial@12C00000 { |
| 1dd4e599 | 500 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
| 34dcedfb CK |
501 | clock-names = "uart", "clk_uart_baud0"; |
| 502 | }; | |
| 503 | ||
| 8e371a91 | 504 | uart_1: serial@12C10000 { |
| 1dd4e599 | 505 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
| 34dcedfb CK |
506 | clock-names = "uart", "clk_uart_baud0"; |
| 507 | }; | |
| 508 | ||
| 8e371a91 | 509 | uart_2: serial@12C20000 { |
| 1dd4e599 | 510 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
| 34dcedfb CK |
511 | clock-names = "uart", "clk_uart_baud0"; |
| 512 | }; | |
| 513 | ||
| 8e371a91 | 514 | uart_3: serial@12C30000 { |
| 1dd4e599 | 515 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
| 34dcedfb CK |
516 | clock-names = "uart", "clk_uart_baud0"; |
| 517 | }; | |
| ee3381d4 | 518 | |
| 022cf308 LKA |
519 | pwm: pwm@12dd0000 { |
| 520 | compatible = "samsung,exynos4210-pwm"; | |
| 521 | reg = <0x12dd0000 0x100>; | |
| 522 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
| 523 | #pwm-cells = <3>; | |
| 1dd4e599 | 524 | clocks = <&clock CLK_PWM>; |
| 022cf308 LKA |
525 | clock-names = "timers"; |
| 526 | }; | |
| 527 | ||
| 1339d33a | 528 | dp_phy: video-phy@10040728 { |
| e93e5454 VG |
529 | compatible = "samsung,exynos5420-dp-video-phy"; |
| 530 | samsung,pmu-syscon = <&pmu_system_controller>; | |
| 1339d33a VS |
531 | #phy-cells = <0>; |
| 532 | }; | |
| 533 | ||
| 8e371a91 | 534 | dp: dp-controller@145B0000 { |
| 1dd4e599 | 535 | clocks = <&clock CLK_DP1>; |
| 1339d33a VS |
536 | clock-names = "dp"; |
| 537 | phys = <&dp_phy>; | |
| 538 | phy-names = "dp"; | |
| 0d747762 | 539 | power-domains = <&disp_pd>; |
| 1339d33a VS |
540 | }; |
| 541 | ||
| dc9ec8cd YC |
542 | mipi_phy: video-phy@10040714 { |
| 543 | compatible = "samsung,s5pv210-mipi-video-phy"; | |
| 544 | reg = <0x10040714 12>; | |
| 545 | #phy-cells = <1>; | |
| 546 | }; | |
| 547 | ||
| 5a8da524 YC |
548 | dsi@14500000 { |
| 549 | compatible = "samsung,exynos5410-mipi-dsi"; | |
| 550 | reg = <0x14500000 0x10000>; | |
| 551 | interrupts = <0 82 0>; | |
| 5a8da524 YC |
552 | phys = <&mipi_phy 1>; |
| 553 | phy-names = "dsim"; | |
| 554 | clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; | |
| 555 | clock-names = "bus_clk", "pll_clk"; | |
| 556 | #address-cells = <1>; | |
| 557 | #size-cells = <0>; | |
| 558 | status = "disabled"; | |
| 559 | }; | |
| 560 | ||
| 8e371a91 | 561 | fimd: fimd@14400000 { |
| 1dd4e599 | 562 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
| ee3381d4 | 563 | clock-names = "sclk_fimd", "fimd"; |
| ea08de16 | 564 | power-domains = <&disp_pd>; |
| ee3381d4 | 565 | }; |
| f408f9db NKC |
566 | |
| 567 | adc: adc@12D10000 { | |
| 568 | compatible = "samsung,exynos-adc-v2"; | |
| db9bf4d6 | 569 | reg = <0x12D10000 0x100>; |
| f408f9db | 570 | interrupts = <0 106 0>; |
| 1dd4e599 | 571 | clocks = <&clock CLK_TSADC>; |
| f408f9db NKC |
572 | clock-names = "adc"; |
| 573 | #io-channel-cells = <1>; | |
| 574 | io-channel-ranges; | |
| db9bf4d6 | 575 | samsung,syscon-phandle = <&pmu_system_controller>; |
| f408f9db NKC |
576 | status = "disabled"; |
| 577 | }; | |
| f49e347b AB |
578 | |
| 579 | i2c_0: i2c@12C60000 { | |
| 580 | compatible = "samsung,s3c2440-i2c"; | |
| 581 | reg = <0x12C60000 0x100>; | |
| 582 | interrupts = <0 56 0>; | |
| 583 | #address-cells = <1>; | |
| 584 | #size-cells = <0>; | |
| 1dd4e599 | 585 | clocks = <&clock CLK_I2C0>; |
| f49e347b AB |
586 | clock-names = "i2c"; |
| 587 | pinctrl-names = "default"; | |
| 588 | pinctrl-0 = <&i2c0_bus>; | |
| 1888eb75 | 589 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
| f49e347b AB |
590 | status = "disabled"; |
| 591 | }; | |
| 592 | ||
| 593 | i2c_1: i2c@12C70000 { | |
| 594 | compatible = "samsung,s3c2440-i2c"; | |
| 595 | reg = <0x12C70000 0x100>; | |
| 596 | interrupts = <0 57 0>; | |
| 597 | #address-cells = <1>; | |
| 598 | #size-cells = <0>; | |
| 1dd4e599 | 599 | clocks = <&clock CLK_I2C1>; |
| f49e347b AB |
600 | clock-names = "i2c"; |
| 601 | pinctrl-names = "default"; | |
| 602 | pinctrl-0 = <&i2c1_bus>; | |
| 1888eb75 | 603 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
| f49e347b AB |
604 | status = "disabled"; |
| 605 | }; | |
| 606 | ||
| 607 | i2c_2: i2c@12C80000 { | |
| 608 | compatible = "samsung,s3c2440-i2c"; | |
| 609 | reg = <0x12C80000 0x100>; | |
| 610 | interrupts = <0 58 0>; | |
| 611 | #address-cells = <1>; | |
| 612 | #size-cells = <0>; | |
| 1dd4e599 | 613 | clocks = <&clock CLK_I2C2>; |
| f49e347b AB |
614 | clock-names = "i2c"; |
| 615 | pinctrl-names = "default"; | |
| 616 | pinctrl-0 = <&i2c2_bus>; | |
| 1888eb75 | 617 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
| f49e347b AB |
618 | status = "disabled"; |
| 619 | }; | |
| 620 | ||
| 621 | i2c_3: i2c@12C90000 { | |
| 622 | compatible = "samsung,s3c2440-i2c"; | |
| 623 | reg = <0x12C90000 0x100>; | |
| 624 | interrupts = <0 59 0>; | |
| 625 | #address-cells = <1>; | |
| 626 | #size-cells = <0>; | |
| 1dd4e599 | 627 | clocks = <&clock CLK_I2C3>; |
| f49e347b AB |
628 | clock-names = "i2c"; |
| 629 | pinctrl-names = "default"; | |
| 630 | pinctrl-0 = <&i2c3_bus>; | |
| 1888eb75 | 631 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
| f49e347b AB |
632 | status = "disabled"; |
| 633 | }; | |
| b0e505ce | 634 | |
| 1a9110d6 SK |
635 | hsi2c_4: i2c@12CA0000 { |
| 636 | compatible = "samsung,exynos5-hsi2c"; | |
| 637 | reg = <0x12CA0000 0x1000>; | |
| 638 | interrupts = <0 60 0>; | |
| 639 | #address-cells = <1>; | |
| 640 | #size-cells = <0>; | |
| 641 | pinctrl-names = "default"; | |
| 642 | pinctrl-0 = <&i2c4_hs_bus>; | |
| faec151b | 643 | clocks = <&clock CLK_USI0>; |
| 1a9110d6 SK |
644 | clock-names = "hsi2c"; |
| 645 | status = "disabled"; | |
| 646 | }; | |
| 647 | ||
| 648 | hsi2c_5: i2c@12CB0000 { | |
| 649 | compatible = "samsung,exynos5-hsi2c"; | |
| 650 | reg = <0x12CB0000 0x1000>; | |
| 651 | interrupts = <0 61 0>; | |
| 652 | #address-cells = <1>; | |
| 653 | #size-cells = <0>; | |
| 654 | pinctrl-names = "default"; | |
| 655 | pinctrl-0 = <&i2c5_hs_bus>; | |
| faec151b | 656 | clocks = <&clock CLK_USI1>; |
| 1a9110d6 SK |
657 | clock-names = "hsi2c"; |
| 658 | status = "disabled"; | |
| 659 | }; | |
| 660 | ||
| 661 | hsi2c_6: i2c@12CC0000 { | |
| 662 | compatible = "samsung,exynos5-hsi2c"; | |
| 663 | reg = <0x12CC0000 0x1000>; | |
| 664 | interrupts = <0 62 0>; | |
| 665 | #address-cells = <1>; | |
| 666 | #size-cells = <0>; | |
| 667 | pinctrl-names = "default"; | |
| 668 | pinctrl-0 = <&i2c6_hs_bus>; | |
| faec151b | 669 | clocks = <&clock CLK_USI2>; |
| 1a9110d6 SK |
670 | clock-names = "hsi2c"; |
| 671 | status = "disabled"; | |
| 672 | }; | |
| 673 | ||
| 674 | hsi2c_7: i2c@12CD0000 { | |
| 675 | compatible = "samsung,exynos5-hsi2c"; | |
| 676 | reg = <0x12CD0000 0x1000>; | |
| 677 | interrupts = <0 63 0>; | |
| 678 | #address-cells = <1>; | |
| 679 | #size-cells = <0>; | |
| 680 | pinctrl-names = "default"; | |
| 681 | pinctrl-0 = <&i2c7_hs_bus>; | |
| faec151b | 682 | clocks = <&clock CLK_USI3>; |
| 1a9110d6 SK |
683 | clock-names = "hsi2c"; |
| 684 | status = "disabled"; | |
| 685 | }; | |
| 686 | ||
| 687 | hsi2c_8: i2c@12E00000 { | |
| 688 | compatible = "samsung,exynos5-hsi2c"; | |
| 689 | reg = <0x12E00000 0x1000>; | |
| 690 | interrupts = <0 87 0>; | |
| 691 | #address-cells = <1>; | |
| 692 | #size-cells = <0>; | |
| 693 | pinctrl-names = "default"; | |
| 694 | pinctrl-0 = <&i2c8_hs_bus>; | |
| faec151b | 695 | clocks = <&clock CLK_USI4>; |
| 1a9110d6 SK |
696 | clock-names = "hsi2c"; |
| 697 | status = "disabled"; | |
| 698 | }; | |
| 699 | ||
| 700 | hsi2c_9: i2c@12E10000 { | |
| 701 | compatible = "samsung,exynos5-hsi2c"; | |
| 702 | reg = <0x12E10000 0x1000>; | |
| 703 | interrupts = <0 88 0>; | |
| 704 | #address-cells = <1>; | |
| 705 | #size-cells = <0>; | |
| 706 | pinctrl-names = "default"; | |
| 707 | pinctrl-0 = <&i2c9_hs_bus>; | |
| faec151b | 708 | clocks = <&clock CLK_USI5>; |
| 1a9110d6 SK |
709 | clock-names = "hsi2c"; |
| 710 | status = "disabled"; | |
| 711 | }; | |
| 712 | ||
| 713 | hsi2c_10: i2c@12E20000 { | |
| 714 | compatible = "samsung,exynos5-hsi2c"; | |
| 715 | reg = <0x12E20000 0x1000>; | |
| 716 | interrupts = <0 203 0>; | |
| 717 | #address-cells = <1>; | |
| 718 | #size-cells = <0>; | |
| 719 | pinctrl-names = "default"; | |
| 720 | pinctrl-0 = <&i2c10_hs_bus>; | |
| faec151b | 721 | clocks = <&clock CLK_USI6>; |
| 1a9110d6 SK |
722 | clock-names = "hsi2c"; |
| 723 | status = "disabled"; | |
| 724 | }; | |
| 725 | ||
| 8e371a91 | 726 | hdmi: hdmi@14530000 { |
| 2963c554 | 727 | compatible = "samsung,exynos5420-hdmi"; |
| b0e505ce RS |
728 | reg = <0x14530000 0x70000>; |
| 729 | interrupts = <0 95 0>; | |
| 1dd4e599 AH |
730 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
| 731 | <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
| 732 | <&clock CLK_MOUT_HDMI>; | |
| b0e505ce RS |
733 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
| 734 | "sclk_hdmiphy", "mout_hdmi"; | |
| 6ac189fc | 735 | phy = <&hdmiphy>; |
| 3a7e5dd5 | 736 | samsung,syscon-phandle = <&pmu_system_controller>; |
| b0e505ce | 737 | status = "disabled"; |
| ea08de16 | 738 | power-domains = <&disp_pd>; |
| b0e505ce RS |
739 | }; |
| 740 | ||
| 6ac189fc RS |
741 | hdmiphy: hdmiphy@145D0000 { |
| 742 | reg = <0x145D0000 0x20>; | |
| 743 | }; | |
| 744 | ||
| 8e371a91 | 745 | mixer: mixer@14450000 { |
| b0e505ce RS |
746 | compatible = "samsung,exynos5420-mixer"; |
| 747 | reg = <0x14450000 0x10000>; | |
| 748 | interrupts = <0 94 0>; | |
| c950ea68 MS |
749 | clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, |
| 750 | <&clock CLK_SCLK_HDMI>; | |
| 751 | clock-names = "mixer", "hdmi", "sclk_hdmi"; | |
| ea08de16 | 752 | power-domains = <&disp_pd>; |
| b0e505ce | 753 | }; |
| 01eb4636 LKA |
754 | |
| 755 | gsc_0: video-scaler@13e00000 { | |
| 756 | compatible = "samsung,exynos5-gsc"; | |
| 757 | reg = <0x13e00000 0x1000>; | |
| 758 | interrupts = <0 85 0>; | |
| 1dd4e599 | 759 | clocks = <&clock CLK_GSCL0>; |
| 01eb4636 | 760 | clock-names = "gscl"; |
| 0da65870 | 761 | power-domains = <&gsc_pd>; |
| 01eb4636 LKA |
762 | }; |
| 763 | ||
| 764 | gsc_1: video-scaler@13e10000 { | |
| 765 | compatible = "samsung,exynos5-gsc"; | |
| 766 | reg = <0x13e10000 0x1000>; | |
| 767 | interrupts = <0 86 0>; | |
| 1dd4e599 | 768 | clocks = <&clock CLK_GSCL1>; |
| 01eb4636 | 769 | clock-names = "gscl"; |
| 0da65870 | 770 | power-domains = <&gsc_pd>; |
| 01eb4636 | 771 | }; |
| 655de648 | 772 | |
| c680036a LKA |
773 | pmu_system_controller: system-controller@10040000 { |
| 774 | compatible = "samsung,exynos5420-pmu", "syscon"; | |
| 775 | reg = <0x10040000 0x5000>; | |
| d19bb397 TF |
776 | clock-names = "clkout16"; |
| 777 | clocks = <&clock CLK_FIN_PLL>; | |
| 778 | #clock-cells = <1>; | |
| 8b283c02 MZ |
779 | interrupt-controller; |
| 780 | #interrupt-cells = <3>; | |
| 781 | interrupt-parent = <&gic>; | |
| c680036a LKA |
782 | }; |
| 783 | ||
| dfbbdbf4 VG |
784 | sysreg_system_controller: syscon@10050000 { |
| 785 | compatible = "samsung,exynos5-sysreg", "syscon"; | |
| 786 | reg = <0x10050000 0x5000>; | |
| 787 | }; | |
| 788 | ||
| 655de648 NKC |
789 | tmu_cpu0: tmu@10060000 { |
| 790 | compatible = "samsung,exynos5420-tmu"; | |
| 791 | reg = <0x10060000 0x100>; | |
| 792 | interrupts = <0 65 0>; | |
| 1dd4e599 | 793 | clocks = <&clock CLK_TMU>; |
| 655de648 | 794 | clock-names = "tmu_apbif"; |
| 9843a223 | 795 | #include "exynos4412-tmu-sensor-conf.dtsi" |
| 655de648 NKC |
796 | }; |
| 797 | ||
| 798 | tmu_cpu1: tmu@10064000 { | |
| 799 | compatible = "samsung,exynos5420-tmu"; | |
| 800 | reg = <0x10064000 0x100>; | |
| 801 | interrupts = <0 183 0>; | |
| 1dd4e599 | 802 | clocks = <&clock CLK_TMU>; |
| 655de648 | 803 | clock-names = "tmu_apbif"; |
| 9843a223 | 804 | #include "exynos4412-tmu-sensor-conf.dtsi" |
| 655de648 NKC |
805 | }; |
| 806 | ||
| 807 | tmu_cpu2: tmu@10068000 { | |
| 808 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
| 809 | reg = <0x10068000 0x100>, <0x1006c000 0x4>; | |
| 810 | interrupts = <0 184 0>; | |
| 1dd4e599 | 811 | clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; |
| 655de648 | 812 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
| 9843a223 | 813 | #include "exynos4412-tmu-sensor-conf.dtsi" |
| 655de648 NKC |
814 | }; |
| 815 | ||
| 816 | tmu_cpu3: tmu@1006c000 { | |
| 817 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
| 818 | reg = <0x1006c000 0x100>, <0x100a0000 0x4>; | |
| 819 | interrupts = <0 185 0>; | |
| 1dd4e599 | 820 | clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; |
| 655de648 | 821 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
| 9843a223 | 822 | #include "exynos4412-tmu-sensor-conf.dtsi" |
| 655de648 NKC |
823 | }; |
| 824 | ||
| 825 | tmu_gpu: tmu@100a0000 { | |
| 826 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
| 827 | reg = <0x100a0000 0x100>, <0x10068000 0x4>; | |
| 828 | interrupts = <0 215 0>; | |
| 1dd4e599 | 829 | clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; |
| 655de648 | 830 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
| 9843a223 LM |
831 | #include "exynos4412-tmu-sensor-conf.dtsi" |
| 832 | }; | |
| 833 | ||
| 834 | thermal-zones { | |
| 835 | cpu0_thermal: cpu0-thermal { | |
| 836 | thermal-sensors = <&tmu_cpu0>; | |
| 837 | #include "exynos5420-trip-points.dtsi" | |
| 838 | }; | |
| 839 | cpu1_thermal: cpu1-thermal { | |
| 840 | thermal-sensors = <&tmu_cpu1>; | |
| 841 | #include "exynos5420-trip-points.dtsi" | |
| 842 | }; | |
| 843 | cpu2_thermal: cpu2-thermal { | |
| 844 | thermal-sensors = <&tmu_cpu2>; | |
| 845 | #include "exynos5420-trip-points.dtsi" | |
| 846 | }; | |
| 847 | cpu3_thermal: cpu3-thermal { | |
| 848 | thermal-sensors = <&tmu_cpu3>; | |
| 849 | #include "exynos5420-trip-points.dtsi" | |
| 850 | }; | |
| 851 | gpu_thermal: gpu-thermal { | |
| 852 | thermal-sensors = <&tmu_gpu>; | |
| 853 | #include "exynos5420-trip-points.dtsi" | |
| 854 | }; | |
| 655de648 | 855 | }; |
| 1d287620 | 856 | |
| 8e371a91 | 857 | watchdog: watchdog@101D0000 { |
| 1d287620 LKA |
858 | compatible = "samsung,exynos5420-wdt"; |
| 859 | reg = <0x101D0000 0x100>; | |
| 860 | interrupts = <0 42 0>; | |
| 1dd4e599 | 861 | clocks = <&clock CLK_WDT>; |
| 1d287620 LKA |
862 | clock-names = "watchdog"; |
| 863 | samsung,syscon-phandle = <&pmu_system_controller>; | |
| 864 | }; | |
| 183af252 | 865 | |
| 8e371a91 | 866 | sss: sss@10830000 { |
| 183af252 NKC |
867 | compatible = "samsung,exynos4210-secss"; |
| 868 | reg = <0x10830000 0x10000>; | |
| 869 | interrupts = <0 112 0>; | |
| ab3a158c | 870 | clocks = <&clock CLK_SSS>; |
| 183af252 | 871 | clock-names = "secss"; |
| 183af252 | 872 | }; |
| 3cb7d1cd | 873 | |
| f070267b VG |
874 | usbdrd3_0: usb@12000000 { |
| 875 | compatible = "samsung,exynos5250-dwusb3"; | |
| 876 | clocks = <&clock CLK_USBD300>; | |
| 877 | clock-names = "usbdrd30"; | |
| 878 | #address-cells = <1>; | |
| 879 | #size-cells = <1>; | |
| 880 | ranges; | |
| 881 | ||
| e1c69efc | 882 | usbdrd_dwc3_0: dwc3 { |
| f070267b VG |
883 | compatible = "snps,dwc3"; |
| 884 | reg = <0x12000000 0x10000>; | |
| 885 | interrupts = <0 72 0>; | |
| 886 | phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; | |
| 887 | phy-names = "usb2-phy", "usb3-phy"; | |
| 888 | }; | |
| 889 | }; | |
| 890 | ||
| 3cb7d1cd VG |
891 | usbdrd_phy0: phy@12100000 { |
| 892 | compatible = "samsung,exynos5420-usbdrd-phy"; | |
| 893 | reg = <0x12100000 0x100>; | |
| 894 | clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; | |
| 895 | clock-names = "phy", "ref"; | |
| 896 | samsung,pmu-syscon = <&pmu_system_controller>; | |
| 897 | #phy-cells = <1>; | |
| 898 | }; | |
| 899 | ||
| f070267b VG |
900 | usbdrd3_1: usb@12400000 { |
| 901 | compatible = "samsung,exynos5250-dwusb3"; | |
| 902 | clocks = <&clock CLK_USBD301>; | |
| 903 | clock-names = "usbdrd30"; | |
| 904 | #address-cells = <1>; | |
| 905 | #size-cells = <1>; | |
| 906 | ranges; | |
| 907 | ||
| e1c69efc | 908 | usbdrd_dwc3_1: dwc3 { |
| f070267b VG |
909 | compatible = "snps,dwc3"; |
| 910 | reg = <0x12400000 0x10000>; | |
| 911 | interrupts = <0 73 0>; | |
| 912 | phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; | |
| 913 | phy-names = "usb2-phy", "usb3-phy"; | |
| 914 | }; | |
| 915 | }; | |
| 916 | ||
| 3cb7d1cd VG |
917 | usbdrd_phy1: phy@12500000 { |
| 918 | compatible = "samsung,exynos5420-usbdrd-phy"; | |
| 919 | reg = <0x12500000 0x100>; | |
| 920 | clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; | |
| 921 | clock-names = "phy", "ref"; | |
| 922 | samsung,pmu-syscon = <&pmu_system_controller>; | |
| 923 | #phy-cells = <1>; | |
| 924 | }; | |
| 8d53526f | 925 | |
| 6674fd92 VG |
926 | usbhost2: usb@12110000 { |
| 927 | compatible = "samsung,exynos4210-ehci"; | |
| 928 | reg = <0x12110000 0x100>; | |
| 929 | interrupts = <0 71 0>; | |
| 930 | ||
| 931 | clocks = <&clock CLK_USBH20>; | |
| 932 | clock-names = "usbhost"; | |
| 933 | #address-cells = <1>; | |
| 934 | #size-cells = <0>; | |
| 935 | port@0 { | |
| 936 | reg = <0>; | |
| 937 | phys = <&usb2_phy 1>; | |
| 938 | }; | |
| 939 | }; | |
| 940 | ||
| 941 | usbhost1: usb@12120000 { | |
| 942 | compatible = "samsung,exynos4210-ohci"; | |
| 943 | reg = <0x12120000 0x100>; | |
| 944 | interrupts = <0 71 0>; | |
| 945 | ||
| 946 | clocks = <&clock CLK_USBH20>; | |
| 947 | clock-names = "usbhost"; | |
| 948 | #address-cells = <1>; | |
| 949 | #size-cells = <0>; | |
| 950 | port@0 { | |
| 951 | reg = <0>; | |
| 952 | phys = <&usb2_phy 1>; | |
| 953 | }; | |
| 954 | }; | |
| 955 | ||
| 8d53526f VG |
956 | usb2_phy: phy@12130000 { |
| 957 | compatible = "samsung,exynos5250-usb2-phy"; | |
| 958 | reg = <0x12130000 0x100>; | |
| 959 | clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; | |
| 960 | clock-names = "phy", "ref"; | |
| 961 | #phy-cells = <1>; | |
| 962 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
| 963 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
| 964 | }; | |
| 34dcedfb | 965 | }; |