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34dcedfb CK |
1 | /* |
2 | * SAMSUNG EXYNOS5420 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. | |
8 | * EXYNOS5420 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include "exynos5.dtsi" | |
0bd03f6f | 17 | #include "exynos5420-pinctrl.dtsi" |
35e82775 AB |
18 | |
19 | #include <dt-bindings/clk/exynos-audss-clk.h> | |
20 | ||
34dcedfb CK |
21 | / { |
22 | compatible = "samsung,exynos5420"; | |
23 | ||
d81c6cbe | 24 | aliases { |
0e2c5915 YK |
25 | mshc0 = &mmc_0; |
26 | mshc1 = &mmc_1; | |
27 | mshc2 = &mmc_2; | |
d81c6cbe LKA |
28 | pinctrl0 = &pinctrl_0; |
29 | pinctrl1 = &pinctrl_1; | |
30 | pinctrl2 = &pinctrl_2; | |
31 | pinctrl3 = &pinctrl_3; | |
32 | pinctrl4 = &pinctrl_4; | |
f49e347b AB |
33 | i2c0 = &i2c_0; |
34 | i2c1 = &i2c_1; | |
35 | i2c2 = &i2c_2; | |
36 | i2c3 = &i2c_3; | |
01eb4636 LKA |
37 | gsc0 = &gsc_0; |
38 | gsc1 = &gsc_1; | |
d81c6cbe LKA |
39 | }; |
40 | ||
34dcedfb CK |
41 | cpus { |
42 | #address-cells = <1>; | |
43 | #size-cells = <0>; | |
44 | ||
45 | cpu0: cpu@0 { | |
46 | device_type = "cpu"; | |
47 | compatible = "arm,cortex-a15"; | |
48 | reg = <0x0>; | |
49 | clock-frequency = <1800000000>; | |
50 | }; | |
51 | ||
52 | cpu1: cpu@1 { | |
53 | device_type = "cpu"; | |
54 | compatible = "arm,cortex-a15"; | |
55 | reg = <0x1>; | |
56 | clock-frequency = <1800000000>; | |
57 | }; | |
58 | ||
59 | cpu2: cpu@2 { | |
60 | device_type = "cpu"; | |
61 | compatible = "arm,cortex-a15"; | |
62 | reg = <0x2>; | |
63 | clock-frequency = <1800000000>; | |
64 | }; | |
65 | ||
66 | cpu3: cpu@3 { | |
67 | device_type = "cpu"; | |
68 | compatible = "arm,cortex-a15"; | |
69 | reg = <0x3>; | |
70 | clock-frequency = <1800000000>; | |
71 | }; | |
72 | }; | |
73 | ||
92040bd6 | 74 | clock: clock-controller@10010000 { |
34dcedfb CK |
75 | compatible = "samsung,exynos5420-clock"; |
76 | reg = <0x10010000 0x30000>; | |
77 | #clock-cells = <1>; | |
78 | }; | |
79 | ||
35e82775 AB |
80 | clock_audss: audss-clock-controller@3810000 { |
81 | compatible = "samsung,exynos5420-audss-clock"; | |
82 | reg = <0x03810000 0x0C>; | |
83 | #clock-cells = <1>; | |
84 | clocks = <&clock 148>; | |
85 | clock-names = "sclk_audio"; | |
86 | }; | |
87 | ||
f09d062f AK |
88 | codec@11000000 { |
89 | compatible = "samsung,mfc-v7"; | |
90 | reg = <0x11000000 0x10000>; | |
91 | interrupts = <0 96 0>; | |
92 | clocks = <&clock 401>; | |
93 | clock-names = "mfc"; | |
94 | }; | |
95 | ||
0e2c5915 YK |
96 | mmc_0: mmc@12200000 { |
97 | compatible = "samsung,exynos5420-dw-mshc-smu"; | |
98 | interrupts = <0 75 0>; | |
99 | #address-cells = <1>; | |
100 | #size-cells = <0>; | |
101 | reg = <0x12200000 0x2000>; | |
102 | clocks = <&clock 351>, <&clock 132>; | |
103 | clock-names = "biu", "ciu"; | |
104 | fifo-depth = <0x40>; | |
105 | status = "disabled"; | |
106 | }; | |
107 | ||
108 | mmc_1: mmc@12210000 { | |
109 | compatible = "samsung,exynos5420-dw-mshc-smu"; | |
110 | interrupts = <0 76 0>; | |
111 | #address-cells = <1>; | |
112 | #size-cells = <0>; | |
113 | reg = <0x12210000 0x2000>; | |
114 | clocks = <&clock 352>, <&clock 133>; | |
115 | clock-names = "biu", "ciu"; | |
116 | fifo-depth = <0x40>; | |
117 | status = "disabled"; | |
118 | }; | |
119 | ||
120 | mmc_2: mmc@12220000 { | |
121 | compatible = "samsung,exynos5420-dw-mshc"; | |
122 | interrupts = <0 77 0>; | |
123 | #address-cells = <1>; | |
124 | #size-cells = <0>; | |
125 | reg = <0x12220000 0x1000>; | |
126 | clocks = <&clock 353>, <&clock 134>; | |
127 | clock-names = "biu", "ciu"; | |
128 | fifo-depth = <0x40>; | |
129 | status = "disabled"; | |
130 | }; | |
131 | ||
34dcedfb CK |
132 | mct@101C0000 { |
133 | compatible = "samsung,exynos4210-mct"; | |
134 | reg = <0x101C0000 0x800>; | |
135 | interrupt-controller; | |
136 | #interrups-cells = <1>; | |
137 | interrupt-parent = <&mct_map>; | |
6c16dedf CK |
138 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, |
139 | <8>, <9>, <10>, <11>; | |
34dcedfb CK |
140 | clocks = <&clock 1>, <&clock 315>; |
141 | clock-names = "fin_pll", "mct"; | |
142 | ||
143 | mct_map: mct-map { | |
144 | #interrupt-cells = <1>; | |
145 | #address-cells = <0>; | |
146 | #size-cells = <0>; | |
147 | interrupt-map = <0 &combiner 23 3>, | |
148 | <1 &combiner 23 4>, | |
149 | <2 &combiner 25 2>, | |
150 | <3 &combiner 25 3>, | |
151 | <4 &gic 0 120 0>, | |
152 | <5 &gic 0 121 0>, | |
153 | <6 &gic 0 122 0>, | |
6c16dedf CK |
154 | <7 &gic 0 123 0>, |
155 | <8 &gic 0 128 0>, | |
156 | <9 &gic 0 129 0>, | |
157 | <10 &gic 0 130 0>, | |
158 | <11 &gic 0 131 0>; | |
34dcedfb CK |
159 | }; |
160 | }; | |
161 | ||
dcfca2cc YSB |
162 | gsc_pd: power-domain@10044000 { |
163 | compatible = "samsung,exynos4210-pd"; | |
164 | reg = <0x10044000 0x20>; | |
165 | }; | |
166 | ||
167 | isp_pd: power-domain@10044020 { | |
168 | compatible = "samsung,exynos4210-pd"; | |
169 | reg = <0x10044020 0x20>; | |
170 | }; | |
171 | ||
172 | mfc_pd: power-domain@10044060 { | |
173 | compatible = "samsung,exynos4210-pd"; | |
174 | reg = <0x10044060 0x20>; | |
175 | }; | |
176 | ||
177 | disp_pd: power-domain@100440C0 { | |
178 | compatible = "samsung,exynos4210-pd"; | |
179 | reg = <0x100440C0 0x20>; | |
180 | }; | |
181 | ||
182 | mau_pd: power-domain@100440E0 { | |
183 | compatible = "samsung,exynos4210-pd"; | |
184 | reg = <0x100440E0 0x20>; | |
185 | }; | |
186 | ||
187 | g2d_pd: power-domain@10044100 { | |
188 | compatible = "samsung,exynos4210-pd"; | |
189 | reg = <0x10044100 0x20>; | |
190 | }; | |
191 | ||
192 | msc_pd: power-domain@10044120 { | |
193 | compatible = "samsung,exynos4210-pd"; | |
194 | reg = <0x10044120 0x20>; | |
195 | }; | |
196 | ||
d81c6cbe LKA |
197 | pinctrl_0: pinctrl@13400000 { |
198 | compatible = "samsung,exynos5420-pinctrl"; | |
199 | reg = <0x13400000 0x1000>; | |
200 | interrupts = <0 45 0>; | |
201 | ||
202 | wakeup-interrupt-controller { | |
203 | compatible = "samsung,exynos4210-wakeup-eint"; | |
204 | interrupt-parent = <&gic>; | |
205 | interrupts = <0 32 0>; | |
206 | }; | |
207 | }; | |
208 | ||
209 | pinctrl_1: pinctrl@13410000 { | |
210 | compatible = "samsung,exynos5420-pinctrl"; | |
211 | reg = <0x13410000 0x1000>; | |
212 | interrupts = <0 78 0>; | |
213 | }; | |
214 | ||
215 | pinctrl_2: pinctrl@14000000 { | |
216 | compatible = "samsung,exynos5420-pinctrl"; | |
217 | reg = <0x14000000 0x1000>; | |
218 | interrupts = <0 46 0>; | |
219 | }; | |
220 | ||
221 | pinctrl_3: pinctrl@14010000 { | |
222 | compatible = "samsung,exynos5420-pinctrl"; | |
223 | reg = <0x14010000 0x1000>; | |
224 | interrupts = <0 50 0>; | |
225 | }; | |
226 | ||
227 | pinctrl_4: pinctrl@03860000 { | |
228 | compatible = "samsung,exynos5420-pinctrl"; | |
229 | reg = <0x03860000 0x1000>; | |
230 | interrupts = <0 47 0>; | |
231 | }; | |
232 | ||
a81951d9 VS |
233 | rtc@101E0000 { |
234 | clocks = <&clock 317>; | |
235 | clock-names = "rtc"; | |
236 | status = "okay"; | |
237 | }; | |
238 | ||
34dcedfb CK |
239 | serial@12C00000 { |
240 | clocks = <&clock 257>, <&clock 128>; | |
241 | clock-names = "uart", "clk_uart_baud0"; | |
242 | }; | |
243 | ||
244 | serial@12C10000 { | |
245 | clocks = <&clock 258>, <&clock 129>; | |
246 | clock-names = "uart", "clk_uart_baud0"; | |
247 | }; | |
248 | ||
249 | serial@12C20000 { | |
250 | clocks = <&clock 259>, <&clock 130>; | |
251 | clock-names = "uart", "clk_uart_baud0"; | |
252 | }; | |
253 | ||
254 | serial@12C30000 { | |
255 | clocks = <&clock 260>, <&clock 131>; | |
256 | clock-names = "uart", "clk_uart_baud0"; | |
257 | }; | |
ee3381d4 | 258 | |
1339d33a VS |
259 | dp_phy: video-phy@10040728 { |
260 | compatible = "samsung,exynos5250-dp-video-phy"; | |
261 | reg = <0x10040728 4>; | |
262 | #phy-cells = <0>; | |
263 | }; | |
264 | ||
265 | dp-controller@145B0000 { | |
266 | clocks = <&clock 412>; | |
267 | clock-names = "dp"; | |
268 | phys = <&dp_phy>; | |
269 | phy-names = "dp"; | |
270 | }; | |
271 | ||
ee3381d4 VS |
272 | fimd@14400000 { |
273 | samsung,power-domain = <&disp_pd>; | |
274 | clocks = <&clock 147>, <&clock 421>; | |
275 | clock-names = "sclk_fimd", "fimd"; | |
276 | }; | |
f408f9db NKC |
277 | |
278 | adc: adc@12D10000 { | |
279 | compatible = "samsung,exynos-adc-v2"; | |
280 | reg = <0x12D10000 0x100>, <0x10040720 0x4>; | |
281 | interrupts = <0 106 0>; | |
282 | clocks = <&clock 270>; | |
283 | clock-names = "adc"; | |
284 | #io-channel-cells = <1>; | |
285 | io-channel-ranges; | |
286 | status = "disabled"; | |
287 | }; | |
f49e347b AB |
288 | |
289 | i2c_0: i2c@12C60000 { | |
290 | compatible = "samsung,s3c2440-i2c"; | |
291 | reg = <0x12C60000 0x100>; | |
292 | interrupts = <0 56 0>; | |
293 | #address-cells = <1>; | |
294 | #size-cells = <0>; | |
295 | clocks = <&clock 261>; | |
296 | clock-names = "i2c"; | |
297 | pinctrl-names = "default"; | |
298 | pinctrl-0 = <&i2c0_bus>; | |
299 | status = "disabled"; | |
300 | }; | |
301 | ||
302 | i2c_1: i2c@12C70000 { | |
303 | compatible = "samsung,s3c2440-i2c"; | |
304 | reg = <0x12C70000 0x100>; | |
305 | interrupts = <0 57 0>; | |
306 | #address-cells = <1>; | |
307 | #size-cells = <0>; | |
308 | clocks = <&clock 262>; | |
309 | clock-names = "i2c"; | |
310 | pinctrl-names = "default"; | |
311 | pinctrl-0 = <&i2c1_bus>; | |
312 | status = "disabled"; | |
313 | }; | |
314 | ||
315 | i2c_2: i2c@12C80000 { | |
316 | compatible = "samsung,s3c2440-i2c"; | |
317 | reg = <0x12C80000 0x100>; | |
318 | interrupts = <0 58 0>; | |
319 | #address-cells = <1>; | |
320 | #size-cells = <0>; | |
321 | clocks = <&clock 263>; | |
322 | clock-names = "i2c"; | |
323 | pinctrl-names = "default"; | |
324 | pinctrl-0 = <&i2c2_bus>; | |
325 | status = "disabled"; | |
326 | }; | |
327 | ||
328 | i2c_3: i2c@12C90000 { | |
329 | compatible = "samsung,s3c2440-i2c"; | |
330 | reg = <0x12C90000 0x100>; | |
331 | interrupts = <0 59 0>; | |
332 | #address-cells = <1>; | |
333 | #size-cells = <0>; | |
334 | clocks = <&clock 264>; | |
335 | clock-names = "i2c"; | |
336 | pinctrl-names = "default"; | |
337 | pinctrl-0 = <&i2c3_bus>; | |
338 | status = "disabled"; | |
339 | }; | |
b0e505ce RS |
340 | |
341 | hdmi@14530000 { | |
342 | compatible = "samsung,exynos4212-hdmi"; | |
343 | reg = <0x14530000 0x70000>; | |
344 | interrupts = <0 95 0>; | |
345 | clocks = <&clock 413>, <&clock 143>, <&clock 768>, | |
346 | <&clock 158>, <&clock 640>; | |
347 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", | |
348 | "sclk_hdmiphy", "mout_hdmi"; | |
349 | status = "disabled"; | |
350 | }; | |
351 | ||
352 | mixer@14450000 { | |
353 | compatible = "samsung,exynos5420-mixer"; | |
354 | reg = <0x14450000 0x10000>; | |
355 | interrupts = <0 94 0>; | |
356 | clocks = <&clock 431>, <&clock 143>; | |
357 | clock-names = "mixer", "sclk_hdmi"; | |
358 | }; | |
01eb4636 LKA |
359 | |
360 | gsc_0: video-scaler@13e00000 { | |
361 | compatible = "samsung,exynos5-gsc"; | |
362 | reg = <0x13e00000 0x1000>; | |
363 | interrupts = <0 85 0>; | |
364 | clocks = <&clock 465>; | |
365 | clock-names = "gscl"; | |
366 | samsung,power-domain = <&gsc_pd>; | |
367 | }; | |
368 | ||
369 | gsc_1: video-scaler@13e10000 { | |
370 | compatible = "samsung,exynos5-gsc"; | |
371 | reg = <0x13e10000 0x1000>; | |
372 | interrupts = <0 86 0>; | |
373 | clocks = <&clock 466>; | |
374 | clock-names = "gscl"; | |
375 | samsung,power-domain = <&gsc_pd>; | |
376 | }; | |
34dcedfb | 377 | }; |