]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - arch/arm/boot/dts/exynos5420.dtsi
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: exynos: Add initial support for Odroid XU board
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / exynos5420.dtsi
CommitLineData
34dcedfb
CK		 1/*
2 * SAMSUNG EXYNOS5420 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
c9cf996d 16#include "exynos54xx.dtsi"
1dd4e599 17#include <dt-bindings/clock/exynos5420.h>
602408e3 18#include <dt-bindings/clock/exynos-audss-clk.h>
35e82775 19
34dcedfb 20/ {
8bdb31b4 21 compatible = "samsung,exynos5420", "samsung,exynos5";
34dcedfb 22
d81c6cbe 23 aliases {
0e2c5915
YK		 24 mshc0 = &mmc_0;
25 mshc1 = &mmc_1;
26 mshc2 = &mmc_2;
d81c6cbe
LKA		 27 pinctrl0 = &pinctrl_0;
28 pinctrl1 = &pinctrl_1;
29 pinctrl2 = &pinctrl_2;
30 pinctrl3 = &pinctrl_3;
31 pinctrl4 = &pinctrl_4;
1a9110d6
SK		 32 i2c4 = &hsi2c_4;
33 i2c5 = &hsi2c_5;
34 i2c6 = &hsi2c_6;
35 i2c7 = &hsi2c_7;
36 i2c8 = &hsi2c_8;
37 i2c9 = &hsi2c_9;
38 i2c10 = &hsi2c_10;
01eb4636
LKA		 39 gsc0 = &gsc_0;
40 gsc1 = &gsc_1;
e84a2d91
LKA		 41 spi0 = &spi_0;
42 spi1 = &spi_1;
43 spi2 = &spi_2;
d81c6cbe
LKA		 44 };
45
4f0d20ec
KK		 46 /*
47 * The 'cpus' node is not present here but instead it is provided
48 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
49 */
5b56642b 50
5d99cc59
KK		 51 soc: soc {
52 cluster_a15_opp_table: opp_table0 {
53 compatible = "operating-points-v2";
54 opp-shared;
55 opp@1800000000 {
56 opp-hz = /bits/ 64 <1800000000>;
57 opp-microvolt = <1250000>;
58 clock-latency-ns = <140000>;
59 };
60 opp@1700000000 {
61 opp-hz = /bits/ 64 <1700000000>;
62 opp-microvolt = <1212500>;
63 clock-latency-ns = <140000>;
64 };
65 opp@1600000000 {
66 opp-hz = /bits/ 64 <1600000000>;
67 opp-microvolt = <1175000>;
68 clock-latency-ns = <140000>;
69 };
70 opp@1500000000 {
71 opp-hz = /bits/ 64 <1500000000>;
72 opp-microvolt = <1137500>;
73 clock-latency-ns = <140000>;
74 };
75 opp@1400000000 {
76 opp-hz = /bits/ 64 <1400000000>;
77 opp-microvolt = <1112500>;
78 clock-latency-ns = <140000>;
79 };
80 opp@1300000000 {
81 opp-hz = /bits/ 64 <1300000000>;
82 opp-microvolt = <1062500>;
83 clock-latency-ns = <140000>;
84 };
85 opp@1200000000 {
86 opp-hz = /bits/ 64 <1200000000>;
87 opp-microvolt = <1037500>;
88 clock-latency-ns = <140000>;
89 };
90 opp@1100000000 {
91 opp-hz = /bits/ 64 <1100000000>;
92 opp-microvolt = <1012500>;
93 clock-latency-ns = <140000>;
94 };
95 opp@1000000000 {
96 opp-hz = /bits/ 64 <1000000000>;
97 opp-microvolt = < 987500>;
98 clock-latency-ns = <140000>;
99 };
100 opp@900000000 {
101 opp-hz = /bits/ 64 <900000000>;
102 opp-microvolt = < 962500>;
103 clock-latency-ns = <140000>;
104 };
105 opp@800000000 {
106 opp-hz = /bits/ 64 <800000000>;
107 opp-microvolt = < 937500>;
108 clock-latency-ns = <140000>;
109 };
110 opp@700000000 {
111 opp-hz = /bits/ 64 <700000000>;
112 opp-microvolt = < 912500>;
113 clock-latency-ns = <140000>;
114 };
115 };
116
117 cluster_a7_opp_table: opp_table1 {
118 compatible = "operating-points-v2";
119 opp-shared;
120 opp@1300000000 {
121 opp-hz = /bits/ 64 <1300000000>;
122 opp-microvolt = <1275000>;
123 clock-latency-ns = <140000>;
124 };
125 opp@1200000000 {
126 opp-hz = /bits/ 64 <1200000000>;
127 opp-microvolt = <1212500>;
128 clock-latency-ns = <140000>;
129 };
130 opp@1100000000 {
131 opp-hz = /bits/ 64 <1100000000>;
132 opp-microvolt = <1162500>;
133 clock-latency-ns = <140000>;
134 };
135 opp@1000000000 {
136 opp-hz = /bits/ 64 <1000000000>;
137 opp-microvolt = <1112500>;
138 clock-latency-ns = <140000>;
139 };
140 opp@900000000 {
141 opp-hz = /bits/ 64 <900000000>;
142 opp-microvolt = <1062500>;
143 clock-latency-ns = <140000>;
144 };
145 opp@800000000 {
146 opp-hz = /bits/ 64 <800000000>;
147 opp-microvolt = <1025000>;
148 clock-latency-ns = <140000>;
149 };
150 opp@700000000 {
151 opp-hz = /bits/ 64 <700000000>;
152 opp-microvolt = <975000>;
153 clock-latency-ns = <140000>;
154 };
155 opp@600000000 {
156 opp-hz = /bits/ 64 <600000000>;
157 opp-microvolt = <937500>;
158 clock-latency-ns = <140000>;
159 };
160 };
161
162 cci: cci@10d20000 {
163 compatible = "arm,cci-400";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 reg = <0x10d20000 0x1000>;
167 ranges = <0x0 0x10d20000 0x6000>;
168
169 cci_control0: slave-if@4000 {
170 compatible = "arm,cci-400-ctrl-if";
171 interface-type = "ace";
172 reg = <0x4000 0x1000>;
173 };
174 cci_control1: slave-if@5000 {
175 compatible = "arm,cci-400-ctrl-if";
176 interface-type = "ace";
177 reg = <0x5000 0x1000>;
178 };
179 };
180
5d99cc59
KK		 181 clock: clock-controller@10010000 {
182 compatible = "samsung,exynos5420-clock";
183 reg = <0x10010000 0x30000>;
184 #clock-cells = <1>;
185 };
186
187 clock_audss: audss-clock-controller@3810000 {
188 compatible = "samsung,exynos5420-audss-clock";
189 reg = <0x03810000 0x0C>;
190 #clock-cells = <1>;
191 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
192 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
193 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
194 };
195
196 mfc: codec@11000000 {
197 compatible = "samsung,mfc-v7";
198 reg = <0x11000000 0x10000>;
199 interrupts = <0 96 0>;
200 clocks = <&clock CLK_MFC>;
201 clock-names = "mfc";
202 power-domains = <&mfc_pd>;
203 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
204 iommu-names = "left", "right";
205 };
206
207 mmc_0: mmc@12200000 {
208 compatible = "samsung,exynos5420-dw-mshc-smu";
209 interrupts = <0 75 0>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212 reg = <0x12200000 0x2000>;
213 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
214 clock-names = "biu", "ciu";
215 fifo-depth = <0x40>;
216 status = "disabled";
1c0e0854 217 };
b3205dea 218
5d99cc59
KK		 219 mmc_1: mmc@12210000 {
220 compatible = "samsung,exynos5420-dw-mshc-smu";
221 interrupts = <0 76 0>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224 reg = <0x12210000 0x2000>;
225 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
226 clock-names = "biu", "ciu";
227 fifo-depth = <0x40>;
228 status = "disabled";
b3205dea
SK		 229 };
230
5d99cc59
KK		 231 mmc_2: mmc@12220000 {
232 compatible = "samsung,exynos5420-dw-mshc";
233 interrupts = <0 77 0>;
234 #address-cells = <1>;
235 #size-cells = <0>;
236 reg = <0x12220000 0x1000>;
237 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
238 clock-names = "biu", "ciu";
239 fifo-depth = <0x40>;
240 status = "disabled";
1c0e0854 241 };
f09d062f 242
5d99cc59
KK		 243 nocp_mem0_0: nocp@10CA1000 {
244 compatible = "samsung,exynos5420-nocp";
245 reg = <0x10CA1000 0x200>;
246 status = "disabled";
34dcedfb 247 };
dcfca2cc 248
5d99cc59
KK		 249 nocp_mem0_1: nocp@10CA1400 {
250 compatible = "samsung,exynos5420-nocp";
251 reg = <0x10CA1400 0x200>;
252 status = "disabled";
d81c6cbe 253 };
d81c6cbe 254
5d99cc59
KK		 255 nocp_mem1_0: nocp@10CA1800 {
256 compatible = "samsung,exynos5420-nocp";
257 reg = <0x10CA1800 0x200>;
e6015c1f 258 status = "disabled";
e3188533 259 };
655de648 260
5d99cc59
KK		 261 nocp_mem1_1: nocp@10CA1C00 {
262 compatible = "samsung,exynos5420-nocp";
263 reg = <0x10CA1C00 0x200>;
264 status = "disabled";
9843a223 265 };
3cb7d1cd 266
5d99cc59
KK		 267 nocp_g3d_0: nocp@11A51000 {
268 compatible = "samsung,exynos5420-nocp";
269 reg = <0x11A51000 0x200>;
270 status = "disabled";
f070267b 271 };
f070267b 272
5d99cc59
KK		 273 nocp_g3d_1: nocp@11A51400 {
274 compatible = "samsung,exynos5420-nocp";
275 reg = <0x11A51400 0x200>;
276 status = "disabled";
f070267b 277 };
8d53526f 278
5d99cc59
KK		 279 gsc_pd: power-domain@10044000 {
280 compatible = "samsung,exynos4210-pd";
281 reg = <0x10044000 0x20>;
282 #power-domain-cells = <0>;
283 clocks = <&clock CLK_FIN_PLL>,
284 <&clock CLK_MOUT_USER_ACLK300_GSCL>,
285 <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
286 clock-names = "oscclk", "clk0", "asb0", "asb1";
6674fd92 287 };
6674fd92 288
5d99cc59
KK		 289 isp_pd: power-domain@10044020 {
290 compatible = "samsung,exynos4210-pd";
291 reg = <0x10044020 0x20>;
292 #power-domain-cells = <0>;
6674fd92 293 };
b7004516 294
5d99cc59
KK		 295 mfc_pd: power-domain@10044060 {
296 compatible = "samsung,exynos4210-pd";
297 reg = <0x10044060 0x20>;
298 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
299 clock-names = "oscclk", "clk0";
300 #power-domain-cells = <0>;
b04a62d3 301 };
b04a62d3 302
5d99cc59
KK		 303 msc_pd: power-domain@10044120 {
304 compatible = "samsung,exynos4210-pd";
305 reg = <0x10044120 0x20>;
306 #power-domain-cells = <0>;
b04a62d3 307 };
b04a62d3 308
5d99cc59
KK		 309 disp_pd: power-domain@100440C0 {
310 compatible = "samsung,exynos4210-pd";
311 reg = <0x100440C0 0x20>;
312 #power-domain-cells = <0>;
313 clocks = <&clock CLK_FIN_PLL>,
314 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
315 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
316 <&clock CLK_MOUT_USER_ACLK400_DISP1>,
317 <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
318 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
b04a62d3 319 };
b04a62d3 320
5d99cc59
KK		 321 pinctrl_0: pinctrl@13400000 {
322 compatible = "samsung,exynos5420-pinctrl";
323 reg = <0x13400000 0x1000>;
324 interrupts = <0 45 0>;
b04a62d3 325
5d99cc59
KK		 326 wakeup-interrupt-controller {
327 compatible = "samsung,exynos4210-wakeup-eint";
328 interrupt-parent = <&gic>;
329 interrupts = <0 32 0>;
330 };
b04a62d3 331 };
b04a62d3 332
5d99cc59
KK		 333 pinctrl_1: pinctrl@13410000 {
334 compatible = "samsung,exynos5420-pinctrl";
335 reg = <0x13410000 0x1000>;
336 interrupts = <0 78 0>;
b04a62d3 337 };
5d99cc59
KK		 338
339 pinctrl_2: pinctrl@14000000 {
340 compatible = "samsung,exynos5420-pinctrl";
341 reg = <0x14000000 0x1000>;
342 interrupts = <0 46 0>;
b04a62d3 343 };
5d99cc59
KK		 344
345 pinctrl_3: pinctrl@14010000 {
346 compatible = "samsung,exynos5420-pinctrl";
347 reg = <0x14010000 0x1000>;
348 interrupts = <0 50 0>;
b04a62d3 349 };
5d99cc59
KK		 350
351 pinctrl_4: pinctrl@03860000 {
352 compatible = "samsung,exynos5420-pinctrl";
353 reg = <0x03860000 0x1000>;
354 interrupts = <0 47 0>;
b04a62d3 355 };
5d99cc59
KK		 356
357 amba {
358 #address-cells = <1>;
359 #size-cells = <1>;
360 compatible = "simple-bus";
361 interrupt-parent = <&gic>;
362 ranges;
363
364 adma: adma@03880000 {
365 compatible = "arm,pl330", "arm,primecell";
366 reg = <0x03880000 0x1000>;
367 interrupts = <0 110 0>;
368 clocks = <&clock_audss EXYNOS_ADMA>;
369 clock-names = "apb_pclk";
370 #dma-cells = <1>;
371 #dma-channels = <6>;
372 #dma-requests = <16>;
373 };
374
375 pdma0: pdma@121A0000 {
376 compatible = "arm,pl330", "arm,primecell";
377 reg = <0x121A0000 0x1000>;
378 interrupts = <0 34 0>;
379 clocks = <&clock CLK_PDMA0>;
380 clock-names = "apb_pclk";
381 #dma-cells = <1>;
382 #dma-channels = <8>;
383 #dma-requests = <32>;
384 };
385
386 pdma1: pdma@121B0000 {
387 compatible = "arm,pl330", "arm,primecell";
388 reg = <0x121B0000 0x1000>;
389 interrupts = <0 35 0>;
390 clocks = <&clock CLK_PDMA1>;
391 clock-names = "apb_pclk";
392 #dma-cells = <1>;
393 #dma-channels = <8>;
394 #dma-requests = <32>;
395 };
396
397 mdma0: mdma@10800000 {
398 compatible = "arm,pl330", "arm,primecell";
399 reg = <0x10800000 0x1000>;
400 interrupts = <0 33 0>;
401 clocks = <&clock CLK_MDMA0>;
402 clock-names = "apb_pclk";
403 #dma-cells = <1>;
404 #dma-channels = <8>;
405 #dma-requests = <1>;
406 };
407
408 mdma1: mdma@11C10000 {
409 compatible = "arm,pl330", "arm,primecell";
410 reg = <0x11C10000 0x1000>;
411 interrupts = <0 124 0>;
412 clocks = <&clock CLK_MDMA1>;
413 clock-names = "apb_pclk";
414 #dma-cells = <1>;
415 #dma-channels = <8>;
416 #dma-requests = <1>;
417 /*
418 * MDMA1 can support both secure and non-secure
419 * AXI transactions. When this is enabled in
420 * the kernel for boards that run in secure
421 * mode, we are getting imprecise external
422 * aborts causing the kernel to oops.
423 */
424 status = "disabled";
425 };
426 };
427
428 i2s0: i2s@03830000 {
429 compatible = "samsung,exynos5420-i2s";
430 reg = <0x03830000 0x100>;
431 dmas = <&adma 0
432 &adma 2
433 &adma 1>;
434 dma-names = "tx", "rx", "tx-sec";
435 clocks = <&clock_audss EXYNOS_I2S_BUS>,
436 <&clock_audss EXYNOS_I2S_BUS>,
437 <&clock_audss EXYNOS_SCLK_I2S>;
438 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
439 #clock-cells = <1>;
440 clock-output-names = "i2s_cdclk0";
441 #sound-dai-cells = <1>;
442 samsung,idma-addr = <0x03000000>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&i2s0_bus>;
445 status = "disabled";
b04a62d3 446 };
b04a62d3 447
5d99cc59
KK		 448 i2s1: i2s@12D60000 {
449 compatible = "samsung,exynos5420-i2s";
450 reg = <0x12D60000 0x100>;
451 dmas = <&pdma1 12
452 &pdma1 11>;
453 dma-names = "tx", "rx";
454 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
455 clock-names = "iis", "i2s_opclk0";
456 #clock-cells = <1>;
457 clock-output-names = "i2s_cdclk1";
458 #sound-dai-cells = <1>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&i2s1_bus>;
461 status = "disabled";
462 };
b04a62d3 463
5d99cc59
KK		 464 i2s2: i2s@12D70000 {
465 compatible = "samsung,exynos5420-i2s";
466 reg = <0x12D70000 0x100>;
467 dmas = <&pdma0 12
468 &pdma0 11>;
469 dma-names = "tx", "rx";
470 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
471 clock-names = "iis", "i2s_opclk0";
472 #clock-cells = <1>;
473 clock-output-names = "i2s_cdclk2";
474 #sound-dai-cells = <1>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&i2s2_bus>;
477 status = "disabled";
b04a62d3 478 };
5d99cc59
KK		 479
480 spi_0: spi@12d20000 {
481 compatible = "samsung,exynos4210-spi";
482 reg = <0x12d20000 0x100>;
483 interrupts = <0 68 0>;
484 dmas = <&pdma0 5
485 &pdma0 4>;
486 dma-names = "tx", "rx";
487 #address-cells = <1>;
488 #size-cells = <0>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&spi0_bus>;
491 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
492 clock-names = "spi", "spi_busclk0";
493 status = "disabled";
b04a62d3 494 };
5d99cc59
KK		 495
496 spi_1: spi@12d30000 {
497 compatible = "samsung,exynos4210-spi";
498 reg = <0x12d30000 0x100>;
499 interrupts = <0 69 0>;
500 dmas = <&pdma1 5
501 &pdma1 4>;
502 dma-names = "tx", "rx";
503 #address-cells = <1>;
504 #size-cells = <0>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&spi1_bus>;
507 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
508 clock-names = "spi", "spi_busclk0";
509 status = "disabled";
b04a62d3 510 };
5d99cc59
KK		 511
512 spi_2: spi@12d40000 {
513 compatible = "samsung,exynos4210-spi";
514 reg = <0x12d40000 0x100>;
515 interrupts = <0 70 0>;
516 dmas = <&pdma0 7
517 &pdma0 6>;
518 dma-names = "tx", "rx";
519 #address-cells = <1>;
520 #size-cells = <0>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&spi2_bus>;
523 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
524 clock-names = "spi", "spi_busclk0";
525 status = "disabled";
b04a62d3 526 };
b04a62d3 527
5d99cc59
KK		 528 dp_phy: dp-video-phy {
529 compatible = "samsung,exynos5420-dp-video-phy";
530 samsung,pmu-syscon = <&pmu_system_controller>;
531 #phy-cells = <0>;
532 };
b04a62d3 533
5d99cc59
KK		 534 mipi_phy: mipi-video-phy {
535 compatible = "samsung,s5pv210-mipi-video-phy";
536 syscon = <&pmu_system_controller>;
537 #phy-cells = <1>;
b04a62d3 538 };
b04a62d3 539
5d99cc59
KK		 540 dsi@14500000 {
541 compatible = "samsung,exynos5410-mipi-dsi";
542 reg = <0x14500000 0x10000>;
543 interrupts = <0 82 0>;
544 phys = <&mipi_phy 1>;
545 phy-names = "dsim";
546 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
547 clock-names = "bus_clk", "pll_clk";
548 #address-cells = <1>;
549 #size-cells = <0>;
550 status = "disabled";
551 };
b04a62d3 552
5d99cc59
KK		 553 adc: adc@12D10000 {
554 compatible = "samsung,exynos-adc-v2";
555 reg = <0x12D10000 0x100>;
556 interrupts = <0 106 0>;
557 clocks = <&clock CLK_TSADC>;
558 clock-names = "adc";
559 #io-channel-cells = <1>;
560 io-channel-ranges;
561 samsung,syscon-phandle = <&pmu_system_controller>;
562 status = "disabled";
b04a62d3 563 };
5d99cc59
KK		 564
565 /* i2c_0-3 are defined in exynos5.dtsi */
566 hsi2c_4: i2c@12CA0000 {
567 compatible = "samsung,exynos5250-hsi2c";
568 reg = <0x12CA0000 0x1000>;
569 interrupts = <0 60 0>;
570 #address-cells = <1>;
571 #size-cells = <0>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c4_hs_bus>;
574 clocks = <&clock CLK_USI0>;
575 clock-names = "hsi2c";
576 status = "disabled";
b04a62d3 577 };
5d99cc59
KK		 578
579 hsi2c_5: i2c@12CB0000 {
580 compatible = "samsung,exynos5250-hsi2c";
581 reg = <0x12CB0000 0x1000>;
582 interrupts = <0 61 0>;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&i2c5_hs_bus>;
587 clocks = <&clock CLK_USI1>;
588 clock-names = "hsi2c";
589 status = "disabled";
b04a62d3 590 };
5d99cc59
KK		 591
592 hsi2c_6: i2c@12CC0000 {
593 compatible = "samsung,exynos5250-hsi2c";
594 reg = <0x12CC0000 0x1000>;
595 interrupts = <0 62 0>;
596 #address-cells = <1>;
597 #size-cells = <0>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&i2c6_hs_bus>;
600 clocks = <&clock CLK_USI2>;
601 clock-names = "hsi2c";
602 status = "disabled";
b04a62d3 603 };
5d99cc59
KK		 604
605 hsi2c_7: i2c@12CD0000 {
606 compatible = "samsung,exynos5250-hsi2c";
607 reg = <0x12CD0000 0x1000>;
608 interrupts = <0 63 0>;
609 #address-cells = <1>;
610 #size-cells = <0>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&i2c7_hs_bus>;
613 clocks = <&clock CLK_USI3>;
614 clock-names = "hsi2c";
615 status = "disabled";
b04a62d3 616 };
b04a62d3 617
5d99cc59
KK		 618 hsi2c_8: i2c@12E00000 {
619 compatible = "samsung,exynos5250-hsi2c";
620 reg = <0x12E00000 0x1000>;
621 interrupts = <0 87 0>;
622 #address-cells = <1>;
623 #size-cells = <0>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&i2c8_hs_bus>;
626 clocks = <&clock CLK_USI4>;
627 clock-names = "hsi2c";
628 status = "disabled";
629 };
b04a62d3 630
5d99cc59
KK		 631 hsi2c_9: i2c@12E10000 {
632 compatible = "samsung,exynos5250-hsi2c";
633 reg = <0x12E10000 0x1000>;
634 interrupts = <0 88 0>;
635 #address-cells = <1>;
636 #size-cells = <0>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&i2c9_hs_bus>;
639 clocks = <&clock CLK_USI5>;
640 clock-names = "hsi2c";
641 status = "disabled";
b04a62d3 642 };
5d99cc59
KK		 643
644 hsi2c_10: i2c@12E20000 {
645 compatible = "samsung,exynos5250-hsi2c";
646 reg = <0x12E20000 0x1000>;
647 interrupts = <0 203 0>;
648 #address-cells = <1>;
649 #size-cells = <0>;
650 pinctrl-names = "default";
651 pinctrl-0 = <&i2c10_hs_bus>;
652 clocks = <&clock CLK_USI6>;
653 clock-names = "hsi2c";
654 status = "disabled";
b04a62d3 655 };
5d99cc59
KK		 656
657 hdmi: hdmi@14530000 {
658 compatible = "samsung,exynos5420-hdmi";
659 reg = <0x14530000 0x70000>;
660 interrupts = <0 95 0>;
661 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
662 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
663 <&clock CLK_MOUT_HDMI>;
664 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
665 "sclk_hdmiphy", "mout_hdmi";
666 phy = <&hdmiphy>;
667 samsung,syscon-phandle = <&pmu_system_controller>;
668 status = "disabled";
669 power-domains = <&disp_pd>;
670 };
671
672 hdmiphy: hdmiphy@145D0000 {
673 reg = <0x145D0000 0x20>;
674 };
675
676 mixer: mixer@14450000 {
677 compatible = "samsung,exynos5420-mixer";
678 reg = <0x14450000 0x10000>;
679 interrupts = <0 94 0>;
680 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
681 <&clock CLK_SCLK_HDMI>;
682 clock-names = "mixer", "hdmi", "sclk_hdmi";
683 power-domains = <&disp_pd>;
684 iommus = <&sysmmu_tv>;
685 };
686
687 rotator: rotator@11C00000 {
688 compatible = "samsung,exynos5250-rotator";
689 reg = <0x11C00000 0x64>;
690 interrupts = <0 84 0>;
691 clocks = <&clock CLK_ROTATOR>;
692 clock-names = "rotator";
693 iommus = <&sysmmu_rotator>;
694 };
695
696 gsc_0: video-scaler@13e00000 {
697 compatible = "samsung,exynos5-gsc";
698 reg = <0x13e00000 0x1000>;
699 interrupts = <0 85 0>;
700 clocks = <&clock CLK_GSCL0>;
701 clock-names = "gscl";
702 power-domains = <&gsc_pd>;
703 iommus = <&sysmmu_gscl0>;
704 };
705
706 gsc_1: video-scaler@13e10000 {
707 compatible = "samsung,exynos5-gsc";
708 reg = <0x13e10000 0x1000>;
709 interrupts = <0 86 0>;
710 clocks = <&clock CLK_GSCL1>;
711 clock-names = "gscl";
712 power-domains = <&gsc_pd>;
713 iommus = <&sysmmu_gscl1>;
714 };
715
716 jpeg_0: jpeg@11F50000 {
717 compatible = "samsung,exynos5420-jpeg";
718 reg = <0x11F50000 0x1000>;
719 interrupts = <0 89 0>;
720 clock-names = "jpeg";
721 clocks = <&clock CLK_JPEG>;
722 iommus = <&sysmmu_jpeg0>;
723 };
724
725 jpeg_1: jpeg@11F60000 {
726 compatible = "samsung,exynos5420-jpeg";
727 reg = <0x11F60000 0x1000>;
728 interrupts = <0 168 0>;
729 clock-names = "jpeg";
730 clocks = <&clock CLK_JPEG2>;
731 iommus = <&sysmmu_jpeg1>;
732 };
733
734 pmu_system_controller: system-controller@10040000 {
735 compatible = "samsung,exynos5420-pmu", "syscon";
736 reg = <0x10040000 0x5000>;
737 clock-names = "clkout16";
738 clocks = <&clock CLK_FIN_PLL>;
739 #clock-cells = <1>;
740 interrupt-controller;
741 #interrupt-cells = <3>;
742 interrupt-parent = <&gic>;
b04a62d3 743 };
5d99cc59
KK		 744
745 tmu_cpu0: tmu@10060000 {
746 compatible = "samsung,exynos5420-tmu";
747 reg = <0x10060000 0x100>;
748 interrupts = <0 65 0>;
749 clocks = <&clock CLK_TMU>;
750 clock-names = "tmu_apbif";
751 #include "exynos4412-tmu-sensor-conf.dtsi"
752 };
753
754 tmu_cpu1: tmu@10064000 {
755 compatible = "samsung,exynos5420-tmu";
756 reg = <0x10064000 0x100>;
757 interrupts = <0 183 0>;
758 clocks = <&clock CLK_TMU>;
759 clock-names = "tmu_apbif";
760 #include "exynos4412-tmu-sensor-conf.dtsi"
761 };
762
763 tmu_cpu2: tmu@10068000 {
764 compatible = "samsung,exynos5420-tmu-ext-triminfo";
765 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
766 interrupts = <0 184 0>;
767 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
768 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
769 #include "exynos4412-tmu-sensor-conf.dtsi"
770 };
771
772 tmu_cpu3: tmu@1006c000 {
773 compatible = "samsung,exynos5420-tmu-ext-triminfo";
774 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
775 interrupts = <0 185 0>;
776 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
777 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
778 #include "exynos4412-tmu-sensor-conf.dtsi"
779 };
780
781 tmu_gpu: tmu@100a0000 {
782 compatible = "samsung,exynos5420-tmu-ext-triminfo";
783 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
784 interrupts = <0 215 0>;
785 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
786 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
787 #include "exynos4412-tmu-sensor-conf.dtsi"
788 };
789
790 watchdog: watchdog@101D0000 {
791 compatible = "samsung,exynos5420-wdt";
792 reg = <0x101D0000 0x100>;
793 interrupts = <0 42 0>;
794 clocks = <&clock CLK_WDT>;
795 clock-names = "watchdog";
796 samsung,syscon-phandle = <&pmu_system_controller>;
797 };
798
799 sss: sss@10830000 {
800 compatible = "samsung,exynos4210-secss";
801 reg = <0x10830000 0x300>;
802 interrupts = <0 112 0>;
803 clocks = <&clock CLK_SSS>;
804 clock-names = "secss";
805 };
806
5d99cc59
KK		 807 sysmmu_g2dr: sysmmu@0x10A60000 {
808 compatible = "samsung,exynos-sysmmu";
809 reg = <0x10A60000 0x1000>;
810 interrupt-parent = <&combiner>;
811 interrupts = <24 5>;
812 clock-names = "sysmmu", "master";
813 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
814 #iommu-cells = <0>;
815 };
816
817 sysmmu_g2dw: sysmmu@0x10A70000 {
818 compatible = "samsung,exynos-sysmmu";
819 reg = <0x10A70000 0x1000>;
820 interrupt-parent = <&combiner>;
821 interrupts = <22 2>;
822 clock-names = "sysmmu", "master";
823 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
824 #iommu-cells = <0>;
825 };
826
827 sysmmu_tv: sysmmu@0x14650000 {
828 compatible = "samsung,exynos-sysmmu";
829 reg = <0x14650000 0x1000>;
830 interrupt-parent = <&combiner>;
831 interrupts = <7 4>;
832 clock-names = "sysmmu", "master";
833 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
834 power-domains = <&disp_pd>;
835 #iommu-cells = <0>;
836 };
837
838 sysmmu_gscl0: sysmmu@0x13E80000 {
839 compatible = "samsung,exynos-sysmmu";
840 reg = <0x13E80000 0x1000>;
841 interrupt-parent = <&combiner>;
842 interrupts = <2 0>;
843 clock-names = "sysmmu", "master";
844 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
845 power-domains = <&gsc_pd>;
846 #iommu-cells = <0>;
847 };
848
849 sysmmu_gscl1: sysmmu@0x13E90000 {
850 compatible = "samsung,exynos-sysmmu";
851 reg = <0x13E90000 0x1000>;
852 interrupt-parent = <&combiner>;
853 interrupts = <2 2>;
854 clock-names = "sysmmu", "master";
855 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
856 power-domains = <&gsc_pd>;
857 #iommu-cells = <0>;
858 };
859
860 sysmmu_scaler0r: sysmmu@0x12880000 {
861 compatible = "samsung,exynos-sysmmu";
862 reg = <0x12880000 0x1000>;
863 interrupt-parent = <&combiner>;
864 interrupts = <22 4>;
865 clock-names = "sysmmu", "master";
866 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
867 #iommu-cells = <0>;
868 };
869
870 sysmmu_scaler1r: sysmmu@0x12890000 {
871 compatible = "samsung,exynos-sysmmu";
872 reg = <0x12890000 0x1000>;
873 interrupts = <0 186 0>;
874 clock-names = "sysmmu", "master";
875 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
876 #iommu-cells = <0>;
877 };
878
879 sysmmu_scaler2r: sysmmu@0x128A0000 {
880 compatible = "samsung,exynos-sysmmu";
881 reg = <0x128A0000 0x1000>;
882 interrupts = <0 188 0>;
883 clock-names = "sysmmu", "master";
884 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
885 #iommu-cells = <0>;
886 };
887
888 sysmmu_scaler0w: sysmmu@0x128C0000 {
889 compatible = "samsung,exynos-sysmmu";
890 reg = <0x128C0000 0x1000>;
891 interrupt-parent = <&combiner>;
892 interrupts = <27 2>;
893 clock-names = "sysmmu", "master";
894 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
895 #iommu-cells = <0>;
896 };
897
898 sysmmu_scaler1w: sysmmu@0x128D0000 {
899 compatible = "samsung,exynos-sysmmu";
900 reg = <0x128D0000 0x1000>;
901 interrupt-parent = <&combiner>;
902 interrupts = <22 6>;
903 clock-names = "sysmmu", "master";
904 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
905 #iommu-cells = <0>;
906 };
907
908 sysmmu_scaler2w: sysmmu@0x128E0000 {
909 compatible = "samsung,exynos-sysmmu";
910 reg = <0x128E0000 0x1000>;
911 interrupt-parent = <&combiner>;
912 interrupts = <19 6>;
913 clock-names = "sysmmu", "master";
914 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
915 #iommu-cells = <0>;
916 };
917
918 sysmmu_rotator: sysmmu@0x11D40000 {
919 compatible = "samsung,exynos-sysmmu";
920 reg = <0x11D40000 0x1000>;
921 interrupt-parent = <&combiner>;
922 interrupts = <4 0>;
923 clock-names = "sysmmu", "master";
924 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
925 #iommu-cells = <0>;
926 };
927
928 sysmmu_jpeg0: sysmmu@0x11F10000 {
929 compatible = "samsung,exynos-sysmmu";
930 reg = <0x11F10000 0x1000>;
931 interrupt-parent = <&combiner>;
932 interrupts = <4 2>;
933 clock-names = "sysmmu", "master";
934 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
935 #iommu-cells = <0>;
936 };
937
938 sysmmu_jpeg1: sysmmu@0x11F20000 {
939 compatible = "samsung,exynos-sysmmu";
940 reg = <0x11F20000 0x1000>;
941 interrupts = <0 169 0>;
942 clock-names = "sysmmu", "master";
943 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
944 #iommu-cells = <0>;
945 };
946
947 sysmmu_mfc_l: sysmmu@0x11200000 {
948 compatible = "samsung,exynos-sysmmu";
949 reg = <0x11200000 0x1000>;
950 interrupt-parent = <&combiner>;
951 interrupts = <6 2>;
952 clock-names = "sysmmu", "master";
953 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
954 power-domains = <&mfc_pd>;
955 #iommu-cells = <0>;
956 };
957
958 sysmmu_mfc_r: sysmmu@0x11210000 {
959 compatible = "samsung,exynos-sysmmu";
960 reg = <0x11210000 0x1000>;
961 interrupt-parent = <&combiner>;
962 interrupts = <8 5>;
963 clock-names = "sysmmu", "master";
964 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
965 power-domains = <&mfc_pd>;
966 #iommu-cells = <0>;
967 };
968
969 sysmmu_fimd1_0: sysmmu@0x14640000 {
970 compatible = "samsung,exynos-sysmmu";
971 reg = <0x14640000 0x1000>;
972 interrupt-parent = <&combiner>;
973 interrupts = <3 2>;
974 clock-names = "sysmmu", "master";
975 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
976 power-domains = <&disp_pd>;
977 #iommu-cells = <0>;
978 };
979
980 sysmmu_fimd1_1: sysmmu@0x14680000 {
981 compatible = "samsung,exynos-sysmmu";
982 reg = <0x14680000 0x1000>;
983 interrupt-parent = <&combiner>;
984 interrupts = <3 0>;
985 clock-names = "sysmmu", "master";
986 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
987 power-domains = <&disp_pd>;
988 #iommu-cells = <0>;
989 };
990
991 bus_wcore: bus_wcore {
992 compatible = "samsung,exynos-bus";
993 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
994 clock-names = "bus";
995 operating-points-v2 = <&bus_wcore_opp_table>;
996 status = "disabled";
b04a62d3 997 };
b04a62d3 998
5d99cc59
KK		 999 bus_noc: bus_noc {
1000 compatible = "samsung,exynos-bus";
1001 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
1002 clock-names = "bus";
1003 operating-points-v2 = <&bus_noc_opp_table>;
1004 status = "disabled";
1005 };
b04a62d3 1006
5d99cc59
KK		 1007 bus_fsys_apb: bus_fsys_apb {
1008 compatible = "samsung,exynos-bus";
1009 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
1010 clock-names = "bus";
1011 operating-points-v2 = <&bus_fsys_apb_opp_table>;
1012 status = "disabled";
b04a62d3 1013 };
5d99cc59
KK		 1014
1015 bus_fsys: bus_fsys {
1016 compatible = "samsung,exynos-bus";
1017 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
1018 clock-names = "bus";
1019 operating-points-v2 = <&bus_fsys_apb_opp_table>;
1020 status = "disabled";
b04a62d3 1021 };
5d99cc59
KK		 1022
1023 bus_fsys2: bus_fsys2 {
1024 compatible = "samsung,exynos-bus";
1025 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1026 clock-names = "bus";
1027 operating-points-v2 = <&bus_fsys2_opp_table>;
1028 status = "disabled";
b04a62d3 1029 };
5d99cc59
KK		 1030
1031 bus_mfc: bus_mfc {
1032 compatible = "samsung,exynos-bus";
1033 clocks = <&clock CLK_DOUT_ACLK333>;
1034 clock-names = "bus";
1035 operating-points-v2 = <&bus_mfc_opp_table>;
1036 status = "disabled";
b04a62d3 1037 };
b04a62d3 1038
5d99cc59
KK		 1039 bus_gen: bus_gen {
1040 compatible = "samsung,exynos-bus";
1041 clocks = <&clock CLK_DOUT_ACLK266>;
1042 clock-names = "bus";
1043 operating-points-v2 = <&bus_gen_opp_table>;
1044 status = "disabled";
1045 };
b04a62d3 1046
5d99cc59
KK		 1047 bus_peri: bus_peri {
1048 compatible = "samsung,exynos-bus";
1049 clocks = <&clock CLK_DOUT_ACLK66>;
1050 clock-names = "bus";
1051 operating-points-v2 = <&bus_peri_opp_table>;
1052 status = "disabled";
b04a62d3 1053 };
5d99cc59
KK		 1054
1055 bus_g2d: bus_g2d {
1056 compatible = "samsung,exynos-bus";
1057 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1058 clock-names = "bus";
1059 operating-points-v2 = <&bus_g2d_opp_table>;
1060 status = "disabled";
b04a62d3 1061 };
b04a62d3 1062
5d99cc59
KK		 1063 bus_g2d_acp: bus_g2d_acp {
1064 compatible = "samsung,exynos-bus";
1065 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1066 clock-names = "bus";
1067 operating-points-v2 = <&bus_g2d_acp_opp_table>;
1068 status = "disabled";
1069 };
b04a62d3 1070
5d99cc59
KK		 1071 bus_jpeg: bus_jpeg {
1072 compatible = "samsung,exynos-bus";
1073 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1074 clock-names = "bus";
1075 operating-points-v2 = <&bus_jpeg_opp_table>;
1076 status = "disabled";
b04a62d3 1077 };
5d99cc59
KK		 1078
1079 bus_jpeg_apb: bus_jpeg_apb {
1080 compatible = "samsung,exynos-bus";
1081 clocks = <&clock CLK_DOUT_ACLK166>;
1082 clock-names = "bus";
1083 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1084 status = "disabled";
b04a62d3 1085 };
5d99cc59
KK		 1086
1087 bus_disp1_fimd: bus_disp1_fimd {
1088 compatible = "samsung,exynos-bus";
1089 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1090 clock-names = "bus";
1091 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1092 status = "disabled";
b04a62d3 1093 };
b04a62d3 1094
5d99cc59
KK		 1095 bus_disp1: bus_disp1 {
1096 compatible = "samsung,exynos-bus";
1097 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1098 clock-names = "bus";
1099 operating-points-v2 = <&bus_disp1_opp_table>;
1100 status = "disabled";
1101 };
b04a62d3 1102
5d99cc59
KK		 1103 bus_gscl_scaler: bus_gscl_scaler {
1104 compatible = "samsung,exynos-bus";
1105 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1106 clock-names = "bus";
1107 operating-points-v2 = <&bus_gscl_opp_table>;
1108 status = "disabled";
b04a62d3 1109 };
5d99cc59
KK		 1110
1111 bus_mscl: bus_mscl {
1112 compatible = "samsung,exynos-bus";
1113 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1114 clock-names = "bus";
1115 operating-points-v2 = <&bus_mscl_opp_table>;
1116 status = "disabled";
b04a62d3 1117 };
5d99cc59
KK		 1118
1119 bus_wcore_opp_table: opp_table2 {
1120 compatible = "operating-points-v2";
1121
1122 opp00 {
1123 opp-hz = /bits/ 64 <84000000>;
1124 opp-microvolt = <925000>;
1125 };
1126 opp01 {
1127 opp-hz = /bits/ 64 <111000000>;
1128 opp-microvolt = <950000>;
1129 };
1130 opp02 {
1131 opp-hz = /bits/ 64 <222000000>;
1132 opp-microvolt = <950000>;
1133 };
1134 opp03 {
1135 opp-hz = /bits/ 64 <333000000>;
1136 opp-microvolt = <950000>;
1137 };
1138 opp04 {
1139 opp-hz = /bits/ 64 <400000000>;
1140 opp-microvolt = <987500>;
1141 };
1142 };
1143
1144 bus_noc_opp_table: opp_table3 {
1145 compatible = "operating-points-v2";
1146
1147 opp00 {
1148 opp-hz = /bits/ 64 <67000000>;
1149 };
1150 opp01 {
1151 opp-hz = /bits/ 64 <75000000>;
1152 };
1153 opp02 {
1154 opp-hz = /bits/ 64 <86000000>;
1155 };
1156 opp03 {
1157 opp-hz = /bits/ 64 <100000000>;
1158 };
1159 };
1160
1161 bus_fsys_apb_opp_table: opp_table4 {
1162 compatible = "operating-points-v2";
1163 opp-shared;
1164
1165 opp00 {
1166 opp-hz = /bits/ 64 <100000000>;
1167 };
1168 opp01 {
1169 opp-hz = /bits/ 64 <200000000>;
1170 };
1171 };
1172
1173 bus_fsys2_opp_table: opp_table5 {
1174 compatible = "operating-points-v2";
1175
1176 opp00 {
1177 opp-hz = /bits/ 64 <75000000>;
1178 };
1179 opp01 {
1180 opp-hz = /bits/ 64 <100000000>;
1181 };
1182 opp02 {
1183 opp-hz = /bits/ 64 <150000000>;
1184 };
1185 };
1186
1187 bus_mfc_opp_table: opp_table6 {
1188 compatible = "operating-points-v2";
1189
1190 opp00 {
1191 opp-hz = /bits/ 64 <96000000>;
1192 };
1193 opp01 {
1194 opp-hz = /bits/ 64 <111000000>;
1195 };
1196 opp02 {
1197 opp-hz = /bits/ 64 <167000000>;
1198 };
1199 opp03 {
1200 opp-hz = /bits/ 64 <222000000>;
1201 };
1202 opp04 {
1203 opp-hz = /bits/ 64 <333000000>;
1204 };
1205 };
1206
1207 bus_gen_opp_table: opp_table7 {
1208 compatible = "operating-points-v2";
1209
1210 opp00 {
1211 opp-hz = /bits/ 64 <89000000>;
1212 };
1213 opp01 {
1214 opp-hz = /bits/ 64 <133000000>;
1215 };
1216 opp02 {
1217 opp-hz = /bits/ 64 <178000000>;
1218 };
1219 opp03 {
1220 opp-hz = /bits/ 64 <267000000>;
1221 };
1222 };
1223
1224 bus_peri_opp_table: opp_table8 {
1225 compatible = "operating-points-v2";
1226
1227 opp00 {
1228 opp-hz = /bits/ 64 <67000000>;
1229 };
1230 };
1231
1232 bus_g2d_opp_table: opp_table9 {
1233 compatible = "operating-points-v2";
1234
1235 opp00 {
1236 opp-hz = /bits/ 64 <84000000>;
1237 };
1238 opp01 {
1239 opp-hz = /bits/ 64 <167000000>;
1240 };
1241 opp02 {
1242 opp-hz = /bits/ 64 <222000000>;
1243 };
1244 opp03 {
1245 opp-hz = /bits/ 64 <300000000>;
1246 };
1247 opp04 {
1248 opp-hz = /bits/ 64 <333000000>;
1249 };
1250 };
1251
1252 bus_g2d_acp_opp_table: opp_table10 {
1253 compatible = "operating-points-v2";
1254
1255 opp00 {
1256 opp-hz = /bits/ 64 <67000000>;
1257 };
1258 opp01 {
1259 opp-hz = /bits/ 64 <133000000>;
1260 };
1261 opp02 {
1262 opp-hz = /bits/ 64 <178000000>;
1263 };
1264 opp03 {
1265 opp-hz = /bits/ 64 <267000000>;
1266 };
1267 };
1268
1269 bus_jpeg_opp_table: opp_table11 {
1270 compatible = "operating-points-v2";
1271
1272 opp00 {
1273 opp-hz = /bits/ 64 <75000000>;
1274 };
1275 opp01 {
1276 opp-hz = /bits/ 64 <150000000>;
1277 };
1278 opp02 {
1279 opp-hz = /bits/ 64 <200000000>;
1280 };
1281 opp03 {
1282 opp-hz = /bits/ 64 <300000000>;
1283 };
1284 };
1285
1286 bus_jpeg_apb_opp_table: opp_table12 {
1287 compatible = "operating-points-v2";
1288
1289 opp00 {
1290 opp-hz = /bits/ 64 <84000000>;
1291 };
1292 opp01 {
1293 opp-hz = /bits/ 64 <111000000>;
1294 };
1295 opp02 {
1296 opp-hz = /bits/ 64 <134000000>;
1297 };
1298 opp03 {
1299 opp-hz = /bits/ 64 <167000000>;
1300 };
1301 };
1302
1303 bus_disp1_fimd_opp_table: opp_table13 {
1304 compatible = "operating-points-v2";
1305
1306 opp00 {
1307 opp-hz = /bits/ 64 <120000000>;
1308 };
1309 opp01 {
1310 opp-hz = /bits/ 64 <200000000>;
1311 };
1312 };
1313
1314 bus_disp1_opp_table: opp_table14 {
1315 compatible = "operating-points-v2";
1316
1317 opp00 {
1318 opp-hz = /bits/ 64 <120000000>;
1319 };
1320 opp01 {
1321 opp-hz = /bits/ 64 <200000000>;
1322 };
1323 opp02 {
1324 opp-hz = /bits/ 64 <300000000>;
1325 };
1326 };
1327
1328 bus_gscl_opp_table: opp_table15 {
1329 compatible = "operating-points-v2";
1330
1331 opp00 {
1332 opp-hz = /bits/ 64 <150000000>;
1333 };
1334 opp01 {
1335 opp-hz = /bits/ 64 <200000000>;
1336 };
1337 opp02 {
1338 opp-hz = /bits/ 64 <300000000>;
1339 };
1340 };
1341
1342 bus_mscl_opp_table: opp_table16 {
1343 compatible = "operating-points-v2";
1344
1345 opp00 {
1346 opp-hz = /bits/ 64 <84000000>;
1347 };
1348 opp01 {
1349 opp-hz = /bits/ 64 <167000000>;
1350 };
1351 opp02 {
1352 opp-hz = /bits/ 64 <222000000>;
1353 };
1354 opp03 {
1355 opp-hz = /bits/ 64 <333000000>;
1356 };
1357 opp04 {
1358 opp-hz = /bits/ 64 <400000000>;
1359 };
b04a62d3
CC		 1360 };
1361 };
1362
5d99cc59
KK		 1363 thermal-zones {
1364 cpu0_thermal: cpu0-thermal {
1365 thermal-sensors = <&tmu_cpu0>;
1366 #include "exynos5420-trip-points.dtsi"
b04a62d3 1367 };
5d99cc59
KK		 1368 cpu1_thermal: cpu1-thermal {
1369 thermal-sensors = <&tmu_cpu1>;
1370 #include "exynos5420-trip-points.dtsi"
b04a62d3 1371 };
5d99cc59
KK		 1372 cpu2_thermal: cpu2-thermal {
1373 thermal-sensors = <&tmu_cpu2>;
1374 #include "exynos5420-trip-points.dtsi"
b04a62d3 1375 };
5d99cc59
KK		 1376 cpu3_thermal: cpu3-thermal {
1377 thermal-sensors = <&tmu_cpu3>;
1378 #include "exynos5420-trip-points.dtsi"
b04a62d3 1379 };
5d99cc59
KK		 1380 gpu_thermal: gpu-thermal {
1381 thermal-sensors = <&tmu_gpu>;
1382 #include "exynos5420-trip-points.dtsi"
b04a62d3
CC		 1383 };
1384 };
34dcedfb 1385};
3a3cf6c4
KK		 1386
1387&dp {
1388 clocks = <&clock CLK_DP1>;
1389 clock-names = "dp";
1390 phys = <&dp_phy>;
1391 phy-names = "dp";
1392 power-domains = <&disp_pd>;
1393};
1394
1395&fimd {
6dc62f12 1396 compatible = "samsung,exynos5420-fimd";
3a3cf6c4
KK		 1397 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1398 clock-names = "sclk_fimd", "fimd";
1399 power-domains = <&disp_pd>;
b7004516
MS		 1400 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1401 iommu-names = "m0", "m1";
3a3cf6c4
KK		 1402};
1403
5a124fe0
KK		 1404&i2c_0 {
1405 clocks = <&clock CLK_I2C0>;
1406 clock-names = "i2c";
1407 pinctrl-names = "default";
1408 pinctrl-0 = <&i2c0_bus>;
1409};
1410
1411&i2c_1 {
1412 clocks = <&clock CLK_I2C1>;
1413 clock-names = "i2c";
1414 pinctrl-names = "default";
1415 pinctrl-0 = <&i2c1_bus>;
1416};
1417
1418&i2c_2 {
1419 clocks = <&clock CLK_I2C2>;
1420 clock-names = "i2c";
1421 pinctrl-names = "default";
1422 pinctrl-0 = <&i2c2_bus>;
1423};
1424
1425&i2c_3 {
1426 clocks = <&clock CLK_I2C3>;
1427 clock-names = "i2c";
1428 pinctrl-names = "default";
1429 pinctrl-0 = <&i2c3_bus>;
1430};
1431
c9cf996d
KK		 1432&mct {
1433 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1434 clock-names = "fin_pll", "mct";
1435};
1436
5a124fe0
KK		 1437&pwm {
1438 clocks = <&clock CLK_PWM>;
1439 clock-names = "timers";
1440};
1441
3a3cf6c4
KK		 1442&rtc {
1443 clocks = <&clock CLK_RTC>;
1444 clock-names = "rtc";
1445 interrupt-parent = <&pmu_system_controller>;
1446 status = "disabled";
1447};
1448
1449&serial_0 {
1450 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1451 clock-names = "uart", "clk_uart_baud0";
1452};
1453
1454&serial_1 {
1455 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1456 clock-names = "uart", "clk_uart_baud0";
1457};
1458
1459&serial_2 {
1460 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1461 clock-names = "uart", "clk_uart_baud0";
1462};
1463
1464&serial_3 {
1465 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1466 clock-names = "uart", "clk_uart_baud0";
1467};
c07f8270 1468
cb089656
KK		 1469&usbdrd3_0 {
1470 clocks = <&clock CLK_USBD300>;
1471 clock-names = "usbdrd30";
1472};
1473
1474&usbdrd_phy0 {
1475 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1476 clock-names = "phy", "ref";
1477 samsung,pmu-syscon = <&pmu_system_controller>;
1478};
1479
1480&usbdrd3_1 {
1481 clocks = <&clock CLK_USBD301>;
1482 clock-names = "usbdrd30";
1483};
1484
1485&usbdrd_phy1 {
1486 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1487 clock-names = "phy", "ref";
1488 samsung,pmu-syscon = <&pmu_system_controller>;
1489};
1490
1491&usbhost1 {
1492 clocks = <&clock CLK_USBH20>;
1493 clock-names = "usbhost";
1494};
1495
1496&usbhost2 {
1497 clocks = <&clock CLK_USBH20>;
1498 clock-names = "usbhost";
1499};
1500
1501&usb2_phy {
1502 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1503 clock-names = "phy", "ref";
1504 samsung,sysreg-phandle = <&sysreg_system_controller>;
1505 samsung,pmureg-phandle = <&pmu_system_controller>;
1506};
1507
c07f8270 1508#include "exynos5420-pinctrl.dtsi"
Ubuntu Eoan Linux kernel mirror