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clk: exynos5420: Add IDs for clocks used in DISP1 power domain
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / exynos5420.dtsi
CommitLineData
34dcedfb
CK		 1/*
2 * SAMSUNG EXYNOS5420 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
1dd4e599 16#include <dt-bindings/clock/exynos5420.h>
34dcedfb 17#include "exynos5.dtsi"
0bd03f6f 18#include "exynos5420-pinctrl.dtsi"
35e82775 19
602408e3 20#include <dt-bindings/clock/exynos-audss-clk.h>
35e82775 21
34dcedfb 22/ {
8bdb31b4 23 compatible = "samsung,exynos5420", "samsung,exynos5";
34dcedfb 24
d81c6cbe 25 aliases {
0e2c5915
YK		 26 mshc0 = &mmc_0;
27 mshc1 = &mmc_1;
28 mshc2 = &mmc_2;
d81c6cbe
LKA		 29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
f49e347b
AB		 34 i2c0 = &i2c_0;
35 i2c1 = &i2c_1;
36 i2c2 = &i2c_2;
37 i2c3 = &i2c_3;
1a9110d6
SK		 38 i2c4 = &hsi2c_4;
39 i2c5 = &hsi2c_5;
40 i2c6 = &hsi2c_6;
41 i2c7 = &hsi2c_7;
42 i2c8 = &hsi2c_8;
43 i2c9 = &hsi2c_9;
44 i2c10 = &hsi2c_10;
01eb4636
LKA		 45 gsc0 = &gsc_0;
46 gsc1 = &gsc_1;
e84a2d91
LKA		 47 spi0 = &spi_0;
48 spi1 = &spi_1;
49 spi2 = &spi_2;
3cb7d1cd
VG		 50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
d81c6cbe
LKA		 52 };
53
34dcedfb
CK		 54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu0: cpu@0 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a15";
61 reg = <0x0>;
62 clock-frequency = <1800000000>;
5b56642b 63 cci-control-port = <&cci_control1>;
34dcedfb
CK		 64 };
65
66 cpu1: cpu@1 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a15";
69 reg = <0x1>;
70 clock-frequency = <1800000000>;
5b56642b 71 cci-control-port = <&cci_control1>;
34dcedfb
CK		 72 };
73
74 cpu2: cpu@2 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a15";
77 reg = <0x2>;
78 clock-frequency = <1800000000>;
5b56642b 79 cci-control-port = <&cci_control1>;
34dcedfb
CK		 80 };
81
82 cpu3: cpu@3 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <0x3>;
86 clock-frequency = <1800000000>;
5b56642b 87 cci-control-port = <&cci_control1>;
34dcedfb 88 };
1c0e0854
CK		 89
90 cpu4: cpu@100 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a7";
93 reg = <0x100>;
94 clock-frequency = <1000000000>;
5b56642b 95 cci-control-port = <&cci_control0>;
1c0e0854
CK		 96 };
97
98 cpu5: cpu@101 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a7";
101 reg = <0x101>;
102 clock-frequency = <1000000000>;
5b56642b 103 cci-control-port = <&cci_control0>;
1c0e0854
CK		 104 };
105
106 cpu6: cpu@102 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a7";
109 reg = <0x102>;
110 clock-frequency = <1000000000>;
5b56642b 111 cci-control-port = <&cci_control0>;
1c0e0854
CK		 112 };
113
114 cpu7: cpu@103 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a7";
117 reg = <0x103>;
118 clock-frequency = <1000000000>;
5b56642b
AB		 119 cci-control-port = <&cci_control0>;
120 };
121 };
122
123 cci@10d20000 {
124 compatible = "arm,cci-400";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>;
129
130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace";
133 reg = <0x4000 0x1000>;
134 };
135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace";
138 reg = <0x5000 0x1000>;
1c0e0854 139 };
34dcedfb
CK		 140 };
141
b3205dea
SK		 142 sysram@02020000 {
143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>;
146 #size-cells = <1>;
147 ranges = <0 0x02020000 0x54000>;
148
149 smp-sysram@0 {
150 compatible = "samsung,exynos4210-sysram";
151 reg = <0x0 0x1000>;
152 };
153
154 smp-sysram@53000 {
155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>;
1c0e0854 157 };
34dcedfb
CK		 158 };
159
92040bd6 160 clock: clock-controller@10010000 {
34dcedfb
CK		 161 compatible = "samsung,exynos5420-clock";
162 reg = <0x10010000 0x30000>;
163 #clock-cells = <1>;
164 };
165
35e82775
AB		 166 clock_audss: audss-clock-controller@3810000 {
167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>;
169 #clock-cells = <1>;
be0b420a 170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
1dd4e599 171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
59d711e9 172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
35e82775
AB		 173 };
174
8e371a91 175 mfc: codec@11000000 {
f09d062f
AK		 176 compatible = "samsung,mfc-v7";
177 reg = <0x11000000 0x10000>;
178 interrupts = <0 96 0>;
1dd4e599 179 clocks = <&clock CLK_MFC>;
f09d062f 180 clock-names = "mfc";
0da65870 181 power-domains = <&mfc_pd>;
f09d062f
AK		 182 };
183
0e2c5915
YK		 184 mmc_0: mmc@12200000 {
185 compatible = "samsung,exynos5420-dw-mshc-smu";
186 interrupts = <0 75 0>;
187 #address-cells = <1>;
188 #size-cells = <0>;
189 reg = <0x12200000 0x2000>;
1dd4e599 190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
0e2c5915
YK		 191 clock-names = "biu", "ciu";
192 fifo-depth = <0x40>;
193 status = "disabled";
194 };
195
196 mmc_1: mmc@12210000 {
197 compatible = "samsung,exynos5420-dw-mshc-smu";
198 interrupts = <0 76 0>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201 reg = <0x12210000 0x2000>;
1dd4e599 202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
0e2c5915
YK		 203 clock-names = "biu", "ciu";
204 fifo-depth = <0x40>;
205 status = "disabled";
206 };
207
208 mmc_2: mmc@12220000 {
209 compatible = "samsung,exynos5420-dw-mshc";
210 interrupts = <0 77 0>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 reg = <0x12220000 0x1000>;
1dd4e599 214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
0e2c5915
YK		 215 clock-names = "biu", "ciu";
216 fifo-depth = <0x40>;
217 status = "disabled";
218 };
219
8e371a91 220 mct: mct@101C0000 {
34dcedfb
CK		 221 compatible = "samsung,exynos4210-mct";
222 reg = <0x101C0000 0x800>;
223 interrupt-controller;
224 #interrups-cells = <1>;
225 interrupt-parent = <&mct_map>;
6c16dedf
CK		 226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
227 <8>, <9>, <10>, <11>;
1dd4e599 228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
34dcedfb
CK		 229 clock-names = "fin_pll", "mct";
230
231 mct_map: mct-map {
232 #interrupt-cells = <1>;
233 #address-cells = <0>;
234 #size-cells = <0>;
235 interrupt-map = <0 &combiner 23 3>,
236 <1 &combiner 23 4>,
237 <2 &combiner 25 2>,
238 <3 &combiner 25 3>,
239 <4 &gic 0 120 0>,
240 <5 &gic 0 121 0>,
241 <6 &gic 0 122 0>,
6c16dedf
CK		 242 <7 &gic 0 123 0>,
243 <8 &gic 0 128 0>,
244 <9 &gic 0 129 0>,
245 <10 &gic 0 130 0>,
246 <11 &gic 0 131 0>;
34dcedfb
CK		 247 };
248 };
249
dcfca2cc
YSB		 250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>;
0da65870 253 #power-domain-cells = <0>;
dcfca2cc
YSB		 254 };
255
256 isp_pd: power-domain@10044020 {
257 compatible = "samsung,exynos4210-pd";
258 reg = <0x10044020 0x20>;
0da65870 259 #power-domain-cells = <0>;
dcfca2cc
YSB		 260 };
261
262 mfc_pd: power-domain@10044060 {
263 compatible = "samsung,exynos4210-pd";
264 reg = <0x10044060 0x20>;
cacaeb82
AK		 265 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
266 <&clock CLK_MOUT_USER_ACLK333>;
267 clock-names = "oscclk", "pclk0", "clk0";
0da65870 268 #power-domain-cells = <0>;
dcfca2cc
YSB		 269 };
270
dcfca2cc
YSB		 271 msc_pd: power-domain@10044120 {
272 compatible = "samsung,exynos4210-pd";
273 reg = <0x10044120 0x20>;
0da65870 274 #power-domain-cells = <0>;
dcfca2cc
YSB		 275 };
276
d81c6cbe
LKA		 277 pinctrl_0: pinctrl@13400000 {
278 compatible = "samsung,exynos5420-pinctrl";
279 reg = <0x13400000 0x1000>;
280 interrupts = <0 45 0>;
281
282 wakeup-interrupt-controller {
283 compatible = "samsung,exynos4210-wakeup-eint";
284 interrupt-parent = <&gic>;
285 interrupts = <0 32 0>;
286 };
287 };
288
289 pinctrl_1: pinctrl@13410000 {
290 compatible = "samsung,exynos5420-pinctrl";
291 reg = <0x13410000 0x1000>;
292 interrupts = <0 78 0>;
293 };
294
295 pinctrl_2: pinctrl@14000000 {
296 compatible = "samsung,exynos5420-pinctrl";
297 reg = <0x14000000 0x1000>;
298 interrupts = <0 46 0>;
299 };
300
301 pinctrl_3: pinctrl@14010000 {
302 compatible = "samsung,exynos5420-pinctrl";
303 reg = <0x14010000 0x1000>;
304 interrupts = <0 50 0>;
305 };
306
307 pinctrl_4: pinctrl@03860000 {
308 compatible = "samsung,exynos5420-pinctrl";
309 reg = <0x03860000 0x1000>;
310 interrupts = <0 47 0>;
311 };
312
8e371a91 313 rtc: rtc@101E0000 {
1dd4e599 314 clocks = <&clock CLK_RTC>;
a81951d9 315 clock-names = "rtc";
451c402b 316 status = "disabled";
a81951d9
VS		 317 };
318
e3188533
PV		 319 amba {
320 #address-cells = <1>;
321 #size-cells = <1>;
322 compatible = "arm,amba-bus";
323 interrupt-parent = <&gic>;
324 ranges;
325
6dd2f1c4
SK		 326 adma: adma@03880000 {
327 compatible = "arm,pl330", "arm,primecell";
328 reg = <0x03880000 0x1000>;
329 interrupts = <0 110 0>;
330 clocks = <&clock_audss EXYNOS_ADMA>;
331 clock-names = "apb_pclk";
332 #dma-cells = <1>;
333 #dma-channels = <6>;
334 #dma-requests = <16>;
335 };
336
e3188533
PV		 337 pdma0: pdma@121A0000 {
338 compatible = "arm,pl330", "arm,primecell";
339 reg = <0x121A0000 0x1000>;
340 interrupts = <0 34 0>;
1dd4e599 341 clocks = <&clock CLK_PDMA0>;
e3188533
PV		 342 clock-names = "apb_pclk";
343 #dma-cells = <1>;
344 #dma-channels = <8>;
345 #dma-requests = <32>;
346 };
347
348 pdma1: pdma@121B0000 {
349 compatible = "arm,pl330", "arm,primecell";
350 reg = <0x121B0000 0x1000>;
351 interrupts = <0 35 0>;
1dd4e599 352 clocks = <&clock CLK_PDMA1>;
e3188533
PV		 353 clock-names = "apb_pclk";
354 #dma-cells = <1>;
355 #dma-channels = <8>;
356 #dma-requests = <32>;
357 };
358
359 mdma0: mdma@10800000 {
360 compatible = "arm,pl330", "arm,primecell";
361 reg = <0x10800000 0x1000>;
362 interrupts = <0 33 0>;
1dd4e599 363 clocks = <&clock CLK_MDMA0>;
e3188533
PV		 364 clock-names = "apb_pclk";
365 #dma-cells = <1>;
366 #dma-channels = <8>;
367 #dma-requests = <1>;
368 };
369
370 mdma1: mdma@11C10000 {
371 compatible = "arm,pl330", "arm,primecell";
372 reg = <0x11C10000 0x1000>;
373 interrupts = <0 124 0>;
1dd4e599 374 clocks = <&clock CLK_MDMA1>;
e3188533
PV		 375 clock-names = "apb_pclk";
376 #dma-cells = <1>;
377 #dma-channels = <8>;
378 #dma-requests = <1>;
e6015c1f
SJ		 379 /*
380 * MDMA1 can support both secure and non-secure
381 * AXI transactions. When this is enabled in the kernel
382 * for boards that run in secure mode, we are getting
383 * imprecise external aborts causing the kernel to oops.
384 */
385 status = "disabled";
e3188533
PV		 386 };
387 };
388
98bcb547
SK		 389 i2s0: i2s@03830000 {
390 compatible = "samsung,exynos5420-i2s";
391 reg = <0x03830000 0x100>;
392 dmas = <&adma 0
393 &adma 2
394 &adma 1>;
395 dma-names = "tx", "rx", "tx-sec";
396 clocks = <&clock_audss EXYNOS_I2S_BUS>,
397 <&clock_audss EXYNOS_I2S_BUS>,
398 <&clock_audss EXYNOS_SCLK_I2S>;
399 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
400 samsung,idma-addr = <0x03000000>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&i2s0_bus>;
403 status = "disabled";
404 };
405
406 i2s1: i2s@12D60000 {
407 compatible = "samsung,exynos5420-i2s";
408 reg = <0x12D60000 0x100>;
409 dmas = <&pdma1 12
410 &pdma1 11>;
411 dma-names = "tx", "rx";
1dd4e599 412 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
98bcb547
SK		 413 clock-names = "iis", "i2s_opclk0";
414 pinctrl-names = "default";
415 pinctrl-0 = <&i2s1_bus>;
416 status = "disabled";
417 };
418
419 i2s2: i2s@12D70000 {
420 compatible = "samsung,exynos5420-i2s";
421 reg = <0x12D70000 0x100>;
422 dmas = <&pdma0 12
423 &pdma0 11>;
424 dma-names = "tx", "rx";
1dd4e599 425 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
98bcb547
SK		 426 clock-names = "iis", "i2s_opclk0";
427 pinctrl-names = "default";
428 pinctrl-0 = <&i2s2_bus>;
429 status = "disabled";
430 };
431
e84a2d91
LKA		 432 spi_0: spi@12d20000 {
433 compatible = "samsung,exynos4210-spi";
434 reg = <0x12d20000 0x100>;
e3b6c271 435 interrupts = <0 68 0>;
e84a2d91
LKA		 436 dmas = <&pdma0 5
437 &pdma0 4>;
438 dma-names = "tx", "rx";
439 #address-cells = <1>;
440 #size-cells = <0>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&spi0_bus>;
1dd4e599 443 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
e84a2d91
LKA		 444 clock-names = "spi", "spi_busclk0";
445 status = "disabled";
446 };
447
448 spi_1: spi@12d30000 {
449 compatible = "samsung,exynos4210-spi";
450 reg = <0x12d30000 0x100>;
e3b6c271 451 interrupts = <0 69 0>;
e84a2d91
LKA		 452 dmas = <&pdma1 5
453 &pdma1 4>;
454 dma-names = "tx", "rx";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&spi1_bus>;
1dd4e599 459 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
e84a2d91
LKA		 460 clock-names = "spi", "spi_busclk0";
461 status = "disabled";
462 };
463
464 spi_2: spi@12d40000 {
465 compatible = "samsung,exynos4210-spi";
466 reg = <0x12d40000 0x100>;
e3b6c271 467 interrupts = <0 70 0>;
e84a2d91
LKA		 468 dmas = <&pdma0 7
469 &pdma0 6>;
470 dma-names = "tx", "rx";
471 #address-cells = <1>;
472 #size-cells = <0>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&spi2_bus>;
1dd4e599 475 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
e84a2d91
LKA		 476 clock-names = "spi", "spi_busclk0";
477 status = "disabled";
478 };
479
8e371a91 480 uart_0: serial@12C00000 {
1dd4e599 481 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
34dcedfb
CK		 482 clock-names = "uart", "clk_uart_baud0";
483 };
484
8e371a91 485 uart_1: serial@12C10000 {
1dd4e599 486 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
34dcedfb
CK		 487 clock-names = "uart", "clk_uart_baud0";
488 };
489
8e371a91 490 uart_2: serial@12C20000 {
1dd4e599 491 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
34dcedfb
CK		 492 clock-names = "uart", "clk_uart_baud0";
493 };
494
8e371a91 495 uart_3: serial@12C30000 {
1dd4e599 496 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
34dcedfb
CK		 497 clock-names = "uart", "clk_uart_baud0";
498 };
ee3381d4 499
022cf308
LKA		 500 pwm: pwm@12dd0000 {
501 compatible = "samsung,exynos4210-pwm";
502 reg = <0x12dd0000 0x100>;
503 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
504 #pwm-cells = <3>;
1dd4e599 505 clocks = <&clock CLK_PWM>;
022cf308
LKA		 506 clock-names = "timers";
507 };
508
1339d33a
VS		 509 dp_phy: video-phy@10040728 {
510 compatible = "samsung,exynos5250-dp-video-phy";
511 reg = <0x10040728 4>;
512 #phy-cells = <0>;
513 };
514
8e371a91 515 dp: dp-controller@145B0000 {
1dd4e599 516 clocks = <&clock CLK_DP1>;
1339d33a
VS		 517 clock-names = "dp";
518 phys = <&dp_phy>;
519 phy-names = "dp";
520 };
521
dc9ec8cd
YC		 522 mipi_phy: video-phy@10040714 {
523 compatible = "samsung,s5pv210-mipi-video-phy";
524 reg = <0x10040714 12>;
525 #phy-cells = <1>;
526 };
527
5a8da524
YC		 528 dsi@14500000 {
529 compatible = "samsung,exynos5410-mipi-dsi";
530 reg = <0x14500000 0x10000>;
531 interrupts = <0 82 0>;
5a8da524
YC		 532 phys = <&mipi_phy 1>;
533 phy-names = "dsim";
534 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
535 clock-names = "bus_clk", "pll_clk";
536 #address-cells = <1>;
537 #size-cells = <0>;
538 status = "disabled";
539 };
540
8e371a91 541 fimd: fimd@14400000 {
1dd4e599 542 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
ee3381d4
VS		 543 clock-names = "sclk_fimd", "fimd";
544 };
f408f9db
NKC		 545
546 adc: adc@12D10000 {
547 compatible = "samsung,exynos-adc-v2";
db9bf4d6 548 reg = <0x12D10000 0x100>;
f408f9db 549 interrupts = <0 106 0>;
1dd4e599 550 clocks = <&clock CLK_TSADC>;
f408f9db
NKC		 551 clock-names = "adc";
552 #io-channel-cells = <1>;
553 io-channel-ranges;
db9bf4d6 554 samsung,syscon-phandle = <&pmu_system_controller>;
f408f9db
NKC		 555 status = "disabled";
556 };
f49e347b
AB		 557
558 i2c_0: i2c@12C60000 {
559 compatible = "samsung,s3c2440-i2c";
560 reg = <0x12C60000 0x100>;
561 interrupts = <0 56 0>;
562 #address-cells = <1>;
563 #size-cells = <0>;
1dd4e599 564 clocks = <&clock CLK_I2C0>;
f49e347b
AB		 565 clock-names = "i2c";
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c0_bus>;
1888eb75 568 samsung,sysreg-phandle = <&sysreg_system_controller>;
f49e347b
AB		 569 status = "disabled";
570 };
571
572 i2c_1: i2c@12C70000 {
573 compatible = "samsung,s3c2440-i2c";
574 reg = <0x12C70000 0x100>;
575 interrupts = <0 57 0>;
576 #address-cells = <1>;
577 #size-cells = <0>;
1dd4e599 578 clocks = <&clock CLK_I2C1>;
f49e347b
AB		 579 clock-names = "i2c";
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2c1_bus>;
1888eb75 582 samsung,sysreg-phandle = <&sysreg_system_controller>;
f49e347b
AB		 583 status = "disabled";
584 };
585
586 i2c_2: i2c@12C80000 {
587 compatible = "samsung,s3c2440-i2c";
588 reg = <0x12C80000 0x100>;
589 interrupts = <0 58 0>;
590 #address-cells = <1>;
591 #size-cells = <0>;
1dd4e599 592 clocks = <&clock CLK_I2C2>;
f49e347b
AB		 593 clock-names = "i2c";
594 pinctrl-names = "default";
595 pinctrl-0 = <&i2c2_bus>;
1888eb75 596 samsung,sysreg-phandle = <&sysreg_system_controller>;
f49e347b
AB		 597 status = "disabled";
598 };
599
600 i2c_3: i2c@12C90000 {
601 compatible = "samsung,s3c2440-i2c";
602 reg = <0x12C90000 0x100>;
603 interrupts = <0 59 0>;
604 #address-cells = <1>;
605 #size-cells = <0>;
1dd4e599 606 clocks = <&clock CLK_I2C3>;
f49e347b
AB		 607 clock-names = "i2c";
608 pinctrl-names = "default";
609 pinctrl-0 = <&i2c3_bus>;
1888eb75 610 samsung,sysreg-phandle = <&sysreg_system_controller>;
f49e347b
AB		 611 status = "disabled";
612 };
b0e505ce 613
1a9110d6
SK		 614 hsi2c_4: i2c@12CA0000 {
615 compatible = "samsung,exynos5-hsi2c";
616 reg = <0x12CA0000 0x1000>;
617 interrupts = <0 60 0>;
618 #address-cells = <1>;
619 #size-cells = <0>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&i2c4_hs_bus>;
faec151b 622 clocks = <&clock CLK_USI0>;
1a9110d6
SK		 623 clock-names = "hsi2c";
624 status = "disabled";
625 };
626
627 hsi2c_5: i2c@12CB0000 {
628 compatible = "samsung,exynos5-hsi2c";
629 reg = <0x12CB0000 0x1000>;
630 interrupts = <0 61 0>;
631 #address-cells = <1>;
632 #size-cells = <0>;
633 pinctrl-names = "default";
634 pinctrl-0 = <&i2c5_hs_bus>;
faec151b 635 clocks = <&clock CLK_USI1>;
1a9110d6
SK		 636 clock-names = "hsi2c";
637 status = "disabled";
638 };
639
640 hsi2c_6: i2c@12CC0000 {
641 compatible = "samsung,exynos5-hsi2c";
642 reg = <0x12CC0000 0x1000>;
643 interrupts = <0 62 0>;
644 #address-cells = <1>;
645 #size-cells = <0>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&i2c6_hs_bus>;
faec151b 648 clocks = <&clock CLK_USI2>;
1a9110d6
SK		 649 clock-names = "hsi2c";
650 status = "disabled";
651 };
652
653 hsi2c_7: i2c@12CD0000 {
654 compatible = "samsung,exynos5-hsi2c";
655 reg = <0x12CD0000 0x1000>;
656 interrupts = <0 63 0>;
657 #address-cells = <1>;
658 #size-cells = <0>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&i2c7_hs_bus>;
faec151b 661 clocks = <&clock CLK_USI3>;
1a9110d6
SK		 662 clock-names = "hsi2c";
663 status = "disabled";
664 };
665
666 hsi2c_8: i2c@12E00000 {
667 compatible = "samsung,exynos5-hsi2c";
668 reg = <0x12E00000 0x1000>;
669 interrupts = <0 87 0>;
670 #address-cells = <1>;
671 #size-cells = <0>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&i2c8_hs_bus>;
faec151b 674 clocks = <&clock CLK_USI4>;
1a9110d6
SK		 675 clock-names = "hsi2c";
676 status = "disabled";
677 };
678
679 hsi2c_9: i2c@12E10000 {
680 compatible = "samsung,exynos5-hsi2c";
681 reg = <0x12E10000 0x1000>;
682 interrupts = <0 88 0>;
683 #address-cells = <1>;
684 #size-cells = <0>;
685 pinctrl-names = "default";
686 pinctrl-0 = <&i2c9_hs_bus>;
faec151b 687 clocks = <&clock CLK_USI5>;
1a9110d6
SK		 688 clock-names = "hsi2c";
689 status = "disabled";
690 };
691
692 hsi2c_10: i2c@12E20000 {
693 compatible = "samsung,exynos5-hsi2c";
694 reg = <0x12E20000 0x1000>;
695 interrupts = <0 203 0>;
696 #address-cells = <1>;
697 #size-cells = <0>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&i2c10_hs_bus>;
faec151b 700 clocks = <&clock CLK_USI6>;
1a9110d6
SK		 701 clock-names = "hsi2c";
702 status = "disabled";
703 };
704
8e371a91 705 hdmi: hdmi@14530000 {
2963c554 706 compatible = "samsung,exynos5420-hdmi";
b0e505ce
RS		 707 reg = <0x14530000 0x70000>;
708 interrupts = <0 95 0>;
1dd4e599
AH		 709 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
710 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
711 <&clock CLK_MOUT_HDMI>;
b0e505ce
RS		 712 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
713 "sclk_hdmiphy", "mout_hdmi";
6ac189fc 714 phy = <&hdmiphy>;
3a7e5dd5 715 samsung,syscon-phandle = <&pmu_system_controller>;
b0e505ce
RS		 716 status = "disabled";
717 };
718
6ac189fc
RS		 719 hdmiphy: hdmiphy@145D0000 {
720 reg = <0x145D0000 0x20>;
721 };
722
8e371a91 723 mixer: mixer@14450000 {
b0e505ce
RS		 724 compatible = "samsung,exynos5420-mixer";
725 reg = <0x14450000 0x10000>;
726 interrupts = <0 94 0>;
1dd4e599 727 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
b0e505ce
RS		 728 clock-names = "mixer", "sclk_hdmi";
729 };
01eb4636
LKA		 730
731 gsc_0: video-scaler@13e00000 {
732 compatible = "samsung,exynos5-gsc";
733 reg = <0x13e00000 0x1000>;
734 interrupts = <0 85 0>;
1dd4e599 735 clocks = <&clock CLK_GSCL0>;
01eb4636 736 clock-names = "gscl";
0da65870 737 power-domains = <&gsc_pd>;
01eb4636
LKA		 738 };
739
740 gsc_1: video-scaler@13e10000 {
741 compatible = "samsung,exynos5-gsc";
742 reg = <0x13e10000 0x1000>;
743 interrupts = <0 86 0>;
1dd4e599 744 clocks = <&clock CLK_GSCL1>;
01eb4636 745 clock-names = "gscl";
0da65870 746 power-domains = <&gsc_pd>;
01eb4636 747 };
655de648 748
c680036a
LKA		 749 pmu_system_controller: system-controller@10040000 {
750 compatible = "samsung,exynos5420-pmu", "syscon";
751 reg = <0x10040000 0x5000>;
d19bb397
TF		 752 clock-names = "clkout16";
753 clocks = <&clock CLK_FIN_PLL>;
754 #clock-cells = <1>;
c680036a
LKA		 755 };
756
dfbbdbf4
VG		 757 sysreg_system_controller: syscon@10050000 {
758 compatible = "samsung,exynos5-sysreg", "syscon";
759 reg = <0x10050000 0x5000>;
760 };
761
655de648
NKC		 762 tmu_cpu0: tmu@10060000 {
763 compatible = "samsung,exynos5420-tmu";
764 reg = <0x10060000 0x100>;
765 interrupts = <0 65 0>;
1dd4e599 766 clocks = <&clock CLK_TMU>;
655de648
NKC		 767 clock-names = "tmu_apbif";
768 };
769
770 tmu_cpu1: tmu@10064000 {
771 compatible = "samsung,exynos5420-tmu";
772 reg = <0x10064000 0x100>;
773 interrupts = <0 183 0>;
1dd4e599 774 clocks = <&clock CLK_TMU>;
655de648
NKC		 775 clock-names = "tmu_apbif";
776 };
777
778 tmu_cpu2: tmu@10068000 {
779 compatible = "samsung,exynos5420-tmu-ext-triminfo";
780 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
781 interrupts = <0 184 0>;
1dd4e599 782 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
655de648
NKC		 783 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
784 };
785
786 tmu_cpu3: tmu@1006c000 {
787 compatible = "samsung,exynos5420-tmu-ext-triminfo";
788 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
789 interrupts = <0 185 0>;
1dd4e599 790 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
655de648
NKC		 791 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
792 };
793
794 tmu_gpu: tmu@100a0000 {
795 compatible = "samsung,exynos5420-tmu-ext-triminfo";
796 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
797 interrupts = <0 215 0>;
1dd4e599 798 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
655de648
NKC		 799 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
800 };
1d287620 801
8e371a91 802 watchdog: watchdog@101D0000 {
1d287620
LKA		 803 compatible = "samsung,exynos5420-wdt";
804 reg = <0x101D0000 0x100>;
805 interrupts = <0 42 0>;
1dd4e599 806 clocks = <&clock CLK_WDT>;
1d287620
LKA		 807 clock-names = "watchdog";
808 samsung,syscon-phandle = <&pmu_system_controller>;
809 };
183af252 810
8e371a91 811 sss: sss@10830000 {
183af252
NKC		 812 compatible = "samsung,exynos4210-secss";
813 reg = <0x10830000 0x10000>;
814 interrupts = <0 112 0>;
ab3a158c 815 clocks = <&clock CLK_SSS>;
183af252 816 clock-names = "secss";
183af252 817 };
3cb7d1cd 818
f070267b
VG		 819 usbdrd3_0: usb@12000000 {
820 compatible = "samsung,exynos5250-dwusb3";
821 clocks = <&clock CLK_USBD300>;
822 clock-names = "usbdrd30";
823 #address-cells = <1>;
824 #size-cells = <1>;
825 ranges;
826
e1c69efc 827 usbdrd_dwc3_0: dwc3 {
f070267b
VG		 828 compatible = "snps,dwc3";
829 reg = <0x12000000 0x10000>;
830 interrupts = <0 72 0>;
831 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
832 phy-names = "usb2-phy", "usb3-phy";
833 };
834 };
835
3cb7d1cd
VG		 836 usbdrd_phy0: phy@12100000 {
837 compatible = "samsung,exynos5420-usbdrd-phy";
838 reg = <0x12100000 0x100>;
839 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
840 clock-names = "phy", "ref";
841 samsung,pmu-syscon = <&pmu_system_controller>;
842 #phy-cells = <1>;
843 };
844
f070267b
VG		 845 usbdrd3_1: usb@12400000 {
846 compatible = "samsung,exynos5250-dwusb3";
847 clocks = <&clock CLK_USBD301>;
848 clock-names = "usbdrd30";
849 #address-cells = <1>;
850 #size-cells = <1>;
851 ranges;
852
e1c69efc 853 usbdrd_dwc3_1: dwc3 {
f070267b
VG		 854 compatible = "snps,dwc3";
855 reg = <0x12400000 0x10000>;
856 interrupts = <0 73 0>;
857 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
858 phy-names = "usb2-phy", "usb3-phy";
859 };
860 };
861
3cb7d1cd
VG		 862 usbdrd_phy1: phy@12500000 {
863 compatible = "samsung,exynos5420-usbdrd-phy";
864 reg = <0x12500000 0x100>;
865 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
866 clock-names = "phy", "ref";
867 samsung,pmu-syscon = <&pmu_system_controller>;
868 #phy-cells = <1>;
869 };
8d53526f 870
6674fd92
VG		 871 usbhost2: usb@12110000 {
872 compatible = "samsung,exynos4210-ehci";
873 reg = <0x12110000 0x100>;
874 interrupts = <0 71 0>;
875
876 clocks = <&clock CLK_USBH20>;
877 clock-names = "usbhost";
878 #address-cells = <1>;
879 #size-cells = <0>;
880 port@0 {
881 reg = <0>;
882 phys = <&usb2_phy 1>;
883 };
884 };
885
886 usbhost1: usb@12120000 {
887 compatible = "samsung,exynos4210-ohci";
888 reg = <0x12120000 0x100>;
889 interrupts = <0 71 0>;
890
891 clocks = <&clock CLK_USBH20>;
892 clock-names = "usbhost";
893 #address-cells = <1>;
894 #size-cells = <0>;
895 port@0 {
896 reg = <0>;
897 phys = <&usb2_phy 1>;
898 };
899 };
900
8d53526f
VG		 901 usb2_phy: phy@12130000 {
902 compatible = "samsung,exynos5250-usb2-phy";
903 reg = <0x12130000 0x100>;
904 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
905 clock-names = "phy", "ref";
906 #phy-cells = <1>;
907 samsung,sysreg-phandle = <&sysreg_system_controller>;
908 samsung,pmureg-phandle = <&pmu_system_controller>;
909 };
34dcedfb 910};
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