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34dcedfb CK |
1 | /* |
2 | * SAMSUNG EXYNOS5420 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. | |
8 | * EXYNOS5420 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
1dd4e599 | 16 | #include <dt-bindings/clock/exynos5420.h> |
34dcedfb | 17 | #include "exynos5.dtsi" |
0bd03f6f | 18 | #include "exynos5420-pinctrl.dtsi" |
35e82775 | 19 | |
602408e3 | 20 | #include <dt-bindings/clock/exynos-audss-clk.h> |
35e82775 | 21 | |
34dcedfb | 22 | / { |
8bdb31b4 | 23 | compatible = "samsung,exynos5420", "samsung,exynos5"; |
34dcedfb | 24 | |
d81c6cbe | 25 | aliases { |
0e2c5915 YK |
26 | mshc0 = &mmc_0; |
27 | mshc1 = &mmc_1; | |
28 | mshc2 = &mmc_2; | |
d81c6cbe LKA |
29 | pinctrl0 = &pinctrl_0; |
30 | pinctrl1 = &pinctrl_1; | |
31 | pinctrl2 = &pinctrl_2; | |
32 | pinctrl3 = &pinctrl_3; | |
33 | pinctrl4 = &pinctrl_4; | |
f49e347b AB |
34 | i2c0 = &i2c_0; |
35 | i2c1 = &i2c_1; | |
36 | i2c2 = &i2c_2; | |
37 | i2c3 = &i2c_3; | |
1a9110d6 SK |
38 | i2c4 = &hsi2c_4; |
39 | i2c5 = &hsi2c_5; | |
40 | i2c6 = &hsi2c_6; | |
41 | i2c7 = &hsi2c_7; | |
42 | i2c8 = &hsi2c_8; | |
43 | i2c9 = &hsi2c_9; | |
44 | i2c10 = &hsi2c_10; | |
01eb4636 LKA |
45 | gsc0 = &gsc_0; |
46 | gsc1 = &gsc_1; | |
e84a2d91 LKA |
47 | spi0 = &spi_0; |
48 | spi1 = &spi_1; | |
49 | spi2 = &spi_2; | |
3cb7d1cd VG |
50 | usbdrdphy0 = &usbdrd_phy0; |
51 | usbdrdphy1 = &usbdrd_phy1; | |
d81c6cbe LKA |
52 | }; |
53 | ||
34dcedfb CK |
54 | cpus { |
55 | #address-cells = <1>; | |
56 | #size-cells = <0>; | |
57 | ||
58 | cpu0: cpu@0 { | |
59 | device_type = "cpu"; | |
60 | compatible = "arm,cortex-a15"; | |
61 | reg = <0x0>; | |
62 | clock-frequency = <1800000000>; | |
63 | }; | |
64 | ||
65 | cpu1: cpu@1 { | |
66 | device_type = "cpu"; | |
67 | compatible = "arm,cortex-a15"; | |
68 | reg = <0x1>; | |
69 | clock-frequency = <1800000000>; | |
70 | }; | |
71 | ||
72 | cpu2: cpu@2 { | |
73 | device_type = "cpu"; | |
74 | compatible = "arm,cortex-a15"; | |
75 | reg = <0x2>; | |
76 | clock-frequency = <1800000000>; | |
77 | }; | |
78 | ||
79 | cpu3: cpu@3 { | |
80 | device_type = "cpu"; | |
81 | compatible = "arm,cortex-a15"; | |
82 | reg = <0x3>; | |
83 | clock-frequency = <1800000000>; | |
84 | }; | |
1c0e0854 CK |
85 | |
86 | cpu4: cpu@100 { | |
87 | device_type = "cpu"; | |
88 | compatible = "arm,cortex-a7"; | |
89 | reg = <0x100>; | |
90 | clock-frequency = <1000000000>; | |
91 | }; | |
92 | ||
93 | cpu5: cpu@101 { | |
94 | device_type = "cpu"; | |
95 | compatible = "arm,cortex-a7"; | |
96 | reg = <0x101>; | |
97 | clock-frequency = <1000000000>; | |
98 | }; | |
99 | ||
100 | cpu6: cpu@102 { | |
101 | device_type = "cpu"; | |
102 | compatible = "arm,cortex-a7"; | |
103 | reg = <0x102>; | |
104 | clock-frequency = <1000000000>; | |
105 | }; | |
106 | ||
107 | cpu7: cpu@103 { | |
108 | device_type = "cpu"; | |
109 | compatible = "arm,cortex-a7"; | |
110 | reg = <0x103>; | |
111 | clock-frequency = <1000000000>; | |
112 | }; | |
34dcedfb CK |
113 | }; |
114 | ||
b3205dea SK |
115 | sysram@02020000 { |
116 | compatible = "mmio-sram"; | |
117 | reg = <0x02020000 0x54000>; | |
118 | #address-cells = <1>; | |
119 | #size-cells = <1>; | |
120 | ranges = <0 0x02020000 0x54000>; | |
121 | ||
122 | smp-sysram@0 { | |
123 | compatible = "samsung,exynos4210-sysram"; | |
124 | reg = <0x0 0x1000>; | |
125 | }; | |
126 | ||
127 | smp-sysram@53000 { | |
128 | compatible = "samsung,exynos4210-sysram-ns"; | |
129 | reg = <0x53000 0x1000>; | |
130 | }; | |
131 | }; | |
132 | ||
92040bd6 | 133 | clock: clock-controller@10010000 { |
34dcedfb CK |
134 | compatible = "samsung,exynos5420-clock"; |
135 | reg = <0x10010000 0x30000>; | |
136 | #clock-cells = <1>; | |
137 | }; | |
138 | ||
35e82775 AB |
139 | clock_audss: audss-clock-controller@3810000 { |
140 | compatible = "samsung,exynos5420-audss-clock"; | |
141 | reg = <0x03810000 0x0C>; | |
142 | #clock-cells = <1>; | |
1dd4e599 AH |
143 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, |
144 | <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; | |
59d711e9 | 145 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
35e82775 AB |
146 | }; |
147 | ||
8e371a91 | 148 | mfc: codec@11000000 { |
f09d062f AK |
149 | compatible = "samsung,mfc-v7"; |
150 | reg = <0x11000000 0x10000>; | |
151 | interrupts = <0 96 0>; | |
1dd4e599 | 152 | clocks = <&clock CLK_MFC>; |
f09d062f AK |
153 | clock-names = "mfc"; |
154 | }; | |
155 | ||
0e2c5915 YK |
156 | mmc_0: mmc@12200000 { |
157 | compatible = "samsung,exynos5420-dw-mshc-smu"; | |
158 | interrupts = <0 75 0>; | |
159 | #address-cells = <1>; | |
160 | #size-cells = <0>; | |
161 | reg = <0x12200000 0x2000>; | |
1dd4e599 | 162 | clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; |
0e2c5915 YK |
163 | clock-names = "biu", "ciu"; |
164 | fifo-depth = <0x40>; | |
165 | status = "disabled"; | |
166 | }; | |
167 | ||
168 | mmc_1: mmc@12210000 { | |
169 | compatible = "samsung,exynos5420-dw-mshc-smu"; | |
170 | interrupts = <0 76 0>; | |
171 | #address-cells = <1>; | |
172 | #size-cells = <0>; | |
173 | reg = <0x12210000 0x2000>; | |
1dd4e599 | 174 | clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; |
0e2c5915 YK |
175 | clock-names = "biu", "ciu"; |
176 | fifo-depth = <0x40>; | |
177 | status = "disabled"; | |
178 | }; | |
179 | ||
180 | mmc_2: mmc@12220000 { | |
181 | compatible = "samsung,exynos5420-dw-mshc"; | |
182 | interrupts = <0 77 0>; | |
183 | #address-cells = <1>; | |
184 | #size-cells = <0>; | |
185 | reg = <0x12220000 0x1000>; | |
1dd4e599 | 186 | clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; |
0e2c5915 YK |
187 | clock-names = "biu", "ciu"; |
188 | fifo-depth = <0x40>; | |
189 | status = "disabled"; | |
190 | }; | |
191 | ||
8e371a91 | 192 | mct: mct@101C0000 { |
34dcedfb CK |
193 | compatible = "samsung,exynos4210-mct"; |
194 | reg = <0x101C0000 0x800>; | |
195 | interrupt-controller; | |
196 | #interrups-cells = <1>; | |
197 | interrupt-parent = <&mct_map>; | |
6c16dedf CK |
198 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, |
199 | <8>, <9>, <10>, <11>; | |
1dd4e599 | 200 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
34dcedfb CK |
201 | clock-names = "fin_pll", "mct"; |
202 | ||
203 | mct_map: mct-map { | |
204 | #interrupt-cells = <1>; | |
205 | #address-cells = <0>; | |
206 | #size-cells = <0>; | |
207 | interrupt-map = <0 &combiner 23 3>, | |
208 | <1 &combiner 23 4>, | |
209 | <2 &combiner 25 2>, | |
210 | <3 &combiner 25 3>, | |
211 | <4 &gic 0 120 0>, | |
212 | <5 &gic 0 121 0>, | |
213 | <6 &gic 0 122 0>, | |
6c16dedf CK |
214 | <7 &gic 0 123 0>, |
215 | <8 &gic 0 128 0>, | |
216 | <9 &gic 0 129 0>, | |
217 | <10 &gic 0 130 0>, | |
218 | <11 &gic 0 131 0>; | |
34dcedfb CK |
219 | }; |
220 | }; | |
221 | ||
dcfca2cc YSB |
222 | gsc_pd: power-domain@10044000 { |
223 | compatible = "samsung,exynos4210-pd"; | |
224 | reg = <0x10044000 0x20>; | |
225 | }; | |
226 | ||
227 | isp_pd: power-domain@10044020 { | |
228 | compatible = "samsung,exynos4210-pd"; | |
229 | reg = <0x10044020 0x20>; | |
230 | }; | |
231 | ||
232 | mfc_pd: power-domain@10044060 { | |
233 | compatible = "samsung,exynos4210-pd"; | |
234 | reg = <0x10044060 0x20>; | |
235 | }; | |
236 | ||
237 | disp_pd: power-domain@100440C0 { | |
238 | compatible = "samsung,exynos4210-pd"; | |
239 | reg = <0x100440C0 0x20>; | |
240 | }; | |
241 | ||
242 | mau_pd: power-domain@100440E0 { | |
243 | compatible = "samsung,exynos4210-pd"; | |
244 | reg = <0x100440E0 0x20>; | |
245 | }; | |
246 | ||
247 | g2d_pd: power-domain@10044100 { | |
248 | compatible = "samsung,exynos4210-pd"; | |
249 | reg = <0x10044100 0x20>; | |
250 | }; | |
251 | ||
252 | msc_pd: power-domain@10044120 { | |
253 | compatible = "samsung,exynos4210-pd"; | |
254 | reg = <0x10044120 0x20>; | |
255 | }; | |
256 | ||
d81c6cbe LKA |
257 | pinctrl_0: pinctrl@13400000 { |
258 | compatible = "samsung,exynos5420-pinctrl"; | |
259 | reg = <0x13400000 0x1000>; | |
260 | interrupts = <0 45 0>; | |
261 | ||
262 | wakeup-interrupt-controller { | |
263 | compatible = "samsung,exynos4210-wakeup-eint"; | |
264 | interrupt-parent = <&gic>; | |
265 | interrupts = <0 32 0>; | |
266 | }; | |
267 | }; | |
268 | ||
269 | pinctrl_1: pinctrl@13410000 { | |
270 | compatible = "samsung,exynos5420-pinctrl"; | |
271 | reg = <0x13410000 0x1000>; | |
272 | interrupts = <0 78 0>; | |
273 | }; | |
274 | ||
275 | pinctrl_2: pinctrl@14000000 { | |
276 | compatible = "samsung,exynos5420-pinctrl"; | |
277 | reg = <0x14000000 0x1000>; | |
278 | interrupts = <0 46 0>; | |
279 | }; | |
280 | ||
281 | pinctrl_3: pinctrl@14010000 { | |
282 | compatible = "samsung,exynos5420-pinctrl"; | |
283 | reg = <0x14010000 0x1000>; | |
284 | interrupts = <0 50 0>; | |
285 | }; | |
286 | ||
287 | pinctrl_4: pinctrl@03860000 { | |
288 | compatible = "samsung,exynos5420-pinctrl"; | |
289 | reg = <0x03860000 0x1000>; | |
290 | interrupts = <0 47 0>; | |
291 | }; | |
292 | ||
8e371a91 | 293 | rtc: rtc@101E0000 { |
1dd4e599 | 294 | clocks = <&clock CLK_RTC>; |
a81951d9 | 295 | clock-names = "rtc"; |
451c402b | 296 | status = "disabled"; |
a81951d9 VS |
297 | }; |
298 | ||
e3188533 PV |
299 | amba { |
300 | #address-cells = <1>; | |
301 | #size-cells = <1>; | |
302 | compatible = "arm,amba-bus"; | |
303 | interrupt-parent = <&gic>; | |
304 | ranges; | |
305 | ||
6dd2f1c4 SK |
306 | adma: adma@03880000 { |
307 | compatible = "arm,pl330", "arm,primecell"; | |
308 | reg = <0x03880000 0x1000>; | |
309 | interrupts = <0 110 0>; | |
310 | clocks = <&clock_audss EXYNOS_ADMA>; | |
311 | clock-names = "apb_pclk"; | |
312 | #dma-cells = <1>; | |
313 | #dma-channels = <6>; | |
314 | #dma-requests = <16>; | |
315 | }; | |
316 | ||
e3188533 PV |
317 | pdma0: pdma@121A0000 { |
318 | compatible = "arm,pl330", "arm,primecell"; | |
319 | reg = <0x121A0000 0x1000>; | |
320 | interrupts = <0 34 0>; | |
1dd4e599 | 321 | clocks = <&clock CLK_PDMA0>; |
e3188533 PV |
322 | clock-names = "apb_pclk"; |
323 | #dma-cells = <1>; | |
324 | #dma-channels = <8>; | |
325 | #dma-requests = <32>; | |
326 | }; | |
327 | ||
328 | pdma1: pdma@121B0000 { | |
329 | compatible = "arm,pl330", "arm,primecell"; | |
330 | reg = <0x121B0000 0x1000>; | |
331 | interrupts = <0 35 0>; | |
1dd4e599 | 332 | clocks = <&clock CLK_PDMA1>; |
e3188533 PV |
333 | clock-names = "apb_pclk"; |
334 | #dma-cells = <1>; | |
335 | #dma-channels = <8>; | |
336 | #dma-requests = <32>; | |
337 | }; | |
338 | ||
339 | mdma0: mdma@10800000 { | |
340 | compatible = "arm,pl330", "arm,primecell"; | |
341 | reg = <0x10800000 0x1000>; | |
342 | interrupts = <0 33 0>; | |
1dd4e599 | 343 | clocks = <&clock CLK_MDMA0>; |
e3188533 PV |
344 | clock-names = "apb_pclk"; |
345 | #dma-cells = <1>; | |
346 | #dma-channels = <8>; | |
347 | #dma-requests = <1>; | |
348 | }; | |
349 | ||
350 | mdma1: mdma@11C10000 { | |
351 | compatible = "arm,pl330", "arm,primecell"; | |
352 | reg = <0x11C10000 0x1000>; | |
353 | interrupts = <0 124 0>; | |
1dd4e599 | 354 | clocks = <&clock CLK_MDMA1>; |
e3188533 PV |
355 | clock-names = "apb_pclk"; |
356 | #dma-cells = <1>; | |
357 | #dma-channels = <8>; | |
358 | #dma-requests = <1>; | |
359 | }; | |
360 | }; | |
361 | ||
98bcb547 SK |
362 | i2s0: i2s@03830000 { |
363 | compatible = "samsung,exynos5420-i2s"; | |
364 | reg = <0x03830000 0x100>; | |
365 | dmas = <&adma 0 | |
366 | &adma 2 | |
367 | &adma 1>; | |
368 | dma-names = "tx", "rx", "tx-sec"; | |
369 | clocks = <&clock_audss EXYNOS_I2S_BUS>, | |
370 | <&clock_audss EXYNOS_I2S_BUS>, | |
371 | <&clock_audss EXYNOS_SCLK_I2S>; | |
372 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
373 | samsung,idma-addr = <0x03000000>; | |
374 | pinctrl-names = "default"; | |
375 | pinctrl-0 = <&i2s0_bus>; | |
376 | status = "disabled"; | |
377 | }; | |
378 | ||
379 | i2s1: i2s@12D60000 { | |
380 | compatible = "samsung,exynos5420-i2s"; | |
381 | reg = <0x12D60000 0x100>; | |
382 | dmas = <&pdma1 12 | |
383 | &pdma1 11>; | |
384 | dma-names = "tx", "rx"; | |
1dd4e599 | 385 | clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; |
98bcb547 SK |
386 | clock-names = "iis", "i2s_opclk0"; |
387 | pinctrl-names = "default"; | |
388 | pinctrl-0 = <&i2s1_bus>; | |
389 | status = "disabled"; | |
390 | }; | |
391 | ||
392 | i2s2: i2s@12D70000 { | |
393 | compatible = "samsung,exynos5420-i2s"; | |
394 | reg = <0x12D70000 0x100>; | |
395 | dmas = <&pdma0 12 | |
396 | &pdma0 11>; | |
397 | dma-names = "tx", "rx"; | |
1dd4e599 | 398 | clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; |
98bcb547 SK |
399 | clock-names = "iis", "i2s_opclk0"; |
400 | pinctrl-names = "default"; | |
401 | pinctrl-0 = <&i2s2_bus>; | |
402 | status = "disabled"; | |
403 | }; | |
404 | ||
e84a2d91 LKA |
405 | spi_0: spi@12d20000 { |
406 | compatible = "samsung,exynos4210-spi"; | |
407 | reg = <0x12d20000 0x100>; | |
408 | interrupts = <0 66 0>; | |
409 | dmas = <&pdma0 5 | |
410 | &pdma0 4>; | |
411 | dma-names = "tx", "rx"; | |
412 | #address-cells = <1>; | |
413 | #size-cells = <0>; | |
414 | pinctrl-names = "default"; | |
415 | pinctrl-0 = <&spi0_bus>; | |
1dd4e599 | 416 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
e84a2d91 LKA |
417 | clock-names = "spi", "spi_busclk0"; |
418 | status = "disabled"; | |
419 | }; | |
420 | ||
421 | spi_1: spi@12d30000 { | |
422 | compatible = "samsung,exynos4210-spi"; | |
423 | reg = <0x12d30000 0x100>; | |
424 | interrupts = <0 67 0>; | |
425 | dmas = <&pdma1 5 | |
426 | &pdma1 4>; | |
427 | dma-names = "tx", "rx"; | |
428 | #address-cells = <1>; | |
429 | #size-cells = <0>; | |
430 | pinctrl-names = "default"; | |
431 | pinctrl-0 = <&spi1_bus>; | |
1dd4e599 | 432 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
e84a2d91 LKA |
433 | clock-names = "spi", "spi_busclk0"; |
434 | status = "disabled"; | |
435 | }; | |
436 | ||
437 | spi_2: spi@12d40000 { | |
438 | compatible = "samsung,exynos4210-spi"; | |
439 | reg = <0x12d40000 0x100>; | |
440 | interrupts = <0 68 0>; | |
441 | dmas = <&pdma0 7 | |
442 | &pdma0 6>; | |
443 | dma-names = "tx", "rx"; | |
444 | #address-cells = <1>; | |
445 | #size-cells = <0>; | |
446 | pinctrl-names = "default"; | |
447 | pinctrl-0 = <&spi2_bus>; | |
1dd4e599 | 448 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
e84a2d91 LKA |
449 | clock-names = "spi", "spi_busclk0"; |
450 | status = "disabled"; | |
451 | }; | |
452 | ||
8e371a91 | 453 | uart_0: serial@12C00000 { |
1dd4e599 | 454 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
34dcedfb CK |
455 | clock-names = "uart", "clk_uart_baud0"; |
456 | }; | |
457 | ||
8e371a91 | 458 | uart_1: serial@12C10000 { |
1dd4e599 | 459 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
34dcedfb CK |
460 | clock-names = "uart", "clk_uart_baud0"; |
461 | }; | |
462 | ||
8e371a91 | 463 | uart_2: serial@12C20000 { |
1dd4e599 | 464 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
34dcedfb CK |
465 | clock-names = "uart", "clk_uart_baud0"; |
466 | }; | |
467 | ||
8e371a91 | 468 | uart_3: serial@12C30000 { |
1dd4e599 | 469 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
34dcedfb CK |
470 | clock-names = "uart", "clk_uart_baud0"; |
471 | }; | |
ee3381d4 | 472 | |
022cf308 LKA |
473 | pwm: pwm@12dd0000 { |
474 | compatible = "samsung,exynos4210-pwm"; | |
475 | reg = <0x12dd0000 0x100>; | |
476 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
477 | #pwm-cells = <3>; | |
1dd4e599 | 478 | clocks = <&clock CLK_PWM>; |
022cf308 LKA |
479 | clock-names = "timers"; |
480 | }; | |
481 | ||
1339d33a VS |
482 | dp_phy: video-phy@10040728 { |
483 | compatible = "samsung,exynos5250-dp-video-phy"; | |
484 | reg = <0x10040728 4>; | |
485 | #phy-cells = <0>; | |
486 | }; | |
487 | ||
8e371a91 | 488 | dp: dp-controller@145B0000 { |
1dd4e599 | 489 | clocks = <&clock CLK_DP1>; |
1339d33a VS |
490 | clock-names = "dp"; |
491 | phys = <&dp_phy>; | |
492 | phy-names = "dp"; | |
493 | }; | |
494 | ||
8e371a91 | 495 | fimd: fimd@14400000 { |
ee3381d4 | 496 | samsung,power-domain = <&disp_pd>; |
1dd4e599 | 497 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
ee3381d4 VS |
498 | clock-names = "sclk_fimd", "fimd"; |
499 | }; | |
f408f9db NKC |
500 | |
501 | adc: adc@12D10000 { | |
502 | compatible = "samsung,exynos-adc-v2"; | |
503 | reg = <0x12D10000 0x100>, <0x10040720 0x4>; | |
504 | interrupts = <0 106 0>; | |
1dd4e599 | 505 | clocks = <&clock CLK_TSADC>; |
f408f9db NKC |
506 | clock-names = "adc"; |
507 | #io-channel-cells = <1>; | |
508 | io-channel-ranges; | |
509 | status = "disabled"; | |
510 | }; | |
f49e347b AB |
511 | |
512 | i2c_0: i2c@12C60000 { | |
513 | compatible = "samsung,s3c2440-i2c"; | |
514 | reg = <0x12C60000 0x100>; | |
515 | interrupts = <0 56 0>; | |
516 | #address-cells = <1>; | |
517 | #size-cells = <0>; | |
1dd4e599 | 518 | clocks = <&clock CLK_I2C0>; |
f49e347b AB |
519 | clock-names = "i2c"; |
520 | pinctrl-names = "default"; | |
521 | pinctrl-0 = <&i2c0_bus>; | |
522 | status = "disabled"; | |
523 | }; | |
524 | ||
525 | i2c_1: i2c@12C70000 { | |
526 | compatible = "samsung,s3c2440-i2c"; | |
527 | reg = <0x12C70000 0x100>; | |
528 | interrupts = <0 57 0>; | |
529 | #address-cells = <1>; | |
530 | #size-cells = <0>; | |
1dd4e599 | 531 | clocks = <&clock CLK_I2C1>; |
f49e347b AB |
532 | clock-names = "i2c"; |
533 | pinctrl-names = "default"; | |
534 | pinctrl-0 = <&i2c1_bus>; | |
535 | status = "disabled"; | |
536 | }; | |
537 | ||
538 | i2c_2: i2c@12C80000 { | |
539 | compatible = "samsung,s3c2440-i2c"; | |
540 | reg = <0x12C80000 0x100>; | |
541 | interrupts = <0 58 0>; | |
542 | #address-cells = <1>; | |
543 | #size-cells = <0>; | |
1dd4e599 | 544 | clocks = <&clock CLK_I2C2>; |
f49e347b AB |
545 | clock-names = "i2c"; |
546 | pinctrl-names = "default"; | |
547 | pinctrl-0 = <&i2c2_bus>; | |
548 | status = "disabled"; | |
549 | }; | |
550 | ||
551 | i2c_3: i2c@12C90000 { | |
552 | compatible = "samsung,s3c2440-i2c"; | |
553 | reg = <0x12C90000 0x100>; | |
554 | interrupts = <0 59 0>; | |
555 | #address-cells = <1>; | |
556 | #size-cells = <0>; | |
1dd4e599 | 557 | clocks = <&clock CLK_I2C3>; |
f49e347b AB |
558 | clock-names = "i2c"; |
559 | pinctrl-names = "default"; | |
560 | pinctrl-0 = <&i2c3_bus>; | |
561 | status = "disabled"; | |
562 | }; | |
b0e505ce | 563 | |
1a9110d6 SK |
564 | hsi2c_4: i2c@12CA0000 { |
565 | compatible = "samsung,exynos5-hsi2c"; | |
566 | reg = <0x12CA0000 0x1000>; | |
567 | interrupts = <0 60 0>; | |
568 | #address-cells = <1>; | |
569 | #size-cells = <0>; | |
570 | pinctrl-names = "default"; | |
571 | pinctrl-0 = <&i2c4_hs_bus>; | |
1dd4e599 | 572 | clocks = <&clock CLK_I2C4>; |
1a9110d6 SK |
573 | clock-names = "hsi2c"; |
574 | status = "disabled"; | |
575 | }; | |
576 | ||
577 | hsi2c_5: i2c@12CB0000 { | |
578 | compatible = "samsung,exynos5-hsi2c"; | |
579 | reg = <0x12CB0000 0x1000>; | |
580 | interrupts = <0 61 0>; | |
581 | #address-cells = <1>; | |
582 | #size-cells = <0>; | |
583 | pinctrl-names = "default"; | |
584 | pinctrl-0 = <&i2c5_hs_bus>; | |
1dd4e599 | 585 | clocks = <&clock CLK_I2C5>; |
1a9110d6 SK |
586 | clock-names = "hsi2c"; |
587 | status = "disabled"; | |
588 | }; | |
589 | ||
590 | hsi2c_6: i2c@12CC0000 { | |
591 | compatible = "samsung,exynos5-hsi2c"; | |
592 | reg = <0x12CC0000 0x1000>; | |
593 | interrupts = <0 62 0>; | |
594 | #address-cells = <1>; | |
595 | #size-cells = <0>; | |
596 | pinctrl-names = "default"; | |
597 | pinctrl-0 = <&i2c6_hs_bus>; | |
1dd4e599 | 598 | clocks = <&clock CLK_I2C6>; |
1a9110d6 SK |
599 | clock-names = "hsi2c"; |
600 | status = "disabled"; | |
601 | }; | |
602 | ||
603 | hsi2c_7: i2c@12CD0000 { | |
604 | compatible = "samsung,exynos5-hsi2c"; | |
605 | reg = <0x12CD0000 0x1000>; | |
606 | interrupts = <0 63 0>; | |
607 | #address-cells = <1>; | |
608 | #size-cells = <0>; | |
609 | pinctrl-names = "default"; | |
610 | pinctrl-0 = <&i2c7_hs_bus>; | |
1dd4e599 | 611 | clocks = <&clock CLK_I2C7>; |
1a9110d6 SK |
612 | clock-names = "hsi2c"; |
613 | status = "disabled"; | |
614 | }; | |
615 | ||
616 | hsi2c_8: i2c@12E00000 { | |
617 | compatible = "samsung,exynos5-hsi2c"; | |
618 | reg = <0x12E00000 0x1000>; | |
619 | interrupts = <0 87 0>; | |
620 | #address-cells = <1>; | |
621 | #size-cells = <0>; | |
622 | pinctrl-names = "default"; | |
623 | pinctrl-0 = <&i2c8_hs_bus>; | |
1dd4e599 | 624 | clocks = <&clock CLK_I2C8>; |
1a9110d6 SK |
625 | clock-names = "hsi2c"; |
626 | status = "disabled"; | |
627 | }; | |
628 | ||
629 | hsi2c_9: i2c@12E10000 { | |
630 | compatible = "samsung,exynos5-hsi2c"; | |
631 | reg = <0x12E10000 0x1000>; | |
632 | interrupts = <0 88 0>; | |
633 | #address-cells = <1>; | |
634 | #size-cells = <0>; | |
635 | pinctrl-names = "default"; | |
636 | pinctrl-0 = <&i2c9_hs_bus>; | |
1dd4e599 | 637 | clocks = <&clock CLK_I2C9>; |
1a9110d6 SK |
638 | clock-names = "hsi2c"; |
639 | status = "disabled"; | |
640 | }; | |
641 | ||
642 | hsi2c_10: i2c@12E20000 { | |
643 | compatible = "samsung,exynos5-hsi2c"; | |
644 | reg = <0x12E20000 0x1000>; | |
645 | interrupts = <0 203 0>; | |
646 | #address-cells = <1>; | |
647 | #size-cells = <0>; | |
648 | pinctrl-names = "default"; | |
649 | pinctrl-0 = <&i2c10_hs_bus>; | |
1dd4e599 | 650 | clocks = <&clock CLK_I2C10>; |
1a9110d6 SK |
651 | clock-names = "hsi2c"; |
652 | status = "disabled"; | |
653 | }; | |
654 | ||
8e371a91 | 655 | hdmi: hdmi@14530000 { |
2963c554 | 656 | compatible = "samsung,exynos5420-hdmi"; |
b0e505ce RS |
657 | reg = <0x14530000 0x70000>; |
658 | interrupts = <0 95 0>; | |
1dd4e599 AH |
659 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
660 | <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
661 | <&clock CLK_MOUT_HDMI>; | |
b0e505ce RS |
662 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
663 | "sclk_hdmiphy", "mout_hdmi"; | |
6ac189fc | 664 | phy = <&hdmiphy>; |
b0e505ce RS |
665 | status = "disabled"; |
666 | }; | |
667 | ||
6ac189fc RS |
668 | hdmiphy: hdmiphy@145D0000 { |
669 | reg = <0x145D0000 0x20>; | |
670 | }; | |
671 | ||
8e371a91 | 672 | mixer: mixer@14450000 { |
b0e505ce RS |
673 | compatible = "samsung,exynos5420-mixer"; |
674 | reg = <0x14450000 0x10000>; | |
675 | interrupts = <0 94 0>; | |
1dd4e599 | 676 | clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; |
b0e505ce RS |
677 | clock-names = "mixer", "sclk_hdmi"; |
678 | }; | |
01eb4636 LKA |
679 | |
680 | gsc_0: video-scaler@13e00000 { | |
681 | compatible = "samsung,exynos5-gsc"; | |
682 | reg = <0x13e00000 0x1000>; | |
683 | interrupts = <0 85 0>; | |
1dd4e599 | 684 | clocks = <&clock CLK_GSCL0>; |
01eb4636 LKA |
685 | clock-names = "gscl"; |
686 | samsung,power-domain = <&gsc_pd>; | |
687 | }; | |
688 | ||
689 | gsc_1: video-scaler@13e10000 { | |
690 | compatible = "samsung,exynos5-gsc"; | |
691 | reg = <0x13e10000 0x1000>; | |
692 | interrupts = <0 86 0>; | |
1dd4e599 | 693 | clocks = <&clock CLK_GSCL1>; |
01eb4636 LKA |
694 | clock-names = "gscl"; |
695 | samsung,power-domain = <&gsc_pd>; | |
696 | }; | |
655de648 | 697 | |
c680036a LKA |
698 | pmu_system_controller: system-controller@10040000 { |
699 | compatible = "samsung,exynos5420-pmu", "syscon"; | |
700 | reg = <0x10040000 0x5000>; | |
701 | }; | |
702 | ||
655de648 NKC |
703 | tmu_cpu0: tmu@10060000 { |
704 | compatible = "samsung,exynos5420-tmu"; | |
705 | reg = <0x10060000 0x100>; | |
706 | interrupts = <0 65 0>; | |
1dd4e599 | 707 | clocks = <&clock CLK_TMU>; |
655de648 NKC |
708 | clock-names = "tmu_apbif"; |
709 | }; | |
710 | ||
711 | tmu_cpu1: tmu@10064000 { | |
712 | compatible = "samsung,exynos5420-tmu"; | |
713 | reg = <0x10064000 0x100>; | |
714 | interrupts = <0 183 0>; | |
1dd4e599 | 715 | clocks = <&clock CLK_TMU>; |
655de648 NKC |
716 | clock-names = "tmu_apbif"; |
717 | }; | |
718 | ||
719 | tmu_cpu2: tmu@10068000 { | |
720 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
721 | reg = <0x10068000 0x100>, <0x1006c000 0x4>; | |
722 | interrupts = <0 184 0>; | |
1dd4e599 | 723 | clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; |
655de648 NKC |
724 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
725 | }; | |
726 | ||
727 | tmu_cpu3: tmu@1006c000 { | |
728 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
729 | reg = <0x1006c000 0x100>, <0x100a0000 0x4>; | |
730 | interrupts = <0 185 0>; | |
1dd4e599 | 731 | clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; |
655de648 NKC |
732 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
733 | }; | |
734 | ||
735 | tmu_gpu: tmu@100a0000 { | |
736 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
737 | reg = <0x100a0000 0x100>, <0x10068000 0x4>; | |
738 | interrupts = <0 215 0>; | |
1dd4e599 | 739 | clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; |
655de648 NKC |
740 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
741 | }; | |
1d287620 | 742 | |
8e371a91 | 743 | watchdog: watchdog@101D0000 { |
1d287620 LKA |
744 | compatible = "samsung,exynos5420-wdt"; |
745 | reg = <0x101D0000 0x100>; | |
746 | interrupts = <0 42 0>; | |
1dd4e599 | 747 | clocks = <&clock CLK_WDT>; |
1d287620 LKA |
748 | clock-names = "watchdog"; |
749 | samsung,syscon-phandle = <&pmu_system_controller>; | |
750 | }; | |
183af252 | 751 | |
8e371a91 | 752 | sss: sss@10830000 { |
183af252 NKC |
753 | compatible = "samsung,exynos4210-secss"; |
754 | reg = <0x10830000 0x10000>; | |
755 | interrupts = <0 112 0>; | |
756 | clocks = <&clock 471>; | |
757 | clock-names = "secss"; | |
758 | samsung,power-domain = <&g2d_pd>; | |
759 | }; | |
3cb7d1cd | 760 | |
f070267b VG |
761 | usbdrd3_0: usb@12000000 { |
762 | compatible = "samsung,exynos5250-dwusb3"; | |
763 | clocks = <&clock CLK_USBD300>; | |
764 | clock-names = "usbdrd30"; | |
765 | #address-cells = <1>; | |
766 | #size-cells = <1>; | |
767 | ranges; | |
768 | ||
769 | dwc3 { | |
770 | compatible = "snps,dwc3"; | |
771 | reg = <0x12000000 0x10000>; | |
772 | interrupts = <0 72 0>; | |
773 | phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; | |
774 | phy-names = "usb2-phy", "usb3-phy"; | |
775 | }; | |
776 | }; | |
777 | ||
3cb7d1cd VG |
778 | usbdrd_phy0: phy@12100000 { |
779 | compatible = "samsung,exynos5420-usbdrd-phy"; | |
780 | reg = <0x12100000 0x100>; | |
781 | clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; | |
782 | clock-names = "phy", "ref"; | |
783 | samsung,pmu-syscon = <&pmu_system_controller>; | |
784 | #phy-cells = <1>; | |
785 | }; | |
786 | ||
f070267b VG |
787 | usbdrd3_1: usb@12400000 { |
788 | compatible = "samsung,exynos5250-dwusb3"; | |
789 | clocks = <&clock CLK_USBD301>; | |
790 | clock-names = "usbdrd30"; | |
791 | #address-cells = <1>; | |
792 | #size-cells = <1>; | |
793 | ranges; | |
794 | ||
795 | dwc3 { | |
796 | compatible = "snps,dwc3"; | |
797 | reg = <0x12400000 0x10000>; | |
798 | interrupts = <0 73 0>; | |
799 | phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; | |
800 | phy-names = "usb2-phy", "usb3-phy"; | |
801 | }; | |
802 | }; | |
803 | ||
3cb7d1cd VG |
804 | usbdrd_phy1: phy@12500000 { |
805 | compatible = "samsung,exynos5420-usbdrd-phy"; | |
806 | reg = <0x12500000 0x100>; | |
807 | clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; | |
808 | clock-names = "phy", "ref"; | |
809 | samsung,pmu-syscon = <&pmu_system_controller>; | |
810 | #phy-cells = <1>; | |
811 | }; | |
34dcedfb | 812 | }; |