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Merge tag 'for-linus-20170825' of git://git.infradead.org/linux-mtd
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / exynos5422-odroidxu3-common.dtsi
CommitLineData
3a7c01d7
KK		 1/*
2 * Hardkernel Odroid XU3 board device tree source
3 *
3a7c01d7
KK		 4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
f4715dc7
KK		 6 * Copyright (c) 2014 Collabora Ltd.
7 * Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
8 * Anand Moon <linux.amoon@gmail.com>
3a7c01d7
KK		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <dt-bindings/clock/samsung,s2mps11.h>
16#include <dt-bindings/interrupt-controller/irq.h>
17#include <dt-bindings/gpio/gpio.h>
18#include <dt-bindings/sound/samsung-i2s.h>
19#include "exynos5800.dtsi"
df09df6f 20#include "exynos5422-cpus.dtsi"
3a7c01d7
KK		 21
22/ {
a0eb1095 23 memory@40000000 {
12676ee1 24 device_type = "memory";
3a7c01d7
KK		 25 reg = <0x40000000 0x7EA00000>;
26 };
27
28 chosen {
5a5232d1 29 stdout-path = "serial2:115200n8";
3a7c01d7
KK		 30 };
31
32 firmware@02073000 {
33 compatible = "samsung,secure-firmware";
34 reg = <0x02073000 0x1000>;
35 };
36
37 fixed-rate-clocks {
38 oscclk {
39 compatible = "samsung,exynos5420-oscclk";
40 clock-frequency = <24000000>;
41 };
42 };
43
44 emmc_pwrseq: pwrseq {
45 pinctrl-0 = <&emmc_nrst_pin>;
46 pinctrl-names = "default";
47 compatible = "mmc-pwrseq-emmc";
31b9903c 48 reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
3a7c01d7
KK		 49 };
50
b685d540
AM		 51 fan0: pwm-fan {
52 compatible = "pwm-fan";
53 pwms = <&pwm 0 20972 0>;
54 cooling-min-state = <0>;
55 cooling-max-state = <3>;
56 #cooling-cells = <2>;
57 cooling-levels = <0 130 170 230>;
58 };
f4715dc7
KK		 59
60 thermal-zones {
61 cpu0_thermal: cpu0-thermal {
62 thermal-sensors = <&tmu_cpu0 0>;
63 polling-delay-passive = <250>;
64 polling-delay = <0>;
65 trips {
66 cpu_alert0: cpu-alert-0 {
67 temperature = <50000>; /* millicelsius */
68 hysteresis = <5000>; /* millicelsius */
69 type = "active";
70 };
71 cpu_alert1: cpu-alert-1 {
72 temperature = <60000>; /* millicelsius */
73 hysteresis = <5000>; /* millicelsius */
74 type = "active";
75 };
76 cpu_alert2: cpu-alert-2 {
77 temperature = <70000>; /* millicelsius */
78 hysteresis = <5000>; /* millicelsius */
79 type = "active";
80 };
81 cpu_crit0: cpu-crit-0 {
82 temperature = <120000>; /* millicelsius */
83 hysteresis = <0>; /* millicelsius */
84 type = "critical";
85 };
86 /*
87 * Exynos542x supports only 4 trip-points
88 * so for these polling mode is required.
89 * Start polling at temperature level of last
90 * interrupt-driven trip: cpu_alert2
91 */
92 cpu_alert3: cpu-alert-3 {
93 temperature = <70000>; /* millicelsius */
94 hysteresis = <10000>; /* millicelsius */
95 type = "passive";
96 };
97 cpu_alert4: cpu-alert-4 {
98 temperature = <85000>; /* millicelsius */
99 hysteresis = <10000>; /* millicelsius */
100 type = "passive";
101 };
102
103 };
104 cooling-maps {
105 map0 {
106 trip = <&cpu_alert0>;
107 cooling-device = <&fan0 0 1>;
108 };
109 map1 {
110 trip = <&cpu_alert1>;
111 cooling-device = <&fan0 1 2>;
112 };
113 map2 {
114 trip = <&cpu_alert2>;
115 cooling-device = <&fan0 2 3>;
116 };
117 /*
118 * When reaching cpu_alert3, reduce CPU
119 * by 2 steps. On Exynos5422/5800 that would
120 * be: 1600 MHz and 1100 MHz.
121 */
122 map3 {
123 trip = <&cpu_alert3>;
124 cooling-device = <&cpu0 0 2>;
125 };
126 map4 {
127 trip = <&cpu_alert3>;
128 cooling-device = <&cpu4 0 2>;
129 };
130
131 /*
132 * When reaching cpu_alert4, reduce CPU
133 * further, down to 600 MHz (11 steps for big,
134 * 7 steps for LITTLE).
135 */
136 map5 {
137 trip = <&cpu_alert4>;
138 cooling-device = <&cpu0 3 7>;
139 };
140 map6 {
141 trip = <&cpu_alert4>;
142 cooling-device = <&cpu4 3 11>;
143 };
144 };
145 };
146 };
3a7c01d7
KK		 147};
148
c9a865bd
MR		 149&adc {
150 vdd-supply = <&ldo4_reg>;
151 status = "okay";
152};
153
3f2129fd
CC		 154&bus_wcore {
155 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
156 <&nocp_mem1_0>, <&nocp_mem1_1>;
157 vdd-supply = <&buck3_reg>;
158 exynos,saturation-ratio = <100>;
159 status = "okay";
160};
161
162&bus_noc {
163 devfreq = <&bus_wcore>;
164 status = "okay";
165};
166
167&bus_fsys_apb {
168 devfreq = <&bus_wcore>;
169 status = "okay";
170};
171
172&bus_fsys {
173 devfreq = <&bus_wcore>;
174 status = "okay";
175};
176
177&bus_fsys2 {
178 devfreq = <&bus_wcore>;
179 status = "okay";
180};
181
182&bus_mfc {
183 devfreq = <&bus_wcore>;
184 status = "okay";
185};
186
187&bus_gen {
188 devfreq = <&bus_wcore>;
189 status = "okay";
190};
191
192&bus_peri {
193 devfreq = <&bus_wcore>;
194 status = "okay";
195};
196
197&bus_g2d {
198 devfreq = <&bus_wcore>;
199 status = "okay";
200};
201
202&bus_g2d_acp {
203 devfreq = <&bus_wcore>;
204 status = "okay";
205};
206
207&bus_jpeg {
208 devfreq = <&bus_wcore>;
209 status = "okay";
210};
211
212&bus_jpeg_apb {
213 devfreq = <&bus_wcore>;
214 status = "okay";
215};
216
217&bus_disp1_fimd {
218 devfreq = <&bus_wcore>;
219 status = "okay";
220};
221
222&bus_disp1 {
223 devfreq = <&bus_wcore>;
224 status = "okay";
225};
226
227&bus_gscl_scaler {
228 devfreq = <&bus_wcore>;
229 status = "okay";
230};
231
232&bus_mscl {
233 devfreq = <&bus_wcore>;
234 status = "okay";
235};
236
3a7c01d7
KK		 237&clock_audss {
238 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
239 <&clock_audss EXYNOS_MOUT_I2S>,
240 <&clock_audss EXYNOS_DOUT_AUD_BUS>;
241 assigned-clock-parents = <&clock CLK_FIN_PLL>,
242 <&clock_audss EXYNOS_MOUT_AUDSS>;
243 assigned-clock-rates = <0>,
244 <0>,
245 <19200000>;
246};
247
8b51c5e7
BZ		 248&cpu0 {
249 cpu-supply = <&buck6_reg>;
250};
251
252&cpu4 {
253 cpu-supply = <&buck2_reg>;
254};
255
3a7c01d7
KK		 256&hdmi {
257 status = "okay";
05b01dd9 258 hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
3a7c01d7
KK		 259 pinctrl-names = "default";
260 pinctrl-0 = <&hdmi_hpd_irq>;
261
262 vdd_osc-supply = <&ldo7_reg>;
263 vdd_pll-supply = <&ldo6_reg>;
264 vdd-supply = <&ldo6_reg>;
265};
266
5343b157
MS		 267&hdmicec {
268 status = "okay";
93a4c835 269 needs-hpd;
5343b157
MS		 270};
271
3a7c01d7
KK		 272&hsi2c_4 {
273 status = "okay";
274
275 s2mps11_pmic@66 {
276 compatible = "samsung,s2mps11-pmic";
277 reg = <0x66>;
0fb033bb 278 samsung,s2mps11-acokb-ground;
3a7c01d7
KK		 279
280 interrupt-parent = <&gpx0>;
281 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&s2mps11_irq>;
284
285 s2mps11_osc: clocks {
286 #clock-cells = <1>;
287 clock-output-names = "s2mps11_ap",
288 "s2mps11_cp", "s2mps11_bt";
289 };
290
291 regulators {
292 ldo1_reg: LDO1 {
293 regulator-name = "vdd_ldo1";
294 regulator-min-microvolt = <1000000>;
295 regulator-max-microvolt = <1000000>;
296 regulator-always-on;
297 };
298
299 ldo3_reg: LDO3 {
399fc184 300 regulator-name = "vddq_mmc0";
3a7c01d7
KK		 301 regulator-min-microvolt = <1800000>;
302 regulator-max-microvolt = <1800000>;
3a7c01d7
KK		 303 };
304
c9a865bd
MR		 305 ldo4_reg: LDO4 {
306 regulator-name = "vdd_adc";
307 regulator-min-microvolt = <1800000>;
308 regulator-max-microvolt = <1800000>;
309 };
310
3a7c01d7
KK		 311 ldo5_reg: LDO5 {
312 regulator-name = "vdd_ldo5";
313 regulator-min-microvolt = <1800000>;
314 regulator-max-microvolt = <1800000>;
315 regulator-always-on;
316 };
317
318 ldo6_reg: LDO6 {
319 regulator-name = "vdd_ldo6";
320 regulator-min-microvolt = <1000000>;
321 regulator-max-microvolt = <1000000>;
322 regulator-always-on;
323 };
324
325 ldo7_reg: LDO7 {
326 regulator-name = "vdd_ldo7";
327 regulator-min-microvolt = <1800000>;
328 regulator-max-microvolt = <1800000>;
329 regulator-always-on;
330 };
331
332 ldo8_reg: LDO8 {
333 regulator-name = "vdd_ldo8";
334 regulator-min-microvolt = <1800000>;
335 regulator-max-microvolt = <1800000>;
336 regulator-always-on;
337 };
338
339 ldo9_reg: LDO9 {
340 regulator-name = "vdd_ldo9";
341 regulator-min-microvolt = <3000000>;
342 regulator-max-microvolt = <3000000>;
343 regulator-always-on;
344 };
345
346 ldo10_reg: LDO10 {
347 regulator-name = "vdd_ldo10";
348 regulator-min-microvolt = <1800000>;
349 regulator-max-microvolt = <1800000>;
350 regulator-always-on;
351 };
352
353 ldo11_reg: LDO11 {
354 regulator-name = "vdd_ldo11";
355 regulator-min-microvolt = <1000000>;
356 regulator-max-microvolt = <1000000>;
357 regulator-always-on;
358 };
359
360 ldo12_reg: LDO12 {
361 regulator-name = "vdd_ldo12";
362 regulator-min-microvolt = <1800000>;
363 regulator-max-microvolt = <1800000>;
364 regulator-always-on;
365 };
366
367 ldo13_reg: LDO13 {
399fc184 368 regulator-name = "vddq_mmc2";
3a7c01d7
KK		 369 regulator-min-microvolt = <2800000>;
370 regulator-max-microvolt = <2800000>;
3a7c01d7
KK		 371 };
372
373 ldo15_reg: LDO15 {
374 regulator-name = "vdd_ldo15";
375 regulator-min-microvolt = <3100000>;
376 regulator-max-microvolt = <3100000>;
377 regulator-always-on;
378 };
379
380 ldo16_reg: LDO16 {
381 regulator-name = "vdd_ldo16";
382 regulator-min-microvolt = <2200000>;
383 regulator-max-microvolt = <2200000>;
384 regulator-always-on;
385 };
386
387 ldo17_reg: LDO17 {
388 regulator-name = "tsp_avdd";
389 regulator-min-microvolt = <3300000>;
390 regulator-max-microvolt = <3300000>;
391 regulator-always-on;
392 };
393
399fc184
MR		 394 ldo18_reg: LDO18 {
395 regulator-name = "vdd_emmc_1V8";
396 regulator-min-microvolt = <1800000>;
397 regulator-max-microvolt = <1800000>;
398 };
399
3a7c01d7
KK		 400 ldo19_reg: LDO19 {
401 regulator-name = "vdd_sd";
402 regulator-min-microvolt = <2800000>;
403 regulator-max-microvolt = <2800000>;
3a7c01d7
KK		 404 };
405
406 ldo24_reg: LDO24 {
407 regulator-name = "tsp_io";
408 regulator-min-microvolt = <2800000>;
409 regulator-max-microvolt = <2800000>;
410 regulator-always-on;
411 };
412
413 ldo26_reg: LDO26 {
414 regulator-name = "vdd_ldo26";
415 regulator-min-microvolt = <3000000>;
416 regulator-max-microvolt = <3000000>;
417 regulator-always-on;
418 };
419
420 buck1_reg: BUCK1 {
421 regulator-name = "vdd_mif";
422 regulator-min-microvolt = <800000>;
423 regulator-max-microvolt = <1300000>;
424 regulator-always-on;
425 regulator-boot-on;
426 };
427
428 buck2_reg: BUCK2 {
429 regulator-name = "vdd_arm";
430 regulator-min-microvolt = <800000>;
431 regulator-max-microvolt = <1500000>;
432 regulator-always-on;
433 regulator-boot-on;
434 };
435
436 buck3_reg: BUCK3 {
437 regulator-name = "vdd_int";
438 regulator-min-microvolt = <800000>;
439 regulator-max-microvolt = <1400000>;
440 regulator-always-on;
441 regulator-boot-on;
442 };
443
444 buck4_reg: BUCK4 {
445 regulator-name = "vdd_g3d";
446 regulator-min-microvolt = <800000>;
447 regulator-max-microvolt = <1400000>;
448 regulator-always-on;
449 regulator-boot-on;
450 };
451
452 buck5_reg: BUCK5 {
453 regulator-name = "vdd_mem";
454 regulator-min-microvolt = <800000>;
455 regulator-max-microvolt = <1400000>;
456 regulator-always-on;
457 regulator-boot-on;
458 };
459
460 buck6_reg: BUCK6 {
461 regulator-name = "vdd_kfc";
462 regulator-min-microvolt = <800000>;
463 regulator-max-microvolt = <1500000>;
464 regulator-always-on;
465 regulator-boot-on;
466 };
467
468 buck7_reg: BUCK7 {
469 regulator-name = "vdd_1.0v_ldo";
470 regulator-min-microvolt = <800000>;
471 regulator-max-microvolt = <1500000>;
472 regulator-always-on;
473 regulator-boot-on;
474 };
475
476 buck8_reg: BUCK8 {
477 regulator-name = "vdd_1.8v_ldo";
478 regulator-min-microvolt = <800000>;
479 regulator-max-microvolt = <1500000>;
480 regulator-always-on;
481 regulator-boot-on;
482 };
483
484 buck9_reg: BUCK9 {
485 regulator-name = "vdd_2.8v_ldo";
486 regulator-min-microvolt = <3000000>;
487 regulator-max-microvolt = <3750000>;
488 regulator-always-on;
489 regulator-boot-on;
490 };
491
492 buck10_reg: BUCK10 {
493 regulator-name = "vdd_vmem";
494 regulator-min-microvolt = <2850000>;
495 regulator-max-microvolt = <2850000>;
496 regulator-always-on;
497 regulator-boot-on;
498 };
499 };
500 };
501};
502
3a7c01d7
KK		 503&i2c_2 {
504 samsung,i2c-sda-delay = <100>;
505 samsung,i2c-max-bus-freq = <66000>;
506 status = "okay";
507
508 hdmiddc@50 {
509 compatible = "samsung,exynos4210-hdmiddc";
510 reg = <0x50>;
511 };
512};
513
3a7c01d7
KK		 514&mmc_0 {
515 status = "okay";
516 mmc-pwrseq = <&emmc_pwrseq>;
3a7c01d7
KK		 517 card-detect-delay = <200>;
518 samsung,dw-mshc-ciu-div = <3>;
519 samsung,dw-mshc-sdr-timing = <0 4>;
520 samsung,dw-mshc-ddr-timing = <0 2>;
521 samsung,dw-mshc-hs400-timing = <0 2>;
522 samsung,read-strobe-delay = <90>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>;
525 bus-width = <8>;
526 cap-mmc-highspeed;
527 mmc-hs200-1_8v;
528 mmc-hs400-1_8v;
399fc184
MR		 529 vmmc-supply = <&ldo18_reg>;
530 vqmmc-supply = <&ldo3_reg>;
3a7c01d7
KK		 531};
532
533&mmc_2 {
534 status = "okay";
535 card-detect-delay = <200>;
536 samsung,dw-mshc-ciu-div = <3>;
537 samsung,dw-mshc-sdr-timing = <0 4>;
538 samsung,dw-mshc-ddr-timing = <0 2>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
541 bus-width = <4>;
542 cap-sd-highspeed;
399fc184
MR		 543 vmmc-supply = <&ldo19_reg>;
544 vqmmc-supply = <&ldo13_reg>;
3a7c01d7
KK		 545};
546
3f2129fd
CC		 547&nocp_mem0_0 {
548 status = "okay";
549};
550
551&nocp_mem0_1 {
552 status = "okay";
553};
554
555&nocp_mem1_0 {
556 status = "okay";
557};
558
559&nocp_mem1_1 {
560 status = "okay";
561};
562
3a7c01d7
KK		 563&pinctrl_0 {
564 hdmi_hpd_irq: hdmi-hpd-irq {
565 samsung,pins = "gpx3-7";
a2f2bc38
KK		 566 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
567 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
568 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
3a7c01d7
KK		 569 };
570
571 s2mps11_irq: s2mps11-irq {
572 samsung,pins = "gpx0-4";
a2f2bc38
KK		 573 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
574 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
575 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
3a7c01d7
KK		 576 };
577};
578
579&pinctrl_1 {
580 emmc_nrst_pin: emmc-nrst {
581 samsung,pins = "gpd1-0";
a2f2bc38
KK		 582 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
583 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
584 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
3a7c01d7
KK		 585 };
586};
587
8e946a05
AM		 588&tmu_cpu0 {
589 vtmu-supply = <&ldo7_reg>;
8e946a05
AM		 590};
591
592&tmu_cpu1 {
593 vtmu-supply = <&ldo7_reg>;
8e946a05
AM		 594};
595
596&tmu_cpu2 {
597 vtmu-supply = <&ldo7_reg>;
8e946a05
AM		 598};
599
600&tmu_cpu3 {
601 vtmu-supply = <&ldo7_reg>;
8e946a05
AM		 602};
603
604&tmu_gpu {
605 vtmu-supply = <&ldo7_reg>;
8e946a05
AM		 606};
607
3a7c01d7
KK		 608&rtc {
609 status = "okay";
610 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
611 clock-names = "rtc", "rtc_src";
612};
613
614&usbdrd_dwc3_0 {
615 dr_mode = "host";
616};
617
66583560 618/* usbdrd_dwc3_1 mode customized in each board */
dc929d49
AM		 619
620&usbdrd3_0 {
621 vdd33-supply = <&ldo9_reg>;
622 vdd10-supply = <&ldo11_reg>;
623};
624
625&usbdrd3_1 {
626 vdd33-supply = <&ldo9_reg>;
627 vdd10-supply = <&ldo11_reg>;
628};
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