[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / exynos5440.dtsi

/*
 * SAMSUNG EXYNOS5440 SoC device tree source
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <dt-bindings/clock/exynos5440.h>
#include "skeleton.dtsi"

/ {
	compatible = "samsung,exynos5440", "samsung,exynos5";

	interrupt-parent = <&gic>;

	aliases {
		serial0 = &serial_0;
		serial1 = &serial_1;
		spi0 = &spi_0;
		tmuctrl0 = &tmuctrl_0;
		tmuctrl1 = &tmuctrl_1;
		tmuctrl2 = &tmuctrl_2;
	};

	clock: clock-controller@160000 {
		compatible = "samsung,exynos5440-clock";
		reg = <0x160000 0x1000>;
		#clock-cells = <1>;
	};

	gic: interrupt-controller@2E0000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg =	<0x2E1000 0x1000>,
			<0x2E2000 0x1000>,
			<0x2E4000 0x2000>,
			<0x2E6000 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
		interrupts = <0 52 4>,
			     <0 53 4>,
			     <0 54 4>,
			     <0 55 4>;
	};

	timer {
		compatible = "arm,cortex-a15-timer",
			     "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
		clock-frequency = <50000000>;
	};

	cpufreq@160000 {
		compatible = "samsung,exynos5440-cpufreq";
		reg = <0x160000 0x1000>;
		interrupts = <0 57 0>;
		operating-points = <
				/* KHz	  uV */
				1500000 1100000
				1400000 1075000
				1300000 1050000
				1200000 1025000
				1100000 1000000
				1000000 975000
				900000  950000
				800000  925000
		>;
	};

	serial_0: serial@B0000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0xB0000 0x1000>;
		interrupts = <0 2 0>;
		clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
		clock-names = "uart", "clk_uart_baud0";
	};

	serial_1: serial@C0000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0xC0000 0x1000>;
		interrupts = <0 3 0>;
		clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
		clock-names = "uart", "clk_uart_baud0";
	};

	spi_0: spi@D0000 {
		compatible = "samsung,exynos5440-spi";
		reg = <0xD0000 0x100>;
		interrupts = <0 4 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		samsung,spi-src-clk = <0>;
		num-cs = <1>;
		clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
		clock-names = "spi", "spi_busclk0";
	};

	pin_ctrl: pinctrl {
		compatible = "samsung,exynos5440-pinctrl";
		reg = <0xE0000 0x1000>;
		interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
			     <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
		interrupt-controller;
		#interrupt-cells = <2>;
		#gpio-cells = <2>;

		fan: fan {
			samsung,exynos5440-pin-function = <1>;
		};

		hdd_led0: hdd_led0 {
			samsung,exynos5440-pin-function = <2>;
		};

		hdd_led1: hdd_led1 {
			samsung,exynos5440-pin-function = <3>;
		};

		uart1: uart1 {
			samsung,exynos5440-pin-function = <4>;
		};
	};

	i2c@F0000 {
		compatible = "samsung,exynos5440-i2c";
		reg = <0xF0000 0x1000>;
		interrupts = <0 5 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "i2c";
	};

	i2c@100000 {
		compatible = "samsung,exynos5440-i2c";
		reg = <0x100000 0x1000>;
		interrupts = <0 6 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "i2c";
	};

	watchdog@110000 {
		compatible = "samsung,s3c2410-wdt";
		reg = <0x110000 0x1000>;
		interrupts = <0 1 0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "watchdog";
	};

	gmac: ethernet@00230000 {
		compatible = "snps,dwmac-3.70a";
		reg = <0x00230000 0x8000>;
		interrupt-parent = <&gic>;
		interrupts = <0 31 4>;
		interrupt-names = "macirq";
		phy-mode = "sgmii";
		clocks = <&clock CLK_GMAC0>;
		clock-names = "stmmaceth";
	};

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,amba-bus";
		interrupt-parent = <&gic>;
		ranges;
	};

	rtc {
		compatible = "samsung,s3c6410-rtc";
		reg = <0x130000 0x1000>;
		interrupts = <0 17 0>, <0 16 0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "rtc";
	};

	tmuctrl_0: tmuctrl@160118 {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x160118 0x230>, <0x160368 0x10>;
		interrupts = <0 58 0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
		#include "exynos5440-tmu-sensor-conf.dtsi"
	};

	tmuctrl_1: tmuctrl@16011C {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x16011C 0x230>, <0x160368 0x10>;
		interrupts = <0 58 0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
		#include "exynos5440-tmu-sensor-conf.dtsi"
	};

	tmuctrl_2: tmuctrl@160120 {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x160120 0x230>, <0x160368 0x10>;
		interrupts = <0 58 0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
		#include "exynos5440-tmu-sensor-conf.dtsi"
	};

	thermal-zones {
		cpu0_thermal: cpu0-thermal {
			thermal-sensors = <&tmuctrl_0>;
			#include "exynos5440-trip-points.dtsi"
		};
		cpu1_thermal: cpu1-thermal {
		       thermal-sensors = <&tmuctrl_1>;
		       #include "exynos5440-trip-points.dtsi"
		};
		cpu2_thermal: cpu2-thermal {
		       thermal-sensors = <&tmuctrl_2>;
		       #include "exynos5440-trip-points.dtsi"
		};
	};

	sata@210000 {
		compatible = "snps,exynos5440-ahci";
		reg = <0x210000 0x10000>;
		interrupts = <0 30 0>;
		clocks = <&clock CLK_SATA>;
		clock-names = "sata";
	};

	ohci@220000 {
		compatible = "samsung,exynos5440-ohci";
		reg = <0x220000 0x1000>;
		interrupts = <0 29 0>;
		clocks = <&clock CLK_USB>;
		clock-names = "usbhost";
	};

	ehci@221000 {
		compatible = "samsung,exynos5440-ehci";
		reg = <0x221000 0x1000>;
		interrupts = <0 29 0>;
		clocks = <&clock CLK_USB>;
		clock-names = "usbhost";
	};

	pcie@290000 {
		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
		reg = <0x290000 0x1000
			0x270000 0x1000
			0x271000 0x40>;
		interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
		clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
		clock-names = "pcie", "pcie_bus";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
			  0x81000000 0 0	  0x40001000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0x0 0 &gic 53>;
		num-lanes = <4>;
		status = "disabled";
	};

	pcie@2a0000 {
		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
		reg = <0x2a0000 0x1000
			0x272000 0x1000
			0x271040 0x40>;
		interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
		clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
		clock-names = "pcie", "pcie_bus";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
			  0x81000000 0 0	  0x60001000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0x0 0 &gic 56>;
		num-lanes = <4>;
		status = "disabled";
	};
};
Commit	Line	Data
1355bbc4 KK	1	/*
	2	* SAMSUNG EXYNOS5440 SoC device tree source
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
86feafeb	12	#include <dt-bindings/clock/exynos5440.h>
3799279f	13	#include "skeleton.dtsi"
1355bbc4 KK	14
1355bbc4 KK	15	/ {
8bdb31b4	16	compatible = "samsung,exynos5440", "samsung,exynos5";
1355bbc4 KK	17
	18	interrupt-parent = <&gic>;
	19
dabd3f9d	20	aliases {
1e64f48e TF	21	serial0 = &serial_0;
1e64f48e TF	22	serial1 = &serial_1;
dabd3f9d	23	spi0 = &spi_0;
5c7311b5 ADK	24	tmuctrl0 = &tmuctrl_0;
	25	tmuctrl1 = &tmuctrl_1;
	26	tmuctrl2 = &tmuctrl_2;
dabd3f9d G	27	};
dabd3f9d G	28
644a79a8	29	clock: clock-controller@160000 {
d8bafc87 TA	30	compatible = "samsung,exynos5440-clock";
	31	reg = <0x160000 0x1000>;
	32	#clock-cells = <1>;
	33	};
	34
0572b725	35	gic: interrupt-controller@2E0000 {
1355bbc4 KK	36	compatible = "arm,cortex-a15-gic";
	37	#interrupt-cells = <3>;
	38	interrupt-controller;
3279dd36 GM	39	reg = <0x2E1000 0x1000>,
	40	<0x2E2000 0x1000>,
	41	<0x2E4000 0x2000>,
	42	<0x2E6000 0x2000>;
	43	interrupts = <1 9 0xf04>;
1355bbc4 KK	44	};
	45
	46	cpus {
f5108e1c KK	47	#address-cells = <1>;
	48	#size-cells = <0>;
	49
1355bbc4	50	cpu@0 {
88e41848	51	device_type = "cpu";
1355bbc4	52	compatible = "arm,cortex-a15";
f5108e1c	53	reg = <0>;
1355bbc4 KK	54	};
1355bbc4 KK	55	cpu@1 {
88e41848	56	device_type = "cpu";
1355bbc4	57	compatible = "arm,cortex-a15";
f5108e1c	58	reg = <1>;
1355bbc4 KK	59	};
1355bbc4 KK	60	cpu@2 {
88e41848	61	device_type = "cpu";
1355bbc4	62	compatible = "arm,cortex-a15";
f5108e1c	63	reg = <2>;
1355bbc4 KK	64	};
1355bbc4 KK	65	cpu@3 {
88e41848	66	device_type = "cpu";
1355bbc4	67	compatible = "arm,cortex-a15";
f5108e1c	68	reg = <3>;
1355bbc4 KK	69	};
	70	};
	71
4c46f51a SP	72	arm-pmu {
	73	compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
	74	interrupts = <0 52 4>,
	75	<0 53 4>,
	76	<0 54 4>,
	77	<0 55 4>;
	78	};
	79
f5108e1c KK	80	timer {
	81	compatible = "arm,cortex-a15-timer",
	82	"arm,armv7-timer";
	83	interrupts = <1 13 0xf08>,
	84	<1 14 0xf08>,
	85	<1 11 0xf08>,
	86	<1 10 0xf08>;
	87	clock-frequency = <50000000>;
	88	};
	89
7f7b8ed0 ADK	90	cpufreq@160000 {
	91	compatible = "samsung,exynos5440-cpufreq";
	92	reg = <0x160000 0x1000>;
	93	interrupts = <0 57 0>;
	94	operating-points = <
	95	/* KHz uV */
afbbf927 ADK	96	1500000 1100000
	97	1400000 1075000
	98	1300000 1050000
7f7b8ed0	99	1200000 1025000
afbbf927	100	1100000 1000000
7f7b8ed0	101	1000000 975000
afbbf927	102	900000 950000
7f7b8ed0 ADK	103	800000 925000
	104	>;
	105	};
	106
1e64f48e	107	serial_0: serial@B0000 {
1355bbc4 KK	108	compatible = "samsung,exynos4210-uart";
	109	reg = <0xB0000 0x1000>;
	110	interrupts = <0 2 0>;
86feafeb	111	clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
6a0338c2	112	clock-names = "uart", "clk_uart_baud0";
1355bbc4 KK	113	};
1355bbc4 KK	114
1e64f48e	115	serial_1: serial@C0000 {
1355bbc4 KK	116	compatible = "samsung,exynos4210-uart";
	117	reg = <0xC0000 0x1000>;
	118	interrupts = <0 3 0>;
86feafeb	119	clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
6a0338c2	120	clock-names = "uart", "clk_uart_baud0";
1355bbc4 KK	121	};
1355bbc4 KK	122
dabd3f9d G	123	spi_0: spi@D0000 {
	124	compatible = "samsung,exynos5440-spi";
	125	reg = <0xD0000 0x100>;
1355bbc4	126	interrupts = <0 4 0>;
1355bbc4 KK	127	#address-cells = <1>;
1355bbc4 KK	128	#size-cells = <0>;
dabd3f9d G	129	samsung,spi-src-clk = <0>;
dabd3f9d G	130	num-cs = <1>;
86feafeb	131	clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
6a0338c2	132	clock-names = "spi", "spi_busclk0";
1355bbc4 KK	133	};
1355bbc4 KK	134
b342e64c	135	pin_ctrl: pinctrl {
f6925432	136	compatible = "samsung,exynos5440-pinctrl";
1355bbc4	137	reg = <0xE0000 0x1000>;
71d87da3 TA	138	interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
71d87da3 TA	139	<0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
1355bbc4 KK	140	interrupt-controller;
1355bbc4 KK	141	#interrupt-cells = <2>;
b1ce101b TA	142	#gpio-cells = <2>;
	143
	144	fan: fan {
	145	samsung,exynos5440-pin-function = <1>;
	146	};
	147
	148	hdd_led0: hdd_led0 {
	149	samsung,exynos5440-pin-function = <2>;
	150	};
	151
	152	hdd_led1: hdd_led1 {
	153	samsung,exynos5440-pin-function = <3>;
	154	};
	155
	156	uart1: uart1 {
	157	samsung,exynos5440-pin-function = <4>;
	158	};
1355bbc4 KK	159	};
	160
	161	i2c@F0000 {
49498c56	162	compatible = "samsung,exynos5440-i2c";
1355bbc4 KK	163	reg = <0xF0000 0x1000>;
	164	interrupts = <0 5 0>;
	165	#address-cells = <1>;
	166	#size-cells = <0>;
86feafeb	167	clocks = <&clock CLK_B_125>;
6a0338c2	168	clock-names = "i2c";
1355bbc4 KK	169	};
	170
	171	i2c@100000 {
49498c56	172	compatible = "samsung,exynos5440-i2c";
1355bbc4 KK	173	reg = <0x100000 0x1000>;
	174	interrupts = <0 6 0>;
	175	#address-cells = <1>;
	176	#size-cells = <0>;
86feafeb	177	clocks = <&clock CLK_B_125>;
6a0338c2	178	clock-names = "i2c";
1355bbc4 KK	179	};
1355bbc4 KK	180
64f5d1eb	181	watchdog@110000 {
1355bbc4 KK	182	compatible = "samsung,s3c2410-wdt";
	183	reg = <0x110000 0x1000>;
	184	interrupts = <0 1 0>;
86feafeb	185	clocks = <&clock CLK_B_125>;
6a0338c2	186	clock-names = "watchdog";
1355bbc4 KK	187	};
1355bbc4 KK	188
c038c4d8 BA	189	gmac: ethernet@00230000 {
	190	compatible = "snps,dwmac-3.70a";
	191	reg = <0x00230000 0x8000>;
	192	interrupt-parent = <&gic>;
	193	interrupts = <0 31 4>;
	194	interrupt-names = "macirq";
	195	phy-mode = "sgmii";
86feafeb	196	clocks = <&clock CLK_GMAC0>;
c038c4d8 BA	197	clock-names = "stmmaceth";
	198	};
	199
1355bbc4 KK	200	amba {
	201	#address-cells = <1>;
	202	#size-cells = <1>;
	203	compatible = "arm,amba-bus";
	204	interrupt-parent = <&gic>;
	205	ranges;
1355bbc4 KK	206	};
	207
	208	rtc {
	209	compatible = "samsung,s3c6410-rtc";
	210	reg = <0x130000 0x1000>;
e877a5aa	211	interrupts = <0 17 0>, <0 16 0>;
86feafeb	212	clocks = <&clock CLK_B_125>;
6a0338c2	213	clock-names = "rtc";
1355bbc4	214	};
1a12f52e	215
5c7311b5 ADK	216	tmuctrl_0: tmuctrl@160118 {
	217	compatible = "samsung,exynos5440-tmu";
	218	reg = <0x160118 0x230>, <0x160368 0x10>;
	219	interrupts = <0 58 0>;
86feafeb	220	clocks = <&clock CLK_B_125>;
5c7311b5	221	clock-names = "tmu_apbif";
9843a223	222	#include "exynos5440-tmu-sensor-conf.dtsi"
5c7311b5 ADK	223	};
	224
	225	tmuctrl_1: tmuctrl@16011C {
	226	compatible = "samsung,exynos5440-tmu";
	227	reg = <0x16011C 0x230>, <0x160368 0x10>;
	228	interrupts = <0 58 0>;
86feafeb	229	clocks = <&clock CLK_B_125>;
5c7311b5	230	clock-names = "tmu_apbif";
9843a223	231	#include "exynos5440-tmu-sensor-conf.dtsi"
5c7311b5 ADK	232	};
	233
	234	tmuctrl_2: tmuctrl@160120 {
	235	compatible = "samsung,exynos5440-tmu";
	236	reg = <0x160120 0x230>, <0x160368 0x10>;
	237	interrupts = <0 58 0>;
86feafeb	238	clocks = <&clock CLK_B_125>;
5c7311b5	239	clock-names = "tmu_apbif";
9843a223 LM	240	#include "exynos5440-tmu-sensor-conf.dtsi"
	241	};
	242
	243	thermal-zones {
	244	cpu0_thermal: cpu0-thermal {
	245	thermal-sensors = <&tmuctrl_0>;
	246	#include "exynos5440-trip-points.dtsi"
	247	};
	248	cpu1_thermal: cpu1-thermal {
	249	thermal-sensors = <&tmuctrl_1>;
	250	#include "exynos5440-trip-points.dtsi"
	251	};
	252	cpu2_thermal: cpu2-thermal {
	253	thermal-sensors = <&tmuctrl_2>;
	254	#include "exynos5440-trip-points.dtsi"
	255	};
5c7311b5 ADK	256	};
5c7311b5 ADK	257
1a12f52e G	258	sata@210000 {
	259	compatible = "snps,exynos5440-ahci";
	260	reg = <0x210000 0x10000>;
	261	interrupts = <0 30 0>;
86feafeb	262	clocks = <&clock CLK_SATA>;
1a12f52e G	263	clock-names = "sata";
	264	};
	265
a3808905 TA	266	ohci@220000 {
	267	compatible = "samsung,exynos5440-ohci";
	268	reg = <0x220000 0x1000>;
	269	interrupts = <0 29 0>;
86feafeb	270	clocks = <&clock CLK_USB>;
a3808905 TA	271	clock-names = "usbhost";
	272	};
	273
	274	ehci@221000 {
	275	compatible = "samsung,exynos5440-ehci";
	276	reg = <0x221000 0x1000>;
	277	interrupts = <0 29 0>;
86feafeb	278	clocks = <&clock CLK_USB>;
a3808905	279	clock-names = "usbhost";
1355bbc4	280	};
406a9324 JH	281
	282	pcie@290000 {
	283	compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
	284	reg = <0x290000 0x1000
	285	0x270000 0x1000
	286	0x271000 0x40>;
	287	interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
86feafeb	288	clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
406a9324 JH	289	clock-names = "pcie", "pcie_bus";
	290	#address-cells = <3>;
	291	#size-cells = <2>;
	292	device_type = "pci";
	293	ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
	294	0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
	295	0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
	296	#interrupt-cells = <1>;
	297	interrupt-map-mask = <0 0 0 0>;
	298	interrupt-map = <0x0 0 &gic 53>;
4b1ced84	299	num-lanes = <4>;
331d7d6a	300	status = "disabled";
406a9324 JH	301	};
	302
	303	pcie@2a0000 {
	304	compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
	305	reg = <0x2a0000 0x1000
	306	0x272000 0x1000
	307	0x271040 0x40>;
	308	interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
86feafeb	309	clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
406a9324 JH	310	clock-names = "pcie", "pcie_bus";
	311	#address-cells = <3>;
	312	#size-cells = <2>;
	313	device_type = "pci";
	314	ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
	315	0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
	316	0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
	317	#interrupt-cells = <1>;
	318	interrupt-map-mask = <0 0 0 0>;
	319	interrupt-map = <0x0 0 &gic 56>;
4b1ced84	320	num-lanes = <4>;
331d7d6a	321	status = "disabled";
406a9324	322	};
1355bbc4	323	};