[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / exynos5440.dtsi

/*
 * SAMSUNG EXYNOS5440 SoC device tree source
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <dt-bindings/clock/exynos5440.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "samsung,exynos5440", "samsung,exynos5";

	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &serial_0;
		serial1 = &serial_1;
		spi0 = &spi_0;
		tmuctrl0 = &tmuctrl_0;
		tmuctrl1 = &tmuctrl_1;
		tmuctrl2 = &tmuctrl_2;
	};

	clock: clock-controller@160000 {
		compatible = "samsung,exynos5440-clock";
		reg = <0x160000 0x1000>;
		#clock-cells = <1>;
	};

	gic: interrupt-controller@2E0000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg =	<0x2E1000 0x1000>,
			<0x2E2000 0x1000>,
			<0x2E4000 0x2000>,
			<0x2E6000 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
		interrupts = <0 52 4>,
			     <0 53 4>,
			     <0 54 4>,
			     <0 55 4>;
	};

	timer {
		compatible = "arm,cortex-a15-timer",
			     "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
		clock-frequency = <50000000>;
	};

	cpufreq@160000 {
		compatible = "samsung,exynos5440-cpufreq";
		reg = <0x160000 0x1000>;
		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
		operating-points = <
				/* KHz	  uV */
				1500000 1100000
				1400000 1075000
				1300000 1050000
				1200000 1025000
				1100000 1000000
				1000000 975000
				900000  950000
				800000  925000
		>;
	};

	serial_0: serial@B0000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0xB0000 0x1000>;
		interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
		clock-names = "uart", "clk_uart_baud0";
	};

	serial_1: serial@C0000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0xC0000 0x1000>;
		interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
		clock-names = "uart", "clk_uart_baud0";
	};

	spi_0: spi@D0000 {
		compatible = "samsung,exynos5440-spi";
		reg = <0xD0000 0x100>;
		interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		samsung,spi-src-clk = <0>;
		num-cs = <1>;
		clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
		clock-names = "spi", "spi_busclk0";
	};

	pin_ctrl: pinctrl@E0000 {
		compatible = "samsung,exynos5440-pinctrl";
		reg = <0xE0000 0x1000>;
		interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
			     <0 38 IRQ_TYPE_LEVEL_HIGH>,
			     <0 39 IRQ_TYPE_LEVEL_HIGH>,
			     <0 40 IRQ_TYPE_LEVEL_HIGH>,
			     <0 41 IRQ_TYPE_LEVEL_HIGH>,
			     <0 42 IRQ_TYPE_LEVEL_HIGH>,
			     <0 43 IRQ_TYPE_LEVEL_HIGH>,
			     <0 44 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;
		#gpio-cells = <2>;

		fan: fan {
			samsung,exynos5440-pin-function = <1>;
		};

		hdd_led0: hdd_led0 {
			samsung,exynos5440-pin-function = <2>;
		};

		hdd_led1: hdd_led1 {
			samsung,exynos5440-pin-function = <3>;
		};

		uart1: uart1 {
			samsung,exynos5440-pin-function = <4>;
		};
	};

	i2c@F0000 {
		compatible = "samsung,exynos5440-i2c";
		reg = <0xF0000 0x1000>;
		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "i2c";
	};

	i2c@100000 {
		compatible = "samsung,exynos5440-i2c";
		reg = <0x100000 0x1000>;
		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "i2c";
	};

	watchdog@110000 {
		compatible = "samsung,s3c2410-wdt";
		reg = <0x110000 0x1000>;
		interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>;
		clock-names = "watchdog";
	};

	gmac: ethernet@00230000 {
		compatible = "snps,dwmac-3.70a";
		reg = <0x00230000 0x8000>;
		interrupt-parent = <&gic>;
		interrupts = <0 31 4>;
		interrupt-names = "macirq";
		phy-mode = "sgmii";
		clocks = <&clock CLK_GMAC0>;
		clock-names = "stmmaceth";
	};

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;
	};

	rtc@130000 {
		compatible = "samsung,s3c6410-rtc";
		reg = <0x130000 0x1000>;
		interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
			     <0 16 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>;
		clock-names = "rtc";
	};

	tmuctrl_0: tmuctrl@160118 {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x160118 0x230>, <0x160368 0x10>;
		interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
		#include "exynos5440-tmu-sensor-conf.dtsi"
	};

	tmuctrl_1: tmuctrl@16011C {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x16011C 0x230>, <0x160368 0x10>;
		interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
		#include "exynos5440-tmu-sensor-conf.dtsi"
	};

	tmuctrl_2: tmuctrl@160120 {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x160120 0x230>, <0x160368 0x10>;
		interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
		#include "exynos5440-tmu-sensor-conf.dtsi"
	};

	thermal-zones {
		cpu0_thermal: cpu0-thermal {
			thermal-sensors = <&tmuctrl_0>;
			#include "exynos5440-trip-points.dtsi"
		};
		cpu1_thermal: cpu1-thermal {
		       thermal-sensors = <&tmuctrl_1>;
		       #include "exynos5440-trip-points.dtsi"
		};
		cpu2_thermal: cpu2-thermal {
		       thermal-sensors = <&tmuctrl_2>;
		       #include "exynos5440-trip-points.dtsi"
		};
	};

	sata@210000 {
		compatible = "snps,exynos5440-ahci";
		reg = <0x210000 0x10000>;
		interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_SATA>;
		clock-names = "sata";
	};

	ohci@220000 {
		compatible = "samsung,exynos5440-ohci";
		reg = <0x220000 0x1000>;
		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_USB>;
		clock-names = "usbhost";
	};

	ehci@221000 {
		compatible = "samsung,exynos5440-ehci";
		reg = <0x221000 0x1000>;
		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_USB>;
		clock-names = "usbhost";
	};

	pcie_0: pcie@290000 {
		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
		reg = <0x290000 0x1000
			0x270000 0x1000
			0x271000 0x40>;
		interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>,
			     <0 21 IRQ_TYPE_LEVEL_HIGH>,
			     <0 22 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
		clock-names = "pcie", "pcie_bus";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
			  0x81000000 0 0	  0x40001000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0x0 0 &gic 53>;
		num-lanes = <4>;
		status = "disabled";
	};

	pcie_1: pcie@2a0000 {
		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
		reg = <0x2a0000 0x1000
			0x272000 0x1000
			0x271040 0x40>;
		interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>,
			     <0 24 IRQ_TYPE_LEVEL_HIGH>,
			     <0 25 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
		clock-names = "pcie", "pcie_bus";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
			  0x81000000 0 0	  0x60001000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0x0 0 &gic 56>;
		num-lanes = <4>;
		status = "disabled";
	};
};
Commit	Line	Data
1355bbc4 KK	1	/*
	2	* SAMSUNG EXYNOS5440 SoC device tree source
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
86feafeb	12	#include <dt-bindings/clock/exynos5440.h>
c473c9a1	13	#include <dt-bindings/interrupt-controller/irq.h>
1355bbc4 KK	14
1355bbc4 KK	15	/ {
8bdb31b4	16	compatible = "samsung,exynos5440", "samsung,exynos5";
1355bbc4 KK	17
1355bbc4 KK	18	interrupt-parent = <&gic>;
12676ee1 JMC	19	#address-cells = <1>;
12676ee1 JMC	20	#size-cells = <1>;
1355bbc4	21
dabd3f9d	22	aliases {
1e64f48e TF	23	serial0 = &serial_0;
1e64f48e TF	24	serial1 = &serial_1;
dabd3f9d	25	spi0 = &spi_0;
5c7311b5 ADK	26	tmuctrl0 = &tmuctrl_0;
	27	tmuctrl1 = &tmuctrl_1;
	28	tmuctrl2 = &tmuctrl_2;
dabd3f9d G	29	};
dabd3f9d G	30
644a79a8	31	clock: clock-controller@160000 {
d8bafc87 TA	32	compatible = "samsung,exynos5440-clock";
	33	reg = <0x160000 0x1000>;
	34	#clock-cells = <1>;
	35	};
	36
0572b725	37	gic: interrupt-controller@2E0000 {
1355bbc4 KK	38	compatible = "arm,cortex-a15-gic";
	39	#interrupt-cells = <3>;
	40	interrupt-controller;
3279dd36 GM	41	reg = <0x2E1000 0x1000>,
	42	<0x2E2000 0x1000>,
	43	<0x2E4000 0x2000>,
	44	<0x2E6000 0x2000>;
	45	interrupts = <1 9 0xf04>;
1355bbc4 KK	46	};
	47
	48	cpus {
f5108e1c KK	49	#address-cells = <1>;
	50	#size-cells = <0>;
	51
1355bbc4	52	cpu@0 {
88e41848	53	device_type = "cpu";
1355bbc4	54	compatible = "arm,cortex-a15";
f5108e1c	55	reg = <0>;
1355bbc4 KK	56	};
1355bbc4 KK	57	cpu@1 {
88e41848	58	device_type = "cpu";
1355bbc4	59	compatible = "arm,cortex-a15";
f5108e1c	60	reg = <1>;
1355bbc4 KK	61	};
1355bbc4 KK	62	cpu@2 {
88e41848	63	device_type = "cpu";
1355bbc4	64	compatible = "arm,cortex-a15";
f5108e1c	65	reg = <2>;
1355bbc4 KK	66	};
1355bbc4 KK	67	cpu@3 {
88e41848	68	device_type = "cpu";
1355bbc4	69	compatible = "arm,cortex-a15";
f5108e1c	70	reg = <3>;
1355bbc4 KK	71	};
	72	};
	73
4c46f51a SP	74	arm-pmu {
	75	compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
	76	interrupts = <0 52 4>,
	77	<0 53 4>,
	78	<0 54 4>,
	79	<0 55 4>;
	80	};
	81
f5108e1c KK	82	timer {
	83	compatible = "arm,cortex-a15-timer",
	84	"arm,armv7-timer";
	85	interrupts = <1 13 0xf08>,
	86	<1 14 0xf08>,
	87	<1 11 0xf08>,
	88	<1 10 0xf08>;
	89	clock-frequency = <50000000>;
	90	};
	91
7f7b8ed0 ADK	92	cpufreq@160000 {
	93	compatible = "samsung,exynos5440-cpufreq";
	94	reg = <0x160000 0x1000>;
c473c9a1	95	interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
7f7b8ed0 ADK	96	operating-points = <
7f7b8ed0 ADK	97	/* KHz uV */
afbbf927 ADK	98	1500000 1100000
	99	1400000 1075000
	100	1300000 1050000
7f7b8ed0	101	1200000 1025000
afbbf927	102	1100000 1000000
7f7b8ed0	103	1000000 975000
afbbf927	104	900000 950000
7f7b8ed0 ADK	105	800000 925000
	106	>;
	107	};
	108
1e64f48e	109	serial_0: serial@B0000 {
1355bbc4 KK	110	compatible = "samsung,exynos4210-uart";
1355bbc4 KK	111	reg = <0xB0000 0x1000>;
c473c9a1	112	interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	113	clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
6a0338c2	114	clock-names = "uart", "clk_uart_baud0";
1355bbc4 KK	115	};
1355bbc4 KK	116
1e64f48e	117	serial_1: serial@C0000 {
1355bbc4 KK	118	compatible = "samsung,exynos4210-uart";
1355bbc4 KK	119	reg = <0xC0000 0x1000>;
c473c9a1	120	interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	121	clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
6a0338c2	122	clock-names = "uart", "clk_uart_baud0";
1355bbc4 KK	123	};
1355bbc4 KK	124
dabd3f9d G	125	spi_0: spi@D0000 {
	126	compatible = "samsung,exynos5440-spi";
	127	reg = <0xD0000 0x100>;
c473c9a1	128	interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
1355bbc4 KK	129	#address-cells = <1>;
1355bbc4 KK	130	#size-cells = <0>;
dabd3f9d G	131	samsung,spi-src-clk = <0>;
dabd3f9d G	132	num-cs = <1>;
86feafeb	133	clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
6a0338c2	134	clock-names = "spi", "spi_busclk0";
1355bbc4 KK	135	};
1355bbc4 KK	136
4185c53f	137	pin_ctrl: pinctrl@E0000 {
f6925432	138	compatible = "samsung,exynos5440-pinctrl";
1355bbc4	139	reg = <0xE0000 0x1000>;
c473c9a1 KK	140	interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
	141	<0 38 IRQ_TYPE_LEVEL_HIGH>,
	142	<0 39 IRQ_TYPE_LEVEL_HIGH>,
	143	<0 40 IRQ_TYPE_LEVEL_HIGH>,
	144	<0 41 IRQ_TYPE_LEVEL_HIGH>,
	145	<0 42 IRQ_TYPE_LEVEL_HIGH>,
	146	<0 43 IRQ_TYPE_LEVEL_HIGH>,
	147	<0 44 IRQ_TYPE_LEVEL_HIGH>;
1355bbc4 KK	148	interrupt-controller;
1355bbc4 KK	149	#interrupt-cells = <2>;
b1ce101b TA	150	#gpio-cells = <2>;
	151
	152	fan: fan {
	153	samsung,exynos5440-pin-function = <1>;
	154	};
	155
	156	hdd_led0: hdd_led0 {
	157	samsung,exynos5440-pin-function = <2>;
	158	};
	159
	160	hdd_led1: hdd_led1 {
	161	samsung,exynos5440-pin-function = <3>;
	162	};
	163
	164	uart1: uart1 {
	165	samsung,exynos5440-pin-function = <4>;
	166	};
1355bbc4 KK	167	};
	168
	169	i2c@F0000 {
49498c56	170	compatible = "samsung,exynos5440-i2c";
1355bbc4	171	reg = <0xF0000 0x1000>;
c473c9a1	172	interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
1355bbc4 KK	173	#address-cells = <1>;
1355bbc4 KK	174	#size-cells = <0>;
86feafeb	175	clocks = <&clock CLK_B_125>;
6a0338c2	176	clock-names = "i2c";
1355bbc4 KK	177	};
	178
	179	i2c@100000 {
49498c56	180	compatible = "samsung,exynos5440-i2c";
1355bbc4	181	reg = <0x100000 0x1000>;
c473c9a1	182	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
1355bbc4 KK	183	#address-cells = <1>;
1355bbc4 KK	184	#size-cells = <0>;
86feafeb	185	clocks = <&clock CLK_B_125>;
6a0338c2	186	clock-names = "i2c";
1355bbc4 KK	187	};
1355bbc4 KK	188
64f5d1eb	189	watchdog@110000 {
1355bbc4 KK	190	compatible = "samsung,s3c2410-wdt";
1355bbc4 KK	191	reg = <0x110000 0x1000>;
c473c9a1	192	interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	193	clocks = <&clock CLK_B_125>;
6a0338c2	194	clock-names = "watchdog";
1355bbc4 KK	195	};
1355bbc4 KK	196
c038c4d8 BA	197	gmac: ethernet@00230000 {
	198	compatible = "snps,dwmac-3.70a";
	199	reg = <0x00230000 0x8000>;
	200	interrupt-parent = <&gic>;
	201	interrupts = <0 31 4>;
	202	interrupt-names = "macirq";
	203	phy-mode = "sgmii";
86feafeb	204	clocks = <&clock CLK_GMAC0>;
c038c4d8 BA	205	clock-names = "stmmaceth";
	206	};
	207
1355bbc4 KK	208	amba {
	209	#address-cells = <1>;
	210	#size-cells = <1>;
2ef7d5f3	211	compatible = "simple-bus";
1355bbc4 KK	212	interrupt-parent = <&gic>;
1355bbc4 KK	213	ranges;
1355bbc4 KK	214	};
1355bbc4 KK	215
4185c53f	216	rtc@130000 {
1355bbc4 KK	217	compatible = "samsung,s3c6410-rtc";
1355bbc4 KK	218	reg = <0x130000 0x1000>;
c473c9a1 KK	219	interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
c473c9a1 KK	220	<0 16 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	221	clocks = <&clock CLK_B_125>;
6a0338c2	222	clock-names = "rtc";
1355bbc4	223	};
1a12f52e	224
5c7311b5 ADK	225	tmuctrl_0: tmuctrl@160118 {
	226	compatible = "samsung,exynos5440-tmu";
	227	reg = <0x160118 0x230>, <0x160368 0x10>;
c473c9a1	228	interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	229	clocks = <&clock CLK_B_125>;
5c7311b5	230	clock-names = "tmu_apbif";
9843a223	231	#include "exynos5440-tmu-sensor-conf.dtsi"
5c7311b5 ADK	232	};
	233
	234	tmuctrl_1: tmuctrl@16011C {
	235	compatible = "samsung,exynos5440-tmu";
	236	reg = <0x16011C 0x230>, <0x160368 0x10>;
c473c9a1	237	interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	238	clocks = <&clock CLK_B_125>;
5c7311b5	239	clock-names = "tmu_apbif";
9843a223	240	#include "exynos5440-tmu-sensor-conf.dtsi"
5c7311b5 ADK	241	};
	242
	243	tmuctrl_2: tmuctrl@160120 {
	244	compatible = "samsung,exynos5440-tmu";
	245	reg = <0x160120 0x230>, <0x160368 0x10>;
c473c9a1	246	interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	247	clocks = <&clock CLK_B_125>;
5c7311b5	248	clock-names = "tmu_apbif";
9843a223 LM	249	#include "exynos5440-tmu-sensor-conf.dtsi"
	250	};
	251
	252	thermal-zones {
	253	cpu0_thermal: cpu0-thermal {
	254	thermal-sensors = <&tmuctrl_0>;
	255	#include "exynos5440-trip-points.dtsi"
	256	};
	257	cpu1_thermal: cpu1-thermal {
	258	thermal-sensors = <&tmuctrl_1>;
	259	#include "exynos5440-trip-points.dtsi"
	260	};
	261	cpu2_thermal: cpu2-thermal {
	262	thermal-sensors = <&tmuctrl_2>;
	263	#include "exynos5440-trip-points.dtsi"
	264	};
5c7311b5 ADK	265	};
5c7311b5 ADK	266
1a12f52e G	267	sata@210000 {
	268	compatible = "snps,exynos5440-ahci";
	269	reg = <0x210000 0x10000>;
c473c9a1	270	interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	271	clocks = <&clock CLK_SATA>;
1a12f52e G	272	clock-names = "sata";
	273	};
	274
a3808905 TA	275	ohci@220000 {
	276	compatible = "samsung,exynos5440-ohci";
	277	reg = <0x220000 0x1000>;
c473c9a1	278	interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	279	clocks = <&clock CLK_USB>;
a3808905 TA	280	clock-names = "usbhost";
	281	};
	282
	283	ehci@221000 {
	284	compatible = "samsung,exynos5440-ehci";
	285	reg = <0x221000 0x1000>;
c473c9a1	286	interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	287	clocks = <&clock CLK_USB>;
a3808905	288	clock-names = "usbhost";
1355bbc4	289	};
406a9324	290
7c23e7e1	291	pcie_0: pcie@290000 {
406a9324 JH	292	compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
	293	reg = <0x290000 0x1000
	294	0x270000 0x1000
	295	0x271000 0x40>;
c473c9a1 KK	296	interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>,
	297	<0 21 IRQ_TYPE_LEVEL_HIGH>,
	298	<0 22 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	299	clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
406a9324 JH	300	clock-names = "pcie", "pcie_bus";
	301	#address-cells = <3>;
	302	#size-cells = <2>;
	303	device_type = "pci";
	304	ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
	305	0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
	306	0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
	307	#interrupt-cells = <1>;
	308	interrupt-map-mask = <0 0 0 0>;
	309	interrupt-map = <0x0 0 &gic 53>;
4b1ced84	310	num-lanes = <4>;
331d7d6a	311	status = "disabled";
406a9324 JH	312	};
406a9324 JH	313
7c23e7e1	314	pcie_1: pcie@2a0000 {
406a9324 JH	315	compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
	316	reg = <0x2a0000 0x1000
	317	0x272000 0x1000
	318	0x271040 0x40>;
c473c9a1 KK	319	interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>,
	320	<0 24 IRQ_TYPE_LEVEL_HIGH>,
	321	<0 25 IRQ_TYPE_LEVEL_HIGH>;
86feafeb	322	clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
406a9324 JH	323	clock-names = "pcie", "pcie_bus";
	324	#address-cells = <3>;
	325	#size-cells = <2>;
	326	device_type = "pci";
	327	ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
	328	0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
	329	0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
	330	#interrupt-cells = <1>;
	331	interrupt-map-mask = <0 0 0 0>;
	332	interrupt-map = <0x0 0 &gic 56>;
4b1ced84	333	num-lanes = <4>;
331d7d6a	334	status = "disabled";
406a9324	335	};
1355bbc4	336	};