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1 | /* |
2 | * SAMSUNG EXYNOS5440 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | /include/ "skeleton.dtsi" | |
13 | ||
14 | / { | |
15 | compatible = "samsung,exynos5440"; | |
16 | ||
17 | interrupt-parent = <&gic>; | |
18 | ||
19 | gic:interrupt-controller@2E0000 { | |
20 | compatible = "arm,cortex-a15-gic"; | |
21 | #interrupt-cells = <3>; | |
22 | interrupt-controller; | |
23 | reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>; | |
24 | }; | |
25 | ||
26 | cpus { | |
27 | cpu@0 { | |
28 | compatible = "arm,cortex-a15"; | |
29 | timer { | |
30 | compatible = "arm,armv7-timer"; | |
31 | interrupts = <1 13 0xf08>; | |
32 | clock-frequency = <1000000>; | |
33 | }; | |
34 | }; | |
35 | cpu@1 { | |
36 | compatible = "arm,cortex-a15"; | |
37 | timer { | |
38 | compatible = "arm,armv7-timer"; | |
39 | interrupts = <1 14 0xf08>; | |
40 | clock-frequency = <1000000>; | |
41 | }; | |
42 | }; | |
43 | cpu@2 { | |
44 | compatible = "arm,cortex-a15"; | |
45 | timer { | |
46 | compatible = "arm,armv7-timer"; | |
47 | interrupts = <1 14 0xf08>; | |
48 | clock-frequency = <1000000>; | |
49 | }; | |
50 | }; | |
51 | cpu@3 { | |
52 | compatible = "arm,cortex-a15"; | |
53 | timer { | |
54 | compatible = "arm,armv7-timer"; | |
55 | interrupts = <1 14 0xf08>; | |
56 | clock-frequency = <1000000>; | |
57 | }; | |
58 | }; | |
59 | }; | |
60 | ||
61 | common { | |
62 | compatible = "samsung,exynos5440"; | |
63 | ||
64 | }; | |
65 | ||
66 | serial@B0000 { | |
67 | compatible = "samsung,exynos4210-uart"; | |
68 | reg = <0xB0000 0x1000>; | |
69 | interrupts = <0 2 0>; | |
70 | }; | |
71 | ||
72 | serial@C0000 { | |
73 | compatible = "samsung,exynos4210-uart"; | |
74 | reg = <0xC0000 0x1000>; | |
75 | interrupts = <0 3 0>; | |
76 | }; | |
77 | ||
78 | spi { | |
79 | compatible = "samsung,exynos4210-spi"; | |
80 | reg = <0xD0000 0x1000>; | |
81 | interrupts = <0 4 0>; | |
82 | tx-dma-channel = <&pdma0 5>; /* preliminary */ | |
83 | rx-dma-channel = <&pdma0 4>; /* preliminary */ | |
84 | #address-cells = <1>; | |
85 | #size-cells = <0>; | |
86 | }; | |
87 | ||
88 | pinctrl { | |
89 | compatible = "samsung,pinctrl-exynos5440"; | |
90 | reg = <0xE0000 0x1000>; | |
91 | interrupt-controller; | |
92 | #interrupt-cells = <2>; | |
93 | }; | |
94 | ||
95 | i2c@F0000 { | |
96 | compatible = "samsung,s3c2440-i2c"; | |
97 | reg = <0xF0000 0x1000>; | |
98 | interrupts = <0 5 0>; | |
99 | #address-cells = <1>; | |
100 | #size-cells = <0>; | |
101 | }; | |
102 | ||
103 | i2c@100000 { | |
104 | compatible = "samsung,s3c2440-i2c"; | |
105 | reg = <0x100000 0x1000>; | |
106 | interrupts = <0 6 0>; | |
107 | #address-cells = <1>; | |
108 | #size-cells = <0>; | |
109 | }; | |
110 | ||
111 | watchdog { | |
112 | compatible = "samsung,s3c2410-wdt"; | |
113 | reg = <0x110000 0x1000>; | |
114 | interrupts = <0 1 0>; | |
115 | }; | |
116 | ||
117 | amba { | |
118 | #address-cells = <1>; | |
119 | #size-cells = <1>; | |
120 | compatible = "arm,amba-bus"; | |
121 | interrupt-parent = <&gic>; | |
122 | ranges; | |
123 | ||
124 | pdma0: pdma@121A0000 { | |
125 | compatible = "arm,pl330", "arm,primecell"; | |
126 | reg = <0x120000 0x1000>; | |
127 | interrupts = <0 34 0>; | |
128 | }; | |
129 | ||
130 | pdma1: pdma@121B0000 { | |
131 | compatible = "arm,pl330", "arm,primecell"; | |
132 | reg = <0x121000 0x1000>; | |
133 | interrupts = <0 35 0>; | |
134 | }; | |
135 | }; | |
136 | ||
137 | rtc { | |
138 | compatible = "samsung,s3c6410-rtc"; | |
139 | reg = <0x130000 0x1000>; | |
140 | interrupts = <0 16 0>, <0 17 0>; | |
141 | }; | |
142 | }; |