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Commit | Line | Data |
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22789ae3 LW |
1 | /* |
2 | * Device Tree file for D-Link DIR-685 Xtreme N Storage Router | |
3 | */ | |
4 | ||
5 | /dts-v1/; | |
6 | ||
7 | #include "gemini.dtsi" | |
8 | #include <dt-bindings/input/input.h> | |
9 | ||
10 | / { | |
11 | model = "D-Link DIR-685 Xtreme N Storage Router"; | |
12 | compatible = "dlink,dir-685", "cortina,gemini"; | |
13 | #address-cells = <1>; | |
14 | #size-cells = <1>; | |
15 | ||
e7c88159 | 16 | memory@0 { |
22789ae3 LW |
17 | /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */ |
18 | device_type = "memory"; | |
19 | reg = <0x00000000 0x8000000>; | |
20 | }; | |
21 | ||
22 | chosen { | |
0d6ce772 LW |
23 | bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait"; |
24 | stdout-path = "uart0:19200n8"; | |
22789ae3 LW |
25 | }; |
26 | ||
27 | gpio_keys { | |
28 | compatible = "gpio-keys"; | |
e7c88159 | 29 | |
22789ae3 | 30 | button-esc { |
c0b20bac | 31 | debounce-interval = <50>; |
22789ae3 LW |
32 | wakeup-source; |
33 | linux,code = <KEY_ESC>; | |
34 | label = "reset"; | |
f328c2ea | 35 | /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */ |
22789ae3 LW |
36 | gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; |
37 | }; | |
38 | button-eject { | |
c0b20bac | 39 | debounce-interval = <50>; |
22789ae3 LW |
40 | wakeup-source; |
41 | linux,code = <KEY_EJECTCD>; | |
42 | label = "unmount"; | |
f328c2ea | 43 | /* Collides with LPC LFRAME, UART RTS, SSP TXD */ |
22789ae3 LW |
44 | gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; |
45 | }; | |
46 | }; | |
47 | ||
ea6f23f5 LW |
48 | vdisp: regulator { |
49 | compatible = "regulator-fixed"; | |
50 | regulator-name = "display-power"; | |
51 | regulator-min-microvolt = <3600000>; | |
52 | regulator-max-microvolt = <3600000>; | |
53 | /* Collides with LCD E */ | |
54 | gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; | |
55 | enable-active-high; | |
56 | }; | |
57 | ||
58 | spi { | |
59 | compatible = "spi-gpio"; | |
60 | #address-cells = <1>; | |
61 | #size-cells = <0>; | |
62 | ||
63 | /* Collides with IDE pins, that's cool (we do not use them) */ | |
64 | gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>; | |
65 | gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>; | |
66 | gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>; | |
67 | /* Collides with pflash CE1, not so cool */ | |
68 | cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; | |
69 | num-chipselects = <1>; | |
70 | ||
71 | panel: display@0 { | |
72 | compatible = "dlink,dir-685-panel", "ilitek,ili9322"; | |
73 | reg = <0>; | |
74 | /* 50 ns min period = 20 MHz */ | |
75 | spi-max-frequency = <20000000>; | |
76 | spi-cpol; /* Clock active low */ | |
77 | vcc-supply = <&vdisp>; | |
78 | iovcc-supply = <&vdisp>; | |
79 | vci-supply = <&vdisp>; | |
80 | ||
81 | port { | |
82 | panel_in: endpoint { | |
83 | remote-endpoint = <&display_out>; | |
84 | }; | |
85 | }; | |
86 | }; | |
87 | }; | |
88 | ||
22789ae3 LW |
89 | leds { |
90 | compatible = "gpio-leds"; | |
91 | led-wps { | |
92 | label = "dir685:blue:WPS"; | |
f328c2ea | 93 | /* Collides with ICE */ |
22789ae3 LW |
94 | gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; |
95 | default-state = "on"; | |
96 | linux,default-trigger = "heartbeat"; | |
97 | }; | |
98 | /* | |
99 | * These two LEDs are on the side of the device. | |
100 | * For electrical reasons, both LEDs cannot be active | |
8cb24590 | 101 | * at the same time so only blue or orange can be on at |
22789ae3 LW |
102 | * one time. Enabling both makes the LED go dark. |
103 | * The LEDs both sit inside the unmount button and the | |
104 | * label on the case says "unmount". | |
105 | */ | |
106 | led-blue-hd { | |
107 | label = "dir685:blue:HD"; | |
f328c2ea | 108 | /* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */ |
22789ae3 LW |
109 | gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; |
110 | default-state = "off"; | |
8cb24590 | 111 | linux,default-trigger = "disk-read"; |
22789ae3 LW |
112 | }; |
113 | led-orange-hd { | |
114 | label = "dir685:orange:HD"; | |
f328c2ea | 115 | /* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */ |
22789ae3 LW |
116 | gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; |
117 | default-state = "off"; | |
8cb24590 | 118 | linux,default-trigger = "disk-write"; |
22789ae3 LW |
119 | }; |
120 | }; | |
121 | ||
122 | /* | |
123 | * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM. | |
124 | * Since the platform has no temperature sensor, this is controlled | |
125 | * from userspace by using the hard disks S.M.A.R.T. temperature | |
126 | * sensor. It is turned on when the temperature exceeds 46 degrees | |
127 | * and turned off when the temperatures goes below 41 degrees | |
128 | * (celsius). | |
129 | */ | |
130 | gpio-fan { | |
131 | compatible = "gpio-fan"; | |
f328c2ea | 132 | /* Collides with IDE */ |
22789ae3 LW |
133 | gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; |
134 | gpio-fan,speed-map = <0 0>, <10000 1>; | |
135 | #cooling-cells = <2>; | |
136 | }; | |
137 | ||
138 | /* | |
139 | * The touchpad input is connected to a GPIO bit-banged | |
140 | * I2C bus. | |
141 | */ | |
142 | gpio-i2c { | |
143 | compatible = "i2c-gpio"; | |
f328c2ea | 144 | /* Collides with ICE */ |
8632a661 LW |
145 | sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; |
146 | scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; | |
22789ae3 LW |
147 | #address-cells = <1>; |
148 | #size-cells = <0>; | |
149 | ||
150 | touchkeys@26 { | |
151 | compatible = "dlink,dir685-touchkeys"; | |
152 | reg = <0x26>; | |
153 | interrupt-parent = <&gpio0>; | |
f328c2ea | 154 | /* Collides with NAND flash */ |
22789ae3 LW |
155 | interrupts = <17 IRQ_TYPE_EDGE_FALLING>; |
156 | }; | |
157 | }; | |
158 | ||
22a001e8 LW |
159 | /* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */ |
160 | switch { | |
161 | compatible = "realtek,rtl8366rb"; | |
162 | /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ | |
163 | mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; | |
164 | mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; | |
165 | reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; | |
166 | realtek,disable-leds; | |
167 | ||
168 | switch_intc: interrupt-controller { | |
169 | /* GPIO 15 provides the interrupt */ | |
170 | interrupt-parent = <&gpio0>; | |
171 | interrupts = <15 IRQ_TYPE_LEVEL_LOW>; | |
172 | interrupt-controller; | |
173 | #address-cells = <0>; | |
174 | #interrupt-cells = <1>; | |
175 | }; | |
176 | ||
177 | ports { | |
178 | #address-cells = <1>; | |
179 | #size-cells = <0>; | |
180 | ||
181 | port@0 { | |
182 | reg = <0>; | |
183 | label = "lan0"; | |
184 | phy-handle = <&phy0>; | |
185 | }; | |
186 | port@1 { | |
187 | reg = <1>; | |
188 | label = "lan1"; | |
189 | phy-handle = <&phy1>; | |
190 | }; | |
191 | port@2 { | |
192 | reg = <2>; | |
193 | label = "lan2"; | |
194 | phy-handle = <&phy2>; | |
195 | }; | |
196 | port@3 { | |
197 | reg = <3>; | |
198 | label = "lan3"; | |
199 | phy-handle = <&phy3>; | |
200 | }; | |
201 | port@4 { | |
202 | reg = <4>; | |
203 | label = "wan"; | |
204 | phy-handle = <&phy4>; | |
205 | }; | |
206 | rtl8366rb_cpu_port: port@5 { | |
207 | reg = <5>; | |
208 | label = "cpu"; | |
209 | ethernet = <&gmac0>; | |
210 | phy-mode = "rgmii"; | |
211 | fixed-link { | |
212 | speed = <1000>; | |
213 | full-duplex; | |
214 | pause; | |
215 | }; | |
216 | }; | |
217 | ||
218 | }; | |
219 | ||
220 | mdio { | |
221 | compatible = "realtek,smi-mdio"; | |
222 | #address-cells = <1>; | |
223 | #size-cells = <0>; | |
224 | ||
225 | phy0: phy@0 { | |
226 | reg = <0>; | |
227 | interrupt-parent = <&switch_intc>; | |
228 | interrupts = <0>; | |
229 | }; | |
230 | phy1: phy@1 { | |
231 | reg = <1>; | |
232 | interrupt-parent = <&switch_intc>; | |
233 | interrupts = <1>; | |
234 | }; | |
235 | phy2: phy@2 { | |
236 | reg = <2>; | |
237 | interrupt-parent = <&switch_intc>; | |
238 | interrupts = <2>; | |
239 | }; | |
240 | phy3: phy@3 { | |
241 | reg = <3>; | |
242 | interrupt-parent = <&switch_intc>; | |
243 | interrupts = <3>; | |
244 | }; | |
245 | phy4: phy@4 { | |
246 | reg = <4>; | |
247 | interrupt-parent = <&switch_intc>; | |
248 | interrupts = <12>; | |
249 | }; | |
250 | }; | |
251 | }; | |
252 | ||
22789ae3 LW |
253 | soc { |
254 | flash@30000000 { | |
ea6f23f5 LW |
255 | /* |
256 | * Flash access is by default disabled, because it | |
257 | * collides with the Chip Enable signal for the display | |
258 | * panel, that reuse the parallel flash Chip Select 1 | |
259 | * (CS1). Enabling flash makes graphics stop working. | |
260 | * | |
261 | * We might be able to hack around this by letting | |
262 | * GPIO poke around in the flash controller registers. | |
263 | */ | |
264 | /* status = "okay"; */ | |
22789ae3 LW |
265 | /* 32MB of flash */ |
266 | reg = <0x30000000 0x02000000>; | |
267 | ||
268 | /* | |
269 | * This "RedBoot" is the Storlink derivative. | |
270 | */ | |
271 | partition@0 { | |
272 | label = "RedBoot"; | |
273 | reg = <0x00000000 0x00040000>; | |
274 | read-only; | |
275 | }; | |
276 | /* | |
277 | * Between the boot loader and the rootfs is the kernel | |
278 | * in a custom Storlink format flashed from the boot | |
279 | * menu. The rootfs is in squashfs format. | |
280 | */ | |
281 | partition@1800c0 { | |
282 | label = "rootfs"; | |
283 | reg = <0x001800c0 0x01dbff40>; | |
284 | read-only; | |
285 | }; | |
286 | partition@1f40000 { | |
287 | label = "upgrade"; | |
288 | reg = <0x01f40000 0x00040000>; | |
289 | read-only; | |
290 | }; | |
291 | partition@1f80000 { | |
292 | label = "rgdb"; | |
293 | reg = <0x01f80000 0x00040000>; | |
294 | read-only; | |
295 | }; | |
296 | /* | |
297 | * This partition contains MAC addresses for WAN, | |
298 | * WLAN and LAN, and the country code (for wireless | |
299 | * I guess). | |
300 | */ | |
301 | partition@1fc0000 { | |
302 | label = "nvram"; | |
303 | reg = <0x01fc0000 0x00020000>; | |
304 | read-only; | |
305 | }; | |
306 | partition@1fe0000 { | |
307 | label = "LangPack"; | |
308 | reg = <0x01fe0000 0x00020000>; | |
309 | read-only; | |
310 | }; | |
311 | }; | |
312 | ||
f328c2ea LW |
313 | syscon: syscon@40000000 { |
314 | pinctrl { | |
315 | /* | |
316 | * gpio0bgrp cover line 5, 6 used by TK I2C | |
317 | * gpio0bgrp cover line 7 used by WPS LED | |
318 | * gpio0cgrp cover line 8, 13 used by keys | |
319 | * and 11, 12 used by the HD LEDs | |
22a001e8 LW |
320 | * and line 14, 15 used by RTL8366 |
321 | * RESET and phy ready | |
f328c2ea LW |
322 | * gpio0egrp cover line 16 used by VDISP |
323 | * gpio0fgrp cover line 17 used by TK IRQ | |
324 | * gpio0ggrp cover line 20 used by panel CS | |
22a001e8 | 325 | * gpio0hgrp cover line 21,22 used by RTL8366RB MDIO |
f328c2ea LW |
326 | */ |
327 | gpio0_default_pins: pinctrl-gpio0 { | |
328 | mux { | |
329 | function = "gpio0"; | |
330 | groups = "gpio0bgrp", | |
331 | "gpio0cgrp", | |
332 | "gpio0egrp", | |
333 | "gpio0fgrp", | |
334 | "gpio0ggrp", | |
335 | "gpio0hgrp"; | |
336 | }; | |
337 | }; | |
338 | /* | |
339 | * gpio1bgrp cover line 5,8,7 used by panel SPI | |
340 | * also line 6 used by the fan | |
341 | * | |
342 | */ | |
343 | gpio1_default_pins: pinctrl-gpio1 { | |
344 | mux { | |
345 | function = "gpio1"; | |
346 | groups = "gpio1bgrp"; | |
347 | }; | |
348 | }; | |
22a001e8 LW |
349 | pinctrl-gmii { |
350 | mux { | |
351 | function = "gmii"; | |
352 | groups = "gmii_gmac0_grp"; | |
353 | }; | |
354 | conf0 { | |
355 | pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV", | |
356 | "Y7 GMAC0 RXC", "Y11 GMAC1 RXC", | |
357 | "T8 GMAC0 TXEN", "W11 GMAC1 TXEN", | |
358 | "U8 GMAC0 TXC", "V11 GMAC1 TXC", | |
359 | "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", | |
360 | "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", | |
361 | "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", | |
362 | "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", | |
363 | "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", | |
364 | "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", | |
365 | "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", | |
366 | "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; | |
367 | skew-delay = <7>; | |
368 | }; | |
369 | /* Set up drive strength on GMAC0 to 16 mA */ | |
370 | conf1 { | |
371 | groups = "gmii_gmac0_grp"; | |
372 | drive-strength = <16>; | |
373 | }; | |
374 | }; | |
f328c2ea LW |
375 | }; |
376 | }; | |
377 | ||
22789ae3 LW |
378 | sata: sata@46000000 { |
379 | cortina,gemini-ata-muxmode = <0>; | |
380 | cortina,gemini-enable-sata-bridge; | |
381 | status = "okay"; | |
382 | }; | |
383 | ||
f328c2ea LW |
384 | gpio0: gpio@4d000000 { |
385 | pinctrl-names = "default"; | |
386 | pinctrl-0 = <&gpio0_default_pins>; | |
387 | }; | |
388 | ||
389 | gpio1: gpio@4e000000 { | |
390 | pinctrl-names = "default"; | |
391 | pinctrl-0 = <&gpio1_default_pins>; | |
392 | }; | |
393 | ||
22789ae3 LW |
394 | pci@50000000 { |
395 | status = "okay"; | |
396 | interrupt-map-mask = <0xf800 0 0 7>; | |
397 | interrupt-map = | |
398 | <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ | |
399 | <0x4800 0 0 2 &pci_intc 1>, | |
400 | <0x4800 0 0 3 &pci_intc 2>, | |
401 | <0x4800 0 0 4 &pci_intc 3>, | |
402 | <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ | |
403 | <0x5000 0 0 2 &pci_intc 2>, | |
404 | <0x5000 0 0 3 &pci_intc 3>, | |
405 | <0x5000 0 0 4 &pci_intc 0>, | |
406 | <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ | |
407 | <0x5800 0 0 2 &pci_intc 3>, | |
408 | <0x5800 0 0 3 &pci_intc 0>, | |
409 | <0x5800 0 0 4 &pci_intc 1>, | |
410 | <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ | |
411 | <0x6000 0 0 2 &pci_intc 0>, | |
412 | <0x6000 0 0 3 &pci_intc 1>, | |
413 | <0x6000 0 0 4 &pci_intc 2>; | |
414 | }; | |
415 | ||
22a001e8 LW |
416 | ethernet@60000000 { |
417 | status = "okay"; | |
418 | ||
419 | ethernet-port@0 { | |
420 | phy-mode = "rgmii"; | |
421 | fixed-link { | |
422 | speed = <1000>; | |
423 | full-duplex; | |
424 | pause; | |
425 | }; | |
426 | }; | |
427 | ethernet-port@1 { | |
428 | /* Not used in this platform */ | |
429 | }; | |
430 | }; | |
431 | ||
22789ae3 LW |
432 | ata@63000000 { |
433 | status = "okay"; | |
434 | }; | |
ea6f23f5 LW |
435 | |
436 | display-controller@6a000000 { | |
437 | status = "okay"; | |
438 | ||
439 | port@0 { | |
440 | reg = <0>; | |
441 | display_out: endpoint { | |
442 | remote-endpoint = <&panel_in>; | |
443 | }; | |
444 | }; | |
445 | }; | |
22789ae3 LW |
446 | }; |
447 | }; |