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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
9be0d7f8 LW |
2 | /* |
3 | * Device Tree file for Cortina systems Gemini SoC | |
4 | */ | |
5 | ||
6 | /include/ "skeleton.dtsi" | |
7 | ||
8 | #include <dt-bindings/interrupt-controller/irq.h> | |
5896a4d8 LW |
9 | #include <dt-bindings/clock/cortina,gemini-clock.h> |
10 | #include <dt-bindings/reset/cortina,gemini-reset.h> | |
9be0d7f8 LW |
11 | #include <dt-bindings/gpio/gpio.h> |
12 | ||
13 | / { | |
14 | soc { | |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | ranges; | |
18 | compatible = "simple-bus"; | |
19 | interrupt-parent = <&intcon>; | |
20 | ||
21 | flash@30000000 { | |
22 | compatible = "cortina,gemini-flash", "cfi-flash"; | |
23 | syscon = <&syscon>; | |
f328c2ea LW |
24 | pinctrl-names = "default"; |
25 | pinctrl-0 = <&pflash_default_pins>; | |
9be0d7f8 LW |
26 | bank-width = <2>; |
27 | #address-cells = <1>; | |
28 | #size-cells = <1>; | |
29 | status = "disabled"; | |
30 | }; | |
31 | ||
32 | syscon: syscon@40000000 { | |
3863c528 LW |
33 | compatible = "cortina,gemini-syscon", |
34 | "syscon", "simple-mfd"; | |
9be0d7f8 | 35 | reg = <0x40000000 0x1000>; |
664ed4e2 | 36 | #clock-cells = <1>; |
3863c528 | 37 | #reset-cells = <1>; |
9be0d7f8 LW |
38 | |
39 | syscon-reboot { | |
40 | compatible = "syscon-reboot"; | |
41 | regmap = <&syscon>; | |
42 | /* GLOBAL_RESET register */ | |
43 | offset = <0x0c>; | |
44 | /* RESET_GLOBAL | RESET_CPU1 */ | |
45 | mask = <0xC0000000>; | |
46 | }; | |
f328c2ea LW |
47 | |
48 | pinctrl { | |
49 | compatible = "cortina,gemini-pinctrl"; | |
50 | regmap = <&syscon>; | |
51 | /* Hog the DRAM pins */ | |
52 | pinctrl-names = "default"; | |
53 | pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, | |
54 | <&vcontrol_default_pins>; | |
55 | ||
56 | dram_default_pins: pinctrl-dram { | |
57 | mux { | |
58 | function = "dram"; | |
59 | groups = "dramgrp"; | |
60 | }; | |
61 | }; | |
62 | rtc_default_pins: pinctrl-rtc { | |
63 | mux { | |
64 | function = "rtc"; | |
65 | groups = "rtcgrp"; | |
66 | }; | |
67 | }; | |
68 | power_default_pins: pinctrl-power { | |
69 | mux { | |
70 | function = "power"; | |
71 | groups = "powergrp"; | |
72 | }; | |
73 | }; | |
74 | cir_default_pins: pinctrl-cir { | |
75 | mux { | |
76 | function = "cir"; | |
77 | groups = "cirgrp"; | |
78 | }; | |
79 | }; | |
80 | system_default_pins: pinctrl-system { | |
81 | mux { | |
82 | function = "system"; | |
83 | groups = "systemgrp"; | |
84 | }; | |
85 | }; | |
86 | vcontrol_default_pins: pinctrl-vcontrol { | |
87 | mux { | |
88 | function = "vcontrol"; | |
89 | groups = "vcontrolgrp"; | |
90 | }; | |
91 | }; | |
92 | ice_default_pins: pinctrl-ice { | |
93 | mux { | |
94 | function = "ice"; | |
95 | groups = "icegrp"; | |
96 | }; | |
97 | }; | |
98 | uart_default_pins: pinctrl-uart { | |
99 | mux { | |
100 | function = "uart"; | |
101 | groups = "uartrxtxgrp"; | |
102 | }; | |
103 | }; | |
104 | pflash_default_pins: pinctrl-pflash { | |
105 | mux { | |
106 | function = "pflash"; | |
107 | groups = "pflashgrp"; | |
108 | }; | |
109 | }; | |
110 | usb_default_pins: pinctrl-usb { | |
111 | mux { | |
112 | function = "usb"; | |
113 | groups = "usbgrp"; | |
114 | }; | |
115 | }; | |
116 | gmii_default_pins: pinctrl-gmii { | |
117 | mux { | |
118 | function = "gmii"; | |
119 | groups = "gmiigrp"; | |
120 | }; | |
121 | }; | |
122 | pci_default_pins: pinctrl-pci { | |
123 | mux { | |
124 | function = "pci"; | |
125 | groups = "pcigrp"; | |
126 | }; | |
127 | }; | |
128 | sata_default_pins: pinctrl-sata { | |
129 | mux { | |
130 | function = "sata"; | |
131 | groups = "satagrp"; | |
132 | }; | |
133 | }; | |
134 | /* Activate both groups of pins for this state */ | |
135 | sata_and_ide_pins: pinctrl-sata-ide { | |
136 | mux0 { | |
137 | function = "sata"; | |
138 | groups = "satagrp"; | |
139 | }; | |
140 | mux1 { | |
141 | function = "ide"; | |
142 | groups = "idegrp"; | |
143 | }; | |
144 | }; | |
145 | }; | |
9be0d7f8 LW |
146 | }; |
147 | ||
6ae4d211 | 148 | watchdog@41000000 { |
8633e4f2 | 149 | compatible = "cortina,gemini-watchdog", "faraday,ftwdt010"; |
6ae4d211 LW |
150 | reg = <0x41000000 0x1000>; |
151 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; | |
5896a4d8 LW |
152 | resets = <&syscon GEMINI_RESET_WDOG>; |
153 | clocks = <&syscon GEMINI_CLK_APB>; | |
8633e4f2 | 154 | clock-names = "PCLK"; |
6ae4d211 LW |
155 | }; |
156 | ||
9be0d7f8 LW |
157 | uart0: serial@42000000 { |
158 | compatible = "ns16550a"; | |
159 | reg = <0x42000000 0x100>; | |
5896a4d8 LW |
160 | resets = <&syscon GEMINI_RESET_UART>; |
161 | clocks = <&syscon GEMINI_CLK_UART>; | |
9be0d7f8 | 162 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; |
f328c2ea LW |
163 | pinctrl-names = "default"; |
164 | pinctrl-0 = <&uart_default_pins>; | |
9be0d7f8 LW |
165 | reg-shift = <2>; |
166 | }; | |
167 | ||
168 | timer@43000000 { | |
664ed4e2 | 169 | compatible = "faraday,fttmr010"; |
9be0d7f8 LW |
170 | reg = <0x43000000 0x1000>; |
171 | interrupt-parent = <&intcon>; | |
172 | interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ | |
173 | <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ | |
174 | <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ | |
5896a4d8 | 175 | resets = <&syscon GEMINI_RESET_TIMER>; |
664ed4e2 | 176 | /* APB clock or RTC clock */ |
5896a4d8 | 177 | clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; |
664ed4e2 | 178 | clock-names = "PCLK", "EXTCLK"; |
9be0d7f8 LW |
179 | syscon = <&syscon>; |
180 | }; | |
181 | ||
182 | rtc@45000000 { | |
183 | compatible = "cortina,gemini-rtc"; | |
184 | reg = <0x45000000 0x100>; | |
185 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; | |
5896a4d8 LW |
186 | resets = <&syscon GEMINI_RESET_RTC>; |
187 | clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; | |
664ed4e2 | 188 | clock-names = "PCLK", "EXTCLK"; |
f328c2ea LW |
189 | pinctrl-names = "default"; |
190 | pinctrl-0 = <&rtc_default_pins>; | |
9be0d7f8 LW |
191 | }; |
192 | ||
0d7a2c35 LW |
193 | sata: sata@46000000 { |
194 | compatible = "cortina,gemini-sata-bridge"; | |
195 | reg = <0x46000000 0x100>; | |
5896a4d8 LW |
196 | resets = <&syscon GEMINI_RESET_SATA0>, |
197 | <&syscon GEMINI_RESET_SATA1>; | |
0d7a2c35 | 198 | reset-names = "sata0", "sata1"; |
5896a4d8 LW |
199 | clocks = <&syscon GEMINI_CLK_GATE_SATA0>, |
200 | <&syscon GEMINI_CLK_GATE_SATA1>; | |
0d7a2c35 | 201 | clock-names = "SATA0_PCLK", "SATA1_PCLK"; |
f328c2ea LW |
202 | /* |
203 | * This defines the special "ide" state that needs | |
204 | * to be explicitly enabled to enable the IDE pins, | |
205 | * as these pins are normally used for other things. | |
206 | */ | |
207 | pinctrl-names = "default", "ide"; | |
208 | pinctrl-0 = <&sata_default_pins>; | |
209 | pinctrl-1 = <&sata_and_ide_pins>; | |
0d7a2c35 LW |
210 | syscon = <&syscon>; |
211 | status = "disabled"; | |
212 | }; | |
213 | ||
9be0d7f8 LW |
214 | intcon: interrupt-controller@48000000 { |
215 | compatible = "faraday,ftintc010"; | |
216 | reg = <0x48000000 0x1000>; | |
5896a4d8 | 217 | resets = <&syscon GEMINI_RESET_INTCON0>; |
9be0d7f8 LW |
218 | interrupt-controller; |
219 | #interrupt-cells = <2>; | |
220 | }; | |
221 | ||
e9f2c2ae LW |
222 | power-controller@4b000000 { |
223 | compatible = "cortina,gemini-power-controller"; | |
224 | reg = <0x4b000000 0x100>; | |
225 | interrupts = <26 IRQ_TYPE_EDGE_RISING>; | |
f328c2ea LW |
226 | pinctrl-names = "default"; |
227 | pinctrl-0 = <&power_default_pins>; | |
e9f2c2ae LW |
228 | }; |
229 | ||
9be0d7f8 | 230 | gpio0: gpio@4d000000 { |
552c804a | 231 | compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; |
9be0d7f8 LW |
232 | reg = <0x4d000000 0x100>; |
233 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; | |
5896a4d8 LW |
234 | resets = <&syscon GEMINI_RESET_GPIO0>; |
235 | clocks = <&syscon GEMINI_CLK_APB>; | |
9be0d7f8 LW |
236 | gpio-controller; |
237 | #gpio-cells = <2>; | |
238 | interrupt-controller; | |
239 | #interrupt-cells = <2>; | |
240 | }; | |
241 | ||
242 | gpio1: gpio@4e000000 { | |
552c804a | 243 | compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; |
9be0d7f8 LW |
244 | reg = <0x4e000000 0x100>; |
245 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; | |
5896a4d8 LW |
246 | resets = <&syscon GEMINI_RESET_GPIO1>; |
247 | clocks = <&syscon GEMINI_CLK_APB>; | |
9be0d7f8 LW |
248 | gpio-controller; |
249 | #gpio-cells = <2>; | |
250 | interrupt-controller; | |
251 | #interrupt-cells = <2>; | |
252 | }; | |
253 | ||
254 | gpio2: gpio@4f000000 { | |
552c804a | 255 | compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; |
9be0d7f8 LW |
256 | reg = <0x4f000000 0x100>; |
257 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; | |
5896a4d8 LW |
258 | resets = <&syscon GEMINI_RESET_GPIO2>; |
259 | clocks = <&syscon GEMINI_CLK_APB>; | |
9be0d7f8 LW |
260 | gpio-controller; |
261 | #gpio-cells = <2>; | |
262 | interrupt-controller; | |
263 | #interrupt-cells = <2>; | |
264 | }; | |
e3aeca1d LW |
265 | |
266 | pci@50000000 { | |
267 | compatible = "cortina,gemini-pci", "faraday,ftpci100"; | |
268 | /* | |
269 | * The first 256 bytes in the IO range is actually used | |
270 | * to configure the host bridge. | |
271 | */ | |
272 | reg = <0x50000000 0x100>; | |
5896a4d8 LW |
273 | resets = <&syscon GEMINI_RESET_PCI>; |
274 | clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>; | |
664ed4e2 | 275 | clock-names = "PCLK", "PCICLK"; |
f328c2ea LW |
276 | pinctrl-names = "default"; |
277 | pinctrl-0 = <&pci_default_pins>; | |
e3aeca1d LW |
278 | #address-cells = <3>; |
279 | #size-cells = <2>; | |
280 | #interrupt-cells = <1>; | |
281 | status = "disabled"; | |
282 | ||
283 | bus-range = <0x00 0xff>; | |
284 | /* PCI ranges mappings */ | |
285 | ranges = | |
286 | /* 1MiB I/O space 0x50000000-0x500fffff */ | |
287 | <0x01000000 0 0 0x50000000 0 0x00100000>, | |
288 | /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ | |
289 | <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; | |
290 | ||
291 | /* DMA ranges */ | |
292 | dma-ranges = | |
293 | /* 128MiB at 0x00000000-0x07ffffff */ | |
294 | <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, | |
295 | /* 64MiB at 0x00000000-0x03ffffff */ | |
296 | <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, | |
297 | /* 64MiB at 0x00000000-0x03ffffff */ | |
298 | <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; | |
299 | ||
300 | /* | |
301 | * This PCI host bridge variant has a cascaded interrupt | |
302 | * controller embedded in the host bridge. | |
303 | */ | |
304 | pci_intc: interrupt-controller { | |
305 | interrupt-parent = <&intcon>; | |
306 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; | |
307 | interrupt-controller; | |
308 | #address-cells = <0>; | |
309 | #interrupt-cells = <1>; | |
310 | }; | |
311 | }; | |
9eeb0224 | 312 | |
0d7a2c35 LW |
313 | ata@63000000 { |
314 | compatible = "cortina,gemini-pata", "faraday,ftide010"; | |
315 | reg = <0x63000000 0x1000>; | |
316 | interrupts = <4 IRQ_TYPE_EDGE_RISING>; | |
5896a4d8 LW |
317 | resets = <&syscon GEMINI_RESET_IDE>; |
318 | clocks = <&syscon GEMINI_CLK_GATE_IDE>; | |
0d7a2c35 LW |
319 | clock-names = "PCLK"; |
320 | sata = <&sata>; | |
321 | status = "disabled"; | |
322 | }; | |
323 | ||
324 | ata@63400000 { | |
325 | compatible = "cortina,gemini-pata", "faraday,ftide010"; | |
326 | reg = <0x63400000 0x1000>; | |
327 | interrupts = <5 IRQ_TYPE_EDGE_RISING>; | |
5896a4d8 LW |
328 | resets = <&syscon GEMINI_RESET_IDE>; |
329 | clocks = <&syscon GEMINI_CLK_GATE_IDE>; | |
0d7a2c35 LW |
330 | clock-names = "PCLK"; |
331 | sata = <&sata>; | |
332 | status = "disabled"; | |
333 | }; | |
334 | ||
9eeb0224 LW |
335 | dma-controller@67000000 { |
336 | compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; | |
337 | /* Faraday Technology FTDMAC020 variant */ | |
338 | arm,primecell-periphid = <0x0003b080>; | |
339 | reg = <0x67000000 0x1000>; | |
340 | interrupts = <9 IRQ_TYPE_EDGE_RISING>; | |
5896a4d8 LW |
341 | resets = <&syscon GEMINI_RESET_DMAC>; |
342 | clocks = <&syscon GEMINI_CLK_AHB>; | |
9eeb0224 LW |
343 | clock-names = "apb_pclk"; |
344 | /* Bus interface AHB1 (AHB0) is totally tilted */ | |
345 | lli-bus-interface-ahb2; | |
346 | mem-bus-interface-ahb2; | |
347 | memcpy-burst-size = <256>; | |
348 | memcpy-bus-width = <32>; | |
349 | #dma-cells = <2>; | |
350 | }; | |
9be0d7f8 LW |
351 | }; |
352 | }; |