[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / hi3620.dtsi

/*
 * Hisilicon Ltd. Hi3620 SoC
 *
 * Copyright (C) 2012-2013 Hisilicon Ltd.
 * Copyright (C) 2012-2013 Linaro Ltd.
 *
 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */

#include <dt-bindings/clock/hi3620-clock.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
	};

	pclk: clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "apb_pclk";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "hisilicon,hi3620-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
		};
	};

	amba {

		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges = <0 0xfc000000 0x2000000>;

		L2: l2-cache {
			compatible = "arm,pl310-cache";
			reg = <0x100000 0x100000>;
			interrupts = <0 15 4>;
			cache-unified;
			cache-level = <2>;
		};

		gic: interrupt-controller@1000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			/* gic dist base, gic cpu base */
			reg = <0x1000 0x1000>, <0x100 0x100>;
		};

		sysctrl: system-controller@802000 {
			compatible = "hisilicon,sysctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x802000 0x1000>;
			reg = <0x802000 0x1000>;

			smp-offset = <0x31c>;
			resume-offset = <0x308>;
			reboot-offset = <0x4>;

			clock: clock@0 {
				compatible = "hisilicon,hi3620-clock";
				reg = <0 0x10000>;
				#clock-cells = <1>;
			};
		};

		dual_timer0: dual_timer@800000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x800000 0x1000>;
			/* timer00 & timer01 */
			interrupts = <0 0 4>, <0 1 4>;
			clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		dual_timer1: dual_timer@801000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x801000 0x1000>;
			/* timer10 & timer11 */
			interrupts = <0 2 4>, <0 3 4>;
			clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		dual_timer2: dual_timer@a01000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0xa01000 0x1000>;
			/* timer20 & timer21 */
			interrupts = <0 4 4>, <0 5 4>;
			clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		dual_timer3: dual_timer@a02000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0xa02000 0x1000>;
			/* timer30 & timer31 */
			interrupts = <0 6 4>, <0 7 4>;
			clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		dual_timer4: dual_timer@a03000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0xa03000 0x1000>;
			/* timer40 & timer41 */
			interrupts = <0 96 4>, <0 97 4>;
			clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		timer5: timer@600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x600 0x20>;
			interrupts = <1 13 0xf01>;
		};

		uart0: uart@b00000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xb00000 0x1000>;
			interrupts = <0 20 4>;
			clocks = <&clock HI3620_UARTCLK0>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		uart1: uart@b01000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xb01000 0x1000>;
			interrupts = <0 21 4>;
			clocks = <&clock HI3620_UARTCLK1>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		uart2: uart@b02000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xb02000 0x1000>;
			interrupts = <0 22 4>;
			clocks = <&clock HI3620_UARTCLK2>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		uart3: uart@b03000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xb03000 0x1000>;
			interrupts = <0 23 4>;
			clocks = <&clock HI3620_UARTCLK3>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		uart4: uart@b04000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xb04000 0x1000>;
			interrupts = <0 24 4>;
			clocks = <&clock HI3620_UARTCLK4>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio0: gpio@806000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x806000 0x1000>;
			interrupts = <0 64 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
					&pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK0>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@807000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x807000 0x1000>;
			interrupts = <0 65 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
					&pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
					&pmx0 6 5 1 &pmx0 7 6 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK1>;
			clock-names = "apb_pclk";
		};

		gpio2: gpio@808000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x808000 0x1000>;
			interrupts = <0 66 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
					&pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
					&pmx0 6 3 1 &pmx0 7 3 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK2>;
			clock-names = "apb_pclk";
		};

		gpio3: gpio@809000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x809000 0x1000>;
			interrupts = <0 67 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
					&pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
					&pmx0 6 11 1 &pmx0 7 11 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK3>;
			clock-names = "apb_pclk";
		};

		gpio4: gpio@80a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x80a000 0x1000>;
			interrupts = <0 68 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
					&pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
					&pmx0 6 13 1 &pmx0 7 13 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK4>;
			clock-names = "apb_pclk";
		};

		gpio5: gpio@80b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x80b000 0x1000>;
			interrupts = <0 69 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
					&pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
					&pmx0 6 16 1 &pmx0 7 16 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK5>;
			clock-names = "apb_pclk";
		};

		gpio6: gpio@80c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x80c000 0x1000>;
			interrupts = <0 70 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
					&pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
					&pmx0 6 18 1 &pmx0 7 19 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK6>;
			clock-names = "apb_pclk";
		};

		gpio7: gpio@80d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x80d000 0x1000>;
			interrupts = <0 71 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
					&pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
					&pmx0 6 25 1 &pmx0 7 26 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK7>;
			clock-names = "apb_pclk";
		};

		gpio8: gpio@80e000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x80e000 0x1000>;
			interrupts = <0 72 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
					&pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
					&pmx0 6 33 1 &pmx0 7 34 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK8>;
			clock-names = "apb_pclk";
		};

		gpio9: gpio@80f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x80f000 0x1000>;
			interrupts = <0 73 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
					&pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
					&pmx0 6 41 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK9>;
			clock-names = "apb_pclk";
		};

		gpio10: gpio@810000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x810000 0x1000>;
			interrupts = <0 74 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
					&pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK10>;
			clock-names = "apb_pclk";
		};

		gpio11: gpio@811000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x811000 0x1000>;
			interrupts = <0 75 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
					&pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
					&pmx0 6 49 1 &pmx0 7 49 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK11>;
			clock-names = "apb_pclk";
		};

		gpio12: gpio@812000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x812000 0x1000>;
			interrupts = <0 76 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
					&pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
					&pmx0 6 51 1 &pmx0 7 52 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK12>;
			clock-names = "apb_pclk";
		};

		gpio13: gpio@813000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x813000 0x1000>;
			interrupts = <0 77 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
					&pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
					&pmx0 6 55 1 &pmx0 7 56 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK13>;
			clock-names = "apb_pclk";
		};

		gpio14: gpio@814000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x814000 0x1000>;
			interrupts = <0 78 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
					&pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
					&pmx0 6 60 1 &pmx0 7 61 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK14>;
			clock-names = "apb_pclk";
		};

		gpio15: gpio@815000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x815000 0x1000>;
			interrupts = <0 79 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
					&pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
					&pmx0 6 64 1 &pmx0 7 65 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK15>;
			clock-names = "apb_pclk";
		};

		gpio16: gpio@816000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x816000 0x1000>;
			interrupts = <0 80 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
					&pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
					&pmx0 6 72 1 &pmx0 7 73 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK16>;
			clock-names = "apb_pclk";
		};

		gpio17: gpio@817000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x817000 0x1000>;
			interrupts = <0 81 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
					&pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
					&pmx0 6 80 1 &pmx0 7 81 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK17>;
			clock-names = "apb_pclk";
		};

		gpio18: gpio@818000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x818000 0x1000>;
			interrupts = <0 82 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
					&pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
					&pmx0 6 86 1 &pmx0 7 87 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK18>;
			clock-names = "apb_pclk";
		};

		gpio19: gpio@819000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x819000 0x1000>;
			interrupts = <0 83 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
					&pmx0 3 88 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK19>;
			clock-names = "apb_pclk";
		};

		gpio20: gpio@81a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x81a000 0x1000>;
			interrupts = <0 84 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
					&pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK20>;
			clock-names = "apb_pclk";
		};

		gpio21: gpio@81b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x81b000 0x1000>;
			interrupts = <0 85 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 3 94 1 &pmx0 7 96 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clock HI3620_GPIOCLK21>;
			clock-names = "apb_pclk";
		};

		pmx0: pinmux@803000 {
			compatible = "pinctrl-single";
			reg = <0x803000 0x188>;
			#address-cells = <1>;
			#size-cells = <1>;
			#pinctrl-cells = <1>;
			#gpio-range-cells = <3>;
			ranges;

			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <7>;
			/* pin base, nr pins & gpio function */
			pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
						&range 12 1 0 &range 13 29 1
						&range 43 1 0 &range 44 49 1
						&range 94 1 1 &range 96 2 1>;

			range: gpio-range {
				#pinctrl-single,gpio-range-cells = <3>;
			};
		};

		pmx1: pinmux@803800 {
			compatible = "pinconf-single";
			reg = <0x803800 0x2dc>;
			#address-cells = <1>;
			#size-cells = <1>;
			#pinctrl-cells = <1>;
			ranges;

			pinctrl-single,register-width = <32>;
		};
	};
};
Commit	Line	Data
fa8962a8 HZ	1	/*
	2	* Hisilicon Ltd. Hi3620 SoC
	3	*
	4	* Copyright (C) 2012-2013 Hisilicon Ltd.
	5	* Copyright (C) 2012-2013 Linaro Ltd.
	6	*
	7	* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* publishhed by the Free Software Foundation.
	12	*/
	13
22e99a6d	14	#include <dt-bindings/clock/hi3620-clock.h>
fa8962a8 HZ	15
fa8962a8 HZ	16	/ {
4899138f KW	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
fa8962a8 HZ	20	aliases {
	21	serial0 = &uart0;
	22	serial1 = &uart1;
	23	serial2 = &uart2;
	24	serial3 = &uart3;
	25	serial4 = &uart4;
	26	};
	27
	28	pclk: clk {
	29	compatible = "fixed-clock";
	30	#clock-cells = <0>;
	31	clock-frequency = <26000000>;
	32	clock-output-names = "apb_pclk";
	33	};
	34
	35	cpus {
	36	#address-cells = <1>;
	37	#size-cells = <0>;
c2fff85e	38	enable-method = "hisilicon,hi3620-smp";
fa8962a8 HZ	39
	40	cpu@0 {
	41	device_type = "cpu";
	42	compatible = "arm,cortex-a9";
	43	reg = <0x0>;
	44	next-level-cache = <&L2>;
	45	};
a9434e96 KH	46
	47	cpu@1 {
	48	compatible = "arm,cortex-a9";
	49	device_type = "cpu";
	50	reg = <1>;
	51	next-level-cache = <&L2>;
	52	};
	53
	54	cpu@2 {
	55	compatible = "arm,cortex-a9";
	56	device_type = "cpu";
	57	reg = <2>;
	58	next-level-cache = <&L2>;
	59	};
	60
	61	cpu@3 {
	62	compatible = "arm,cortex-a9";
	63	device_type = "cpu";
	64	reg = <3>;
	65	next-level-cache = <&L2>;
	66	};
fa8962a8 HZ	67	};
	68
	69	amba {
22e99a6d	70
fa8962a8 HZ	71	#address-cells = <1>;
fa8962a8 HZ	72	#size-cells = <1>;
2ef7d5f3	73	compatible = "simple-bus";
fa8962a8 HZ	74	interrupt-parent = <&gic>;
	75	ranges = <0 0xfc000000 0x2000000>;
	76
	77	L2: l2-cache {
	78	compatible = "arm,pl310-cache";
28c9770b	79	reg = <0x100000 0x100000>;
fa8962a8 HZ	80	interrupts = <0 15 4>;
	81	cache-unified;
	82	cache-level = <2>;
	83	};
	84
	85	gic: interrupt-controller@1000 {
	86	compatible = "arm,cortex-a9-gic";
	87	#interrupt-cells = <3>;
	88	#address-cells = <0>;
	89	interrupt-controller;
	90	/* gic dist base, gic cpu base */
	91	reg = <0x1000 0x1000>, <0x100 0x100>;
	92	};
	93
a9434e96 KH	94	sysctrl: system-controller@802000 {
a9434e96 KH	95	compatible = "hisilicon,sysctrl";
a9434e96	96	#address-cells = <1>;
22e99a6d HZ	97	#size-cells = <1>;
	98	ranges = <0 0x802000 0x1000>;
	99	reg = <0x802000 0x1000>;
a9434e96 KH	100
	101	smp-offset = <0x31c>;
	102	resume-offset = <0x308>;
	103	reboot-offset = <0x4>;
22e99a6d HZ	104
	105	clock: clock@0 {
	106	compatible = "hisilicon,hi3620-clock";
	107	reg = <0 0x10000>;
	108	#clock-cells = <1>;
	109	};
a9434e96 KH	110	};
a9434e96 KH	111
fa8962a8 HZ	112	dual_timer0: dual_timer@800000 {
	113	compatible = "arm,sp804", "arm,primecell";
	114	reg = <0x800000 0x1000>;
	115	/* timer00 & timer01 */
	116	interrupts = <0 0 4>, <0 1 4>;
22e99a6d	117	clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
fa8962a8 HZ	118	clock-names = "apb_pclk";
	119	status = "disabled";
	120	};
	121
	122	dual_timer1: dual_timer@801000 {
	123	compatible = "arm,sp804", "arm,primecell";
	124	reg = <0x801000 0x1000>;
	125	/* timer10 & timer11 */
	126	interrupts = <0 2 4>, <0 3 4>;
22e99a6d	127	clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
fa8962a8 HZ	128	clock-names = "apb_pclk";
	129	status = "disabled";
	130	};
	131
	132	dual_timer2: dual_timer@a01000 {
	133	compatible = "arm,sp804", "arm,primecell";
	134	reg = <0xa01000 0x1000>;
	135	/* timer20 & timer21 */
	136	interrupts = <0 4 4>, <0 5 4>;
22e99a6d	137	clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
fa8962a8 HZ	138	clock-names = "apb_pclk";
	139	status = "disabled";
	140	};
	141
	142	dual_timer3: dual_timer@a02000 {
	143	compatible = "arm,sp804", "arm,primecell";
	144	reg = <0xa02000 0x1000>;
	145	/* timer30 & timer31 */
	146	interrupts = <0 6 4>, <0 7 4>;
22e99a6d	147	clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
fa8962a8 HZ	148	clock-names = "apb_pclk";
	149	status = "disabled";
	150	};
	151
	152	dual_timer4: dual_timer@a03000 {
	153	compatible = "arm,sp804", "arm,primecell";
	154	reg = <0xa03000 0x1000>;
	155	/* timer40 & timer41 */
	156	interrupts = <0 96 4>, <0 97 4>;
22e99a6d	157	clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
fa8962a8 HZ	158	clock-names = "apb_pclk";
	159	status = "disabled";
	160	};
	161
a9434e96 KH	162	timer5: timer@600 {
	163	compatible = "arm,cortex-a9-twd-timer";
	164	reg = <0x600 0x20>;
	165	interrupts = <1 13 0xf01>;
	166	};
	167
fa8962a8 HZ	168	uart0: uart@b00000 {
	169	compatible = "arm,pl011", "arm,primecell";
	170	reg = <0xb00000 0x1000>;
	171	interrupts = <0 20 4>;
22e99a6d	172	clocks = <&clock HI3620_UARTCLK0>;
fa8962a8 HZ	173	clock-names = "apb_pclk";
	174	status = "disabled";
	175	};
	176
	177	uart1: uart@b01000 {
	178	compatible = "arm,pl011", "arm,primecell";
	179	reg = <0xb01000 0x1000>;
	180	interrupts = <0 21 4>;
22e99a6d	181	clocks = <&clock HI3620_UARTCLK1>;
fa8962a8 HZ	182	clock-names = "apb_pclk";
	183	status = "disabled";
	184	};
	185
	186	uart2: uart@b02000 {
	187	compatible = "arm,pl011", "arm,primecell";
	188	reg = <0xb02000 0x1000>;
	189	interrupts = <0 22 4>;
22e99a6d	190	clocks = <&clock HI3620_UARTCLK2>;
fa8962a8 HZ	191	clock-names = "apb_pclk";
	192	status = "disabled";
	193	};
	194
	195	uart3: uart@b03000 {
	196	compatible = "arm,pl011", "arm,primecell";
	197	reg = <0xb03000 0x1000>;
	198	interrupts = <0 23 4>;
22e99a6d	199	clocks = <&clock HI3620_UARTCLK3>;
fa8962a8 HZ	200	clock-names = "apb_pclk";
	201	status = "disabled";
	202	};
	203
	204	uart4: uart@b04000 {
	205	compatible = "arm,pl011", "arm,primecell";
	206	reg = <0xb04000 0x1000>;
	207	interrupts = <0 24 4>;
22e99a6d	208	clocks = <&clock HI3620_UARTCLK4>;
fa8962a8 HZ	209	clock-names = "apb_pclk";
	210	status = "disabled";
	211	};
	212
	213	gpio0: gpio@806000 {
	214	compatible = "arm,pl061", "arm,primecell";
	215	reg = <0x806000 0x1000>;
	216	interrupts = <0 64 0x4>;
	217	gpio-controller;
	218	#gpio-cells = <2>;
	219	gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
	220	&pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
	221	interrupt-controller;
	222	#interrupt-cells = <2>;
22e99a6d	223	clocks = <&clock HI3620_GPIOCLK0>;
fa8962a8 HZ	224	clock-names = "apb_pclk";
	225	};
	226
	227	gpio1: gpio@807000 {
	228	compatible = "arm,pl061", "arm,primecell";
	229	reg = <0x807000 0x1000>;
	230	interrupts = <0 65 0x4>;
	231	gpio-controller;
	232	#gpio-cells = <2>;
	233	gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
	234	&pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
	235	&pmx0 6 5 1 &pmx0 7 6 1>;
	236	interrupt-controller;
	237	#interrupt-cells = <2>;
22e99a6d	238	clocks = <&clock HI3620_GPIOCLK1>;
fa8962a8 HZ	239	clock-names = "apb_pclk";
	240	};
	241
	242	gpio2: gpio@808000 {
	243	compatible = "arm,pl061", "arm,primecell";
	244	reg = <0x808000 0x1000>;
	245	interrupts = <0 66 0x4>;
	246	gpio-controller;
	247	#gpio-cells = <2>;
	248	gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
	249	&pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
	250	&pmx0 6 3 1 &pmx0 7 3 1>;
	251	interrupt-controller;
	252	#interrupt-cells = <2>;
22e99a6d	253	clocks = <&clock HI3620_GPIOCLK2>;
fa8962a8 HZ	254	clock-names = "apb_pclk";
	255	};
	256
	257	gpio3: gpio@809000 {
	258	compatible = "arm,pl061", "arm,primecell";
	259	reg = <0x809000 0x1000>;
	260	interrupts = <0 67 0x4>;
	261	gpio-controller;
	262	#gpio-cells = <2>;
	263	gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
	264	&pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
	265	&pmx0 6 11 1 &pmx0 7 11 1>;
	266	interrupt-controller;
	267	#interrupt-cells = <2>;
22e99a6d	268	clocks = <&clock HI3620_GPIOCLK3>;
fa8962a8 HZ	269	clock-names = "apb_pclk";
	270	};
	271
	272	gpio4: gpio@80a000 {
	273	compatible = "arm,pl061", "arm,primecell";
	274	reg = <0x80a000 0x1000>;
	275	interrupts = <0 68 0x4>;
	276	gpio-controller;
	277	#gpio-cells = <2>;
	278	gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
	279	&pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
	280	&pmx0 6 13 1 &pmx0 7 13 1>;
	281	interrupt-controller;
	282	#interrupt-cells = <2>;
22e99a6d	283	clocks = <&clock HI3620_GPIOCLK4>;
fa8962a8 HZ	284	clock-names = "apb_pclk";
	285	};
	286
	287	gpio5: gpio@80b000 {
	288	compatible = "arm,pl061", "arm,primecell";
	289	reg = <0x80b000 0x1000>;
	290	interrupts = <0 69 0x4>;
	291	gpio-controller;
	292	#gpio-cells = <2>;
	293	gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
	294	&pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
	295	&pmx0 6 16 1 &pmx0 7 16 1>;
	296	interrupt-controller;
	297	#interrupt-cells = <2>;
22e99a6d	298	clocks = <&clock HI3620_GPIOCLK5>;
fa8962a8 HZ	299	clock-names = "apb_pclk";
	300	};
	301
	302	gpio6: gpio@80c000 {
	303	compatible = "arm,pl061", "arm,primecell";
	304	reg = <0x80c000 0x1000>;
	305	interrupts = <0 70 0x4>;
	306	gpio-controller;
	307	#gpio-cells = <2>;
	308	gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
	309	&pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
	310	&pmx0 6 18 1 &pmx0 7 19 1>;
	311	interrupt-controller;
	312	#interrupt-cells = <2>;
22e99a6d	313	clocks = <&clock HI3620_GPIOCLK6>;
fa8962a8 HZ	314	clock-names = "apb_pclk";
	315	};
	316
	317	gpio7: gpio@80d000 {
	318	compatible = "arm,pl061", "arm,primecell";
	319	reg = <0x80d000 0x1000>;
	320	interrupts = <0 71 0x4>;
	321	gpio-controller;
	322	#gpio-cells = <2>;
	323	gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
	324	&pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
	325	&pmx0 6 25 1 &pmx0 7 26 1>;
	326	interrupt-controller;
	327	#interrupt-cells = <2>;
22e99a6d	328	clocks = <&clock HI3620_GPIOCLK7>;
fa8962a8 HZ	329	clock-names = "apb_pclk";
	330	};
	331
	332	gpio8: gpio@80e000 {
	333	compatible = "arm,pl061", "arm,primecell";
	334	reg = <0x80e000 0x1000>;
	335	interrupts = <0 72 0x4>;
	336	gpio-controller;
	337	#gpio-cells = <2>;
	338	gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
	339	&pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
	340	&pmx0 6 33 1 &pmx0 7 34 1>;
	341	interrupt-controller;
	342	#interrupt-cells = <2>;
22e99a6d	343	clocks = <&clock HI3620_GPIOCLK8>;
fa8962a8 HZ	344	clock-names = "apb_pclk";
	345	};
	346
	347	gpio9: gpio@80f000 {
	348	compatible = "arm,pl061", "arm,primecell";
	349	reg = <0x80f000 0x1000>;
	350	interrupts = <0 73 0x4>;
	351	gpio-controller;
	352	#gpio-cells = <2>;
	353	gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
	354	&pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
	355	&pmx0 6 41 1>;
	356	interrupt-controller;
	357	#interrupt-cells = <2>;
22e99a6d	358	clocks = <&clock HI3620_GPIOCLK9>;
fa8962a8 HZ	359	clock-names = "apb_pclk";
	360	};
	361
	362	gpio10: gpio@810000 {
	363	compatible = "arm,pl061", "arm,primecell";
	364	reg = <0x810000 0x1000>;
	365	interrupts = <0 74 0x4>;
	366	gpio-controller;
	367	#gpio-cells = <2>;
	368	gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
	369	&pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
	370	interrupt-controller;
	371	#interrupt-cells = <2>;
22e99a6d	372	clocks = <&clock HI3620_GPIOCLK10>;
fa8962a8 HZ	373	clock-names = "apb_pclk";
	374	};
	375
	376	gpio11: gpio@811000 {
	377	compatible = "arm,pl061", "arm,primecell";
	378	reg = <0x811000 0x1000>;
	379	interrupts = <0 75 0x4>;
	380	gpio-controller;
	381	#gpio-cells = <2>;
	382	gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
	383	&pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
	384	&pmx0 6 49 1 &pmx0 7 49 1>;
	385	interrupt-controller;
	386	#interrupt-cells = <2>;
22e99a6d	387	clocks = <&clock HI3620_GPIOCLK11>;
fa8962a8 HZ	388	clock-names = "apb_pclk";
	389	};
	390
	391	gpio12: gpio@812000 {
	392	compatible = "arm,pl061", "arm,primecell";
	393	reg = <0x812000 0x1000>;
	394	interrupts = <0 76 0x4>;
	395	gpio-controller;
	396	#gpio-cells = <2>;
	397	gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
	398	&pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
	399	&pmx0 6 51 1 &pmx0 7 52 1>;
	400	interrupt-controller;
	401	#interrupt-cells = <2>;
22e99a6d	402	clocks = <&clock HI3620_GPIOCLK12>;
fa8962a8 HZ	403	clock-names = "apb_pclk";
	404	};
	405
	406	gpio13: gpio@813000 {
	407	compatible = "arm,pl061", "arm,primecell";
	408	reg = <0x813000 0x1000>;
	409	interrupts = <0 77 0x4>;
	410	gpio-controller;
	411	#gpio-cells = <2>;
	412	gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
	413	&pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
	414	&pmx0 6 55 1 &pmx0 7 56 1>;
	415	interrupt-controller;
	416	#interrupt-cells = <2>;
22e99a6d	417	clocks = <&clock HI3620_GPIOCLK13>;
fa8962a8 HZ	418	clock-names = "apb_pclk";
	419	};
	420
	421	gpio14: gpio@814000 {
	422	compatible = "arm,pl061", "arm,primecell";
	423	reg = <0x814000 0x1000>;
	424	interrupts = <0 78 0x4>;
	425	gpio-controller;
	426	#gpio-cells = <2>;
	427	gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
	428	&pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
	429	&pmx0 6 60 1 &pmx0 7 61 1>;
	430	interrupt-controller;
	431	#interrupt-cells = <2>;
22e99a6d	432	clocks = <&clock HI3620_GPIOCLK14>;
fa8962a8 HZ	433	clock-names = "apb_pclk";
	434	};
	435
	436	gpio15: gpio@815000 {
	437	compatible = "arm,pl061", "arm,primecell";
	438	reg = <0x815000 0x1000>;
	439	interrupts = <0 79 0x4>;
	440	gpio-controller;
	441	#gpio-cells = <2>;
	442	gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
	443	&pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
	444	&pmx0 6 64 1 &pmx0 7 65 1>;
	445	interrupt-controller;
	446	#interrupt-cells = <2>;
22e99a6d	447	clocks = <&clock HI3620_GPIOCLK15>;
fa8962a8 HZ	448	clock-names = "apb_pclk";
	449	};
	450
	451	gpio16: gpio@816000 {
	452	compatible = "arm,pl061", "arm,primecell";
	453	reg = <0x816000 0x1000>;
	454	interrupts = <0 80 0x4>;
	455	gpio-controller;
	456	#gpio-cells = <2>;
	457	gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
	458	&pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
	459	&pmx0 6 72 1 &pmx0 7 73 1>;
	460	interrupt-controller;
	461	#interrupt-cells = <2>;
22e99a6d	462	clocks = <&clock HI3620_GPIOCLK16>;
fa8962a8 HZ	463	clock-names = "apb_pclk";
	464	};
	465
	466	gpio17: gpio@817000 {
	467	compatible = "arm,pl061", "arm,primecell";
	468	reg = <0x817000 0x1000>;
	469	interrupts = <0 81 0x4>;
	470	gpio-controller;
	471	#gpio-cells = <2>;
	472	gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
	473	&pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
	474	&pmx0 6 80 1 &pmx0 7 81 1>;
	475	interrupt-controller;
	476	#interrupt-cells = <2>;
22e99a6d	477	clocks = <&clock HI3620_GPIOCLK17>;
fa8962a8 HZ	478	clock-names = "apb_pclk";
	479	};
	480
	481	gpio18: gpio@818000 {
	482	compatible = "arm,pl061", "arm,primecell";
	483	reg = <0x818000 0x1000>;
	484	interrupts = <0 82 0x4>;
	485	gpio-controller;
	486	#gpio-cells = <2>;
	487	gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
	488	&pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
	489	&pmx0 6 86 1 &pmx0 7 87 1>;
	490	interrupt-controller;
	491	#interrupt-cells = <2>;
22e99a6d	492	clocks = <&clock HI3620_GPIOCLK18>;
fa8962a8 HZ	493	clock-names = "apb_pclk";
	494	};
	495
	496	gpio19: gpio@819000 {
	497	compatible = "arm,pl061", "arm,primecell";
	498	reg = <0x819000 0x1000>;
	499	interrupts = <0 83 0x4>;
	500	gpio-controller;
	501	#gpio-cells = <2>;
	502	gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
	503	&pmx0 3 88 1>;
	504	interrupt-controller;
	505	#interrupt-cells = <2>;
22e99a6d	506	clocks = <&clock HI3620_GPIOCLK19>;
fa8962a8 HZ	507	clock-names = "apb_pclk";
	508	};
	509
	510	gpio20: gpio@81a000 {
	511	compatible = "arm,pl061", "arm,primecell";
	512	reg = <0x81a000 0x1000>;
	513	interrupts = <0 84 0x4>;
	514	gpio-controller;
	515	#gpio-cells = <2>;
	516	gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
	517	&pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
	518	interrupt-controller;
	519	#interrupt-cells = <2>;
22e99a6d	520	clocks = <&clock HI3620_GPIOCLK20>;
fa8962a8 HZ	521	clock-names = "apb_pclk";
	522	};
	523
	524	gpio21: gpio@81b000 {
	525	compatible = "arm,pl061", "arm,primecell";
	526	reg = <0x81b000 0x1000>;
	527	interrupts = <0 85 0x4>;
	528	gpio-controller;
	529	#gpio-cells = <2>;
	530	gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
	531	interrupt-controller;
	532	#interrupt-cells = <2>;
22e99a6d	533	clocks = <&clock HI3620_GPIOCLK21>;
fa8962a8 HZ	534	clock-names = "apb_pclk";
	535	};
	536
	537	pmx0: pinmux@803000 {
	538	compatible = "pinctrl-single";
	539	reg = <0x803000 0x188>;
	540	#address-cells = <1>;
	541	#size-cells = <1>;
be76fd31	542	#pinctrl-cells = <1>;
fa8962a8 HZ	543	#gpio-range-cells = <3>;
	544	ranges;
	545
	546	pinctrl-single,register-width = <32>;
	547	pinctrl-single,function-mask = <7>;
	548	/* pin base, nr pins & gpio function */
	549	pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
	550	&range 12 1 0 &range 13 29 1
	551	&range 43 1 0 &range 44 49 1
	552	&range 94 1 1 &range 96 2 1>;
	553
	554	range: gpio-range {
	555	#pinctrl-single,gpio-range-cells = <3>;
	556	};
	557	};
	558
	559	pmx1: pinmux@803800 {
	560	compatible = "pinconf-single";
	561	reg = <0x803800 0x2dc>;
	562	#address-cells = <1>;
	563	#size-cells = <1>;
be76fd31	564	#pinctrl-cells = <1>;
fa8962a8 HZ	565	ranges;
	566
	567	pinctrl-single,register-width = <32>;
	568	};
	569	};
	570	};