projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 253d7add | 1 | /* |
| 8d4d9f52 | 2 | * Copyright 2011-2012 Calxeda, Inc. |
| 253d7add RH |
3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it | |
| 5 | * under the terms and conditions of the GNU General Public License, | |
| 6 | * version 2, as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 11 | * more details. | |
| 12 | * | |
| 13 | * You should have received a copy of the GNU General Public License along with | |
| 14 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
| 15 | */ | |
| 16 | ||
| 17 | /dts-v1/; | |
| 18 | ||
| 19 | /* First 4KB has pen for secondary cores. */ | |
| 20 | /memreserve/ 0x00000000 0x0001000; | |
| 21 | ||
| 22 | / { | |
| 23 | model = "Calxeda Highbank"; | |
| 24 | compatible = "calxeda,highbank"; | |
| 25 | #address-cells = <1>; | |
| 26 | #size-cells = <1>; | |
| 8d4d9f52 | 27 | clock-ranges; |
| 253d7add RH |
28 | |
| 29 | cpus { | |
| 30 | #address-cells = <1>; | |
| 31 | #size-cells = <0>; | |
| 32 | ||
| 3943deed | 33 | cpu@900 { |
| 253d7add | 34 | compatible = "arm,cortex-a9"; |
| 36ff67bc | 35 | device_type = "cpu"; |
| 3943deed | 36 | reg = <0x900>; |
| 253d7add | 37 | next-level-cache = <&L2>; |
| 8d4d9f52 RH |
38 | clocks = <&a9pll>; |
| 39 | clock-names = "cpu"; | |
| 6754f556 ML |
40 | operating-points = < |
| 41 | /* kHz ignored */ | |
| 42 | 1300000 1000000 | |
| 43 | 1200000 1000000 | |
| 44 | 1100000 1000000 | |
| 45 | 800000 1000000 | |
| 46 | 400000 1000000 | |
| 47 | 200000 1000000 | |
| 48 | >; | |
| 49 | clock-latency = <100000>; | |
| 253d7add RH |
50 | }; |
| 51 | ||
| 3943deed | 52 | cpu@901 { |
| 253d7add | 53 | compatible = "arm,cortex-a9"; |
| 36ff67bc | 54 | device_type = "cpu"; |
| 3943deed | 55 | reg = <0x901>; |
| 253d7add | 56 | next-level-cache = <&L2>; |
| 8d4d9f52 RH |
57 | clocks = <&a9pll>; |
| 58 | clock-names = "cpu"; | |
| c7ea1579 VK |
59 | operating-points = < |
| 60 | /* kHz ignored */ | |
| 61 | 1300000 1000000 | |
| 62 | 1200000 1000000 | |
| 63 | 1100000 1000000 | |
| 64 | 800000 1000000 | |
| 65 | 400000 1000000 | |
| 66 | 200000 1000000 | |
| 67 | >; | |
| 68 | clock-latency = <100000>; | |
| 253d7add RH |
69 | }; |
| 70 | ||
| 3943deed | 71 | cpu@902 { |
| 253d7add | 72 | compatible = "arm,cortex-a9"; |
| 36ff67bc | 73 | device_type = "cpu"; |
| 3943deed | 74 | reg = <0x902>; |
| 253d7add | 75 | next-level-cache = <&L2>; |
| 8d4d9f52 RH |
76 | clocks = <&a9pll>; |
| 77 | clock-names = "cpu"; | |
| c7ea1579 VK |
78 | operating-points = < |
| 79 | /* kHz ignored */ | |
| 80 | 1300000 1000000 | |
| 81 | 1200000 1000000 | |
| 82 | 1100000 1000000 | |
| 83 | 800000 1000000 | |
| 84 | 400000 1000000 | |
| 85 | 200000 1000000 | |
| 86 | >; | |
| 87 | clock-latency = <100000>; | |
| 253d7add RH |
88 | }; |
| 89 | ||
| 3943deed | 90 | cpu@903 { |
| 253d7add | 91 | compatible = "arm,cortex-a9"; |
| 36ff67bc | 92 | device_type = "cpu"; |
| 3943deed | 93 | reg = <0x903>; |
| 253d7add | 94 | next-level-cache = <&L2>; |
| 8d4d9f52 RH |
95 | clocks = <&a9pll>; |
| 96 | clock-names = "cpu"; | |
| c7ea1579 VK |
97 | operating-points = < |
| 98 | /* kHz ignored */ | |
| 99 | 1300000 1000000 | |
| 100 | 1200000 1000000 | |
| 101 | 1100000 1000000 | |
| 102 | 800000 1000000 | |
| 103 | 400000 1000000 | |
| 104 | 200000 1000000 | |
| 105 | >; | |
| 106 | clock-latency = <100000>; | |
| 253d7add RH |
107 | }; |
| 108 | }; | |
| 109 | ||
| 110 | memory { | |
| 111 | name = "memory"; | |
| 112 | device_type = "memory"; | |
| 113 | reg = <0x00000000 0xff900000>; | |
| 114 | }; | |
| 115 | ||
| 253d7add | 116 | soc { |
| 7d6ab9b8 | 117 | ranges = <0x00000000 0x00000000 0xffffffff>; |
| 253d7add | 118 | |
| 982ac2a7 RH |
119 | memory-controller@fff00000 { |
| 120 | compatible = "calxeda,hb-ddr-ctrl"; | |
| 121 | reg = <0xfff00000 0x1000>; | |
| 122 | interrupts = <0 91 4>; | |
| 123 | }; | |
| 124 | ||
| 253d7add | 125 | timer@fff10600 { |
| 7ac9b9eb | 126 | compatible = "arm,cortex-a9-twd-timer"; |
| 253d7add | 127 | reg = <0xfff10600 0x20>; |
| 7ac9b9eb | 128 | interrupts = <1 13 0xf01>; |
| 8d4d9f52 | 129 | clocks = <&a9periphclk>; |
| 253d7add RH |
130 | }; |
| 131 | ||
| 132 | watchdog@fff10620 { | |
| 7ac9b9eb | 133 | compatible = "arm,cortex-a9-twd-wdt"; |
| 253d7add | 134 | reg = <0xfff10620 0x20>; |
| 7ac9b9eb | 135 | interrupts = <1 14 0xf01>; |
| 8d4d9f52 | 136 | clocks = <&a9periphclk>; |
| 253d7add RH |
137 | }; |
| 138 | ||
| 139 | intc: interrupt-controller@fff11000 { | |
| 140 | compatible = "arm,cortex-a9-gic"; | |
| 141 | #interrupt-cells = <3>; | |
| 142 | #size-cells = <0>; | |
| 143 | #address-cells = <1>; | |
| 144 | interrupt-controller; | |
| 253d7add RH |
145 | reg = <0xfff11000 0x1000>, |
| 146 | <0xfff10100 0x100>; | |
| 147 | }; | |
| 148 | ||
| 149 | L2: l2-cache { | |
| 150 | compatible = "arm,pl310-cache"; | |
| 151 | reg = <0xfff12000 0x1000>; | |
| 152 | interrupts = <0 70 4>; | |
| 153 | cache-unified; | |
| 154 | cache-level = <2>; | |
| 155 | }; | |
| 156 | ||
| 157 | pmu { | |
| 158 | compatible = "arm,cortex-a9-pmu"; | |
| 159 | interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; | |
| 160 | }; | |
| 161 | ||
| 253d7add | 162 | |
| 69154d06 RH |
163 | sregs@fff3c200 { |
| 164 | compatible = "calxeda,hb-sregs-l2-ecc"; | |
| 165 | reg = <0xfff3c200 0x100>; | |
| 166 | interrupts = <0 71 4 0 72 4>; | |
| 167 | }; | |
| 168 | ||
| 253d7add RH |
169 | }; |
| 170 | }; | |
| 7d6ab9b8 RH |
171 | |
| 172 | /include/ "ecx-common.dtsi" |