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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
56a9c909 WL |
2 | /* |
3 | * Hisilicon Ltd. HiP01 SoC | |
4 | * | |
5 | * Copyright (C) 2014 Hisilicon Ltd. | |
6 | * Copyright (C) 2014 Huawei Ltd. | |
7 | * | |
8 | * Author: Wang Long <long.wanglong@huawei.com> | |
56a9c909 WL |
9 | */ |
10 | ||
11 | /dts-v1/; | |
12 | ||
13 | /* First 8KB reserved for secondary core boot */ | |
14 | /memreserve/ 0x80000000 0x00002000; | |
15 | ||
16 | #include "hip01.dtsi" | |
17 | ||
18 | / { | |
19 | model = "Hisilicon HIP01 Development Board"; | |
20 | compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01"; | |
21 | ||
22 | cpus { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <0>; | |
25 | enable-method = "hisilicon,hip01-smp"; | |
26 | ||
27 | cpu@0 { | |
28 | device_type = "cpu"; | |
29 | compatible = "arm,cortex-a9"; | |
30 | reg = <0>; | |
31 | }; | |
32 | ||
33 | cpu@1 { | |
34 | device_type = "cpu"; | |
35 | compatible = "arm,cortex-a9"; | |
36 | reg = <1>; | |
37 | }; | |
38 | }; | |
39 | ||
40 | memory { | |
41 | device_type = "memory"; | |
42 | reg = <0x80000000 0x80000000>; | |
43 | }; | |
44 | }; | |
45 | ||
46 | &uart0 { | |
47 | status = "okay"; | |
48 | }; |