[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / imx1.dtsi

/*
 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "imx1-pinfunc.h"

#include <dt-bindings/clock/imx1-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 * Also for U-Boot there must be a pre-existing /memory node.
	 */
	chosen {};
	memory { device_type = "memory"; reg = <0 0>; };

	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		i2c0 = &i2c;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		spi0 = &cspi1;
		spi1 = &cspi2;
	};

	aitc: aitc-interrupt-controller@00223000 {
		compatible = "fsl,imx1-aitc", "fsl,avic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x00223000 0x1000>;
	};

	cpus {
		#size-cells = <0>;
		#address-cells = <1>;

		cpu: cpu@0 {
			device_type = "cpu";
			compatible = "arm,arm920t";
			operating-points = <200000 1900000>;
			clock-latency = <62500>;
			clocks = <&clks IMX1_CLK_MCU>;
			voltage-tolerance = <5>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&aitc>;
		ranges;

		aipi@00200000 {
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x00200000 0x10000>;
			ranges;

			gpt1: timer@00202000 {
				compatible = "fsl,imx1-gpt";
				reg = <0x00202000 0x1000>;
				interrupts = <59>;
				clocks = <&clks IMX1_CLK_HCLK>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
			};

			gpt2: timer@00203000 {
				compatible = "fsl,imx1-gpt";
				reg = <0x00203000 0x1000>;
				interrupts = <58>;
				clocks = <&clks IMX1_CLK_HCLK>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
			};

			fb: fb@00205000 {
				compatible = "fsl,imx1-fb";
				reg = <0x00205000 0x1000>;
				interrupts = <14>;
				clocks = <&clks IMX1_CLK_DUMMY>,
					 <&clks IMX1_CLK_DUMMY>,
					 <&clks IMX1_CLK_PER2>;
				clock-names = "ipg", "ahb", "per";
				status = "disabled";
			};

			uart1: serial@00206000 {
				compatible = "fsl,imx1-uart";
				reg = <0x00206000 0x1000>;
				interrupts = <30 29 26>;
				clocks = <&clks IMX1_CLK_HCLK>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@00207000 {
				compatible = "fsl,imx1-uart";
				reg = <0x00207000 0x1000>;
				interrupts = <24 23 20>;
				clocks = <&clks IMX1_CLK_HCLK>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			pwm: pwm@00208000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx1-pwm";
				reg = <0x00208000 0x1000>;
				interrupts = <34>;
				clocks = <&clks IMX1_CLK_DUMMY>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
			};

			dma: dma@00209000 {
				compatible = "fsl,imx1-dma";
				reg = <0x00209000 0x1000>;
				interrupts = <61 60>;
				clocks = <&clks IMX1_CLK_HCLK>,
					 <&clks IMX1_CLK_DMA_GATE>;
				clock-names = "ipg", "ahb";
				#dma-cells = <1>;
			};

			uart3: serial@0020a000 {
				compatible = "fsl,imx1-uart";
				reg = <0x0020a000 0x1000>;
				interrupts = <54 4 1>;
				clocks = <&clks IMX1_CLK_UART3_GATE>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};

		aipi@00210000 {
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x00210000 0x10000>;
			ranges;

			cspi1: cspi@00213000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx1-cspi";
				reg = <0x00213000 0x1000>;
				interrupts = <41>;
				clocks = <&clks IMX1_CLK_DUMMY>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c: i2c@00217000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx1-i2c";
				reg = <0x00217000 0x1000>;
				interrupts = <39>;
				clocks = <&clks IMX1_CLK_HCLK>;
				status = "disabled";
			};

			cspi2: cspi@00219000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx1-cspi";
				reg = <0x00219000 0x1000>;
				interrupts = <40>;
				clocks = <&clks IMX1_CLK_DUMMY>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			clks: ccm@0021b000 {
				compatible = "fsl,imx1-ccm";
				reg = <0x0021b000 0x1000>;
				#clock-cells = <1>;
			};

			iomuxc: iomuxc@0021c000 {
				compatible = "fsl,imx1-iomuxc";
				reg = <0x0021c000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				gpio1: gpio@0021c000 {
					compatible = "fsl,imx1-gpio";
					reg = <0x0021c000 0x100>;
					interrupts = <11>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio2: gpio@0021c100 {
					compatible = "fsl,imx1-gpio";
					reg = <0x0021c100 0x100>;
					interrupts = <12>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio3: gpio@0021c200 {
					compatible = "fsl,imx1-gpio";
					reg = <0x0021c200 0x100>;
					interrupts = <13>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio4: gpio@0021c300 {
					compatible = "fsl,imx1-gpio";
					reg = <0x0021c300 0x100>;
					interrupts = <62>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};
			};
		};

		weim: weim@00220000 {
			#address-cells = <2>;
			#size-cells = <1>;
			compatible = "fsl,imx1-weim";
			reg = <0x00220000 0x1000>;
			clocks = <&clks IMX1_CLK_DUMMY>;
			ranges = <
				0 0 0x10000000 0x02000000
				1 0 0x12000000 0x01000000
				2 0 0x13000000 0x01000000
				3 0 0x14000000 0x01000000
				4 0 0x15000000 0x01000000
				5 0 0x16000000 0x01000000
			>;
			status = "disabled";
		};

		esram: esram@00300000 {
			compatible = "mmio-sram";
			reg = <0x00300000 0x20000>;
		};
	};
};
Commit	Line	Data
d0eb8fc5 AS	1	/*
	2	* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
d0eb8fc5 AS	12	#include "imx1-pinfunc.h"
	13
	14	#include <dt-bindings/clock/imx1-clock.h>
	15	#include <dt-bindings/gpio/gpio.h>
	16	#include <dt-bindings/interrupt-controller/irq.h>
	17
	18	/ {
7f107887 FE	19	#address-cells = <1>;
7f107887 FE	20	#size-cells = <1>;
a971c554 FE	21	/*
	22	* The decompressor and also some bootloaders rely on a
	23	* pre-existing /chosen node to be available to insert the
	24	* command line and merge other ATAGS info.
	25	* Also for U-Boot there must be a pre-existing /memory node.
	26	*/
	27	chosen {};
	28	memory { device_type = "memory"; reg = <0 0>; };
7f107887	29
d0eb8fc5 AS	30	aliases {
	31	gpio0 = &gpio1;
	32	gpio1 = &gpio2;
	33	gpio2 = &gpio3;
	34	gpio3 = &gpio4;
	35	i2c0 = &i2c;
	36	serial0 = &uart1;
	37	serial1 = &uart2;
	38	serial2 = &uart3;
	39	spi0 = &cspi1;
	40	spi1 = &cspi2;
	41	};
	42
	43	aitc: aitc-interrupt-controller@00223000 {
	44	compatible = "fsl,imx1-aitc", "fsl,avic";
	45	interrupt-controller;
	46	#interrupt-cells = <1>;
	47	reg = <0x00223000 0x1000>;
	48	};
	49
	50	cpus {
	51	#size-cells = <0>;
	52	#address-cells = <1>;
	53
	54	cpu: cpu@0 {
	55	device_type = "cpu";
	56	compatible = "arm,arm920t";
	57	operating-points = <200000 1900000>;
	58	clock-latency = <62500>;
	59	clocks = <&clks IMX1_CLK_MCU>;
	60	voltage-tolerance = <5>;
	61	};
	62	};
	63
	64	soc {
	65	#address-cells = <1>;
	66	#size-cells = <1>;
	67	compatible = "simple-bus";
	68	interrupt-parent = <&aitc>;
	69	ranges;
	70
	71	aipi@00200000 {
	72	compatible = "fsl,aipi-bus", "simple-bus";
	73	#address-cells = <1>;
	74	#size-cells = <1>;
	75	reg = <0x00200000 0x10000>;
	76	ranges;
	77
	78	gpt1: timer@00202000 {
	79	compatible = "fsl,imx1-gpt";
	80	reg = <0x00202000 0x1000>;
	81	interrupts = <59>;
	82	clocks = <&clks IMX1_CLK_HCLK>,
	83	<&clks IMX1_CLK_PER1>;
	84	clock-names = "ipg", "per";
	85	};
	86
	87	gpt2: timer@00203000 {
	88	compatible = "fsl,imx1-gpt";
	89	reg = <0x00203000 0x1000>;
	90	interrupts = <58>;
	91	clocks = <&clks IMX1_CLK_HCLK>,
	92	<&clks IMX1_CLK_PER1>;
	93	clock-names = "ipg", "per";
94	};
95
96	fb: fb@00205000 {
97	compatible = "fsl,imx1-fb";
98	reg = <0x00205000 0x1000>;
99	interrupts = <14>;
100	clocks = <&clks IMX1_CLK_DUMMY>,
101	<&clks IMX1_CLK_DUMMY>,
102	<&clks IMX1_CLK_PER2>;
103	clock-names = "ipg", "ahb", "per";
104	status = "disabled";
105	};
106
107	uart1: serial@00206000 {
108	compatible = "fsl,imx1-uart";
109	reg = <0x00206000 0x1000>;
110	interrupts = <30 29 26>;
111	clocks = <&clks IMX1_CLK_HCLK>,
112	<&clks IMX1_CLK_PER1>;
113	clock-names = "ipg", "per";
114	status = "disabled";
115	};
116
117	uart2: serial@00207000 {
118	compatible = "fsl,imx1-uart";
119	reg = <0x00207000 0x1000>;
120	interrupts = <24 23 20>;
121	clocks = <&clks IMX1_CLK_HCLK>,
122	<&clks IMX1_CLK_PER1>;
123	clock-names = "ipg", "per";
124	status = "disabled";
125	};
126
127	pwm: pwm@00208000 {
128	#pwm-cells = <2>;
129	compatible = "fsl,imx1-pwm";
130	reg = <0x00208000 0x1000>;
131	interrupts = <34>;
132	clocks = <&clks IMX1_CLK_DUMMY>,
133	<&clks IMX1_CLK_PER1>;
134	clock-names = "ipg", "per";
135	};
136
137	dma: dma@00209000 {
138	compatible = "fsl,imx1-dma";
139	reg = <0x00209000 0x1000>;
140	interrupts = <61 60>;
141	clocks = <&clks IMX1_CLK_HCLK>,
142	<&clks IMX1_CLK_DMA_GATE>;
143	clock-names = "ipg", "ahb";
144	#dma-cells = <1>;
145	};
146
147	uart3: serial@0020a000 {
148	compatible = "fsl,imx1-uart";
149	reg = <0x0020a000 0x1000>;
150	interrupts = <54 4 1>;
151	clocks = <&clks IMX1_CLK_UART3_GATE>,
152	<&clks IMX1_CLK_PER1>;
153	clock-names = "ipg", "per";
154	status = "disabled";
155	};
156	};
157
158	aipi@00210000 {
159	compatible = "fsl,aipi-bus", "simple-bus";
160	#address-cells = <1>;
161	#size-cells = <1>;
162	reg = <0x00210000 0x10000>;
163	ranges;
164
165	cspi1: cspi@00213000 {
166	#address-cells = <1>;
167	#size-cells = <0>;
168	compatible = "fsl,imx1-cspi";
169	reg = <0x00213000 0x1000>;
170	interrupts = <41>;
171	clocks = <&clks IMX1_CLK_DUMMY>,
172	<&clks IMX1_CLK_PER1>;
173	clock-names = "ipg", "per";
174	status = "disabled";
175	};
176
177	i2c: i2c@00217000 {
178	#address-cells = <1>;
179	#size-cells = <0>;
180	compatible = "fsl,imx1-i2c";
181	reg = <0x00217000 0x1000>;
182	interrupts = <39>;
183	clocks = <&clks IMX1_CLK_HCLK>;
184	status = "disabled";
185	};
186
187	cspi2: cspi@00219000 {
188	#address-cells = <1>;
189	#size-cells = <0>;
190	compatible = "fsl,imx1-cspi";
191	reg = <0x00219000 0x1000>;
192	interrupts = <40>;
193	clocks = <&clks IMX1_CLK_DUMMY>,
194	<&clks IMX1_CLK_PER1>;
195	clock-names = "ipg", "per";
196	status = "disabled";
197	};
198
199	clks: ccm@0021b000 {
200	compatible = "fsl,imx1-ccm";
201	reg = <0x0021b000 0x1000>;
202	#clock-cells = <1>;
203	};
204
205	iomuxc: iomuxc@0021c000 {
206	compatible = "fsl,imx1-iomuxc";
207	reg = <0x0021c000 0x1000>;
208	#address-cells = <1>;
209	#size-cells = <1>;
210	ranges;
211
212	gpio1: gpio@0021c000 {
213	compatible = "fsl,imx1-gpio";
214	reg = <0x0021c000 0x100>;
215	interrupts = <11>;
216	gpio-controller;
217	#gpio-cells = <2>;
218	interrupt-controller;
219	#interrupt-cells = <2>;
220	};
221
222	gpio2: gpio@0021c100 {
223	compatible = "fsl,imx1-gpio";
224	reg = <0x0021c100 0x100>;
225	interrupts = <12>;
226	gpio-controller;
227	#gpio-cells = <2>;
228	interrupt-controller;
229	#interrupt-cells = <2>;
230	};
231
232	gpio3: gpio@0021c200 {
233	compatible = "fsl,imx1-gpio";
234	reg = <0x0021c200 0x100>;
235	interrupts = <13>;
236	gpio-controller;
237	#gpio-cells = <2>;
238	interrupt-controller;
239	#interrupt-cells = <2>;
240	};
241
242	gpio4: gpio@0021c300 {
243	compatible = "fsl,imx1-gpio";
244	reg = <0x0021c300 0x100>;
245	interrupts = <62>;
246	gpio-controller;
247	#gpio-cells = <2>;
248	interrupt-controller;
249	#interrupt-cells = <2>;
250	};
251	};
252	};
253
254	weim: weim@00220000 {
255	#address-cells = <2>;
256	#size-cells = <1>;
257	compatible = "fsl,imx1-weim";
258	reg = <0x00220000 0x1000>;
259	clocks = <&clks IMX1_CLK_DUMMY>;
260	ranges = <
261	0 0 0x10000000 0x02000000
262	1 0 0x12000000 0x01000000
263	2 0 0x13000000 0x01000000
264	3 0 0x14000000 0x01000000
265	4 0 0x15000000 0x01000000
266	5 0 0x16000000 0x01000000
267	>;
268	status = "disabled";
269	};
270
271	esram: esram@00300000 {
272	compatible = "mmio-sram";
273	reg = <0x00300000 0x20000>;
274	};
275	};
276	};